DESCRIPTION TRANSMISSION DEVICE
Field
[0001] The present invention relates to a transmission device that transmits a transmission bit sequence by performing differential space time block coding on the bit sequence.
Background
[0002] In radio communications, there are many diversity techniques to improve communication quality. STBC (Space Time Block Coding) and DSTBC (Differential Space Time Block Coding) are examples of the transmission diversity techniques. In these techniques, a transmitter transmits a signal, which has undergone the space time block coding (STBC coding) or the differential space time block coding (DSTBC coding), through a plurality of transmission antennas, and therefore diversity effects are obtained. For example, in the STBC or DSTBC using two transmission antennas, two symbols are included in one block, and the STBC coding or the DSTBC coding is performed for each block. The STBC coding only uses one block, while the DSTBC coding uses the current block and its immediately-previous block. A receiver performs STBC decoding or DSTBC decoding on each block generated by the transmitter. In the STBC decoding, the receiver obtains an estimated value of a transmission path, and extracts the original symbols by the decoding process on the block. In the DSTBC decoding, the receiver extracts the original symbols by the inter-block decoding process between a block and its immediately-previous block. The STBC has more improved sensitivity characteristics as compared to the DSTBC. However, in the DSTBC decoding

process, it is unnecessary for the receiver to estimate a transmission path from a received signal. Therefore, the throughput required for the receiver in the DSTBC decoding process is reduced as compared to the STBC receiver that needs to estimate a transmission path. Accordingly, the DSTBC receiver has an advantage of simplifying its configuration. The technique as described above is disclosed in Non Patent Literature 1 listed below.
[0003] At the time of decoding a received signal, a reception device needs to extract the timing at which a modulated signal is generated (hereinafter, "symbol timing"). When a transmission-reception device performs filtering through a Nyquist filter, a modulated signal is not interfered with by its adjacent modulated signal at the symbol timing. However, at timings other than the symbol timing, the modulated signal is affected by intersymbol interference. In a case where a clock of a transmission device and a clock of a reception device are synchronized with each other, it is unnecessary to perform the process of extracting the symbol timing. However, in radio communications, the clocks of the transmission device and the reception device cannot be synchronized with each other. Therefore, a method is necessary, in which the phase of the reception device is synchronized with the clock of the transmission device to recover the symbol timing
(hereinafter, "BTR (Bit Timing Recovery) method"). As the BTR method, a multiplier tank method is described in Non Patent Literature 2. In the multiplier tank method, an I-phase component and a Q-phase component, which are extracted from a received signal after having undergone quadrature detection, are individually squared and added together to calculate a power value. The power value is shaped into a clock waveform. A phase component of the

clock waveform is calculated by DFT (Discrete Fourier Transformation) so as to extract the symbol timing. The multiplier tank method does not need the known signals such as a preamble or a SW (Sync Word), and can process the
> entire received signal. This makes it possible to perform
the timing recovery at a high speed. As is the case with
the DSTBC, even when signal points of the known signals are
not constant in each frame due to differential coding, the
symbol timing recovery by the multiplier tank method is
i still effective.
Citation List Non Patent Literatures [0004] Non Patent Literature 1: V. Tarokh, H. Jafarkhani,
> "A differential Detection Scheme for Transmit Diversity",
IEEE Journal on Selected Areas in Communications, Vol. 18,
pp. 1169-1174, July 2000.
Non Patent Literature 2: Yoichi Matsumoto, Masahiro Morikura, Shuzo Kato, "A Burst Mode All-Digital High Speed i Clock Recovery Circuit -Block Clock Recovery Scheme-", The transactions of the Institute of Electronics, Information and Communication on Engineers, B-II Vol. 75-B-II No. 6, pp. 354-362, June 1992.
> Summary
Technical Problem
[0005] In the conventional-technique multiplier tank method, an I-phase component and a Q-phase component of a received signal are individually squared, and added i together to calculate a power value. The power value is
shaped into a clock waveform. The DFT process is performed on the clock waveform to calculate a phase. Thereafter, the phase is averaged in order to reduce variations in the

phase due to the influences such as noise. When the power of a symbol is not constant, the clock waveform becomes irregular, which also causes the phase calculation results to vary. Therefore, when a modulation method, which results in smaller variations in power, is used, then the symbol timing is recovered by the multiplier tank method with higher accuracy. Accordingly, the symbol timing can be recovered with high accuracy when the multiplier tank method is used as the BTR method for a modulation method by which a modulated signal has constant power, such as QPSK
(Quadrature Phase Shift Keying) or DQPSK (Differential QPSK). However, when DSTBC differential coding is performed on a signal, the signal after having undergone the differential coding does not have constant power although the QPSK modulation method is used. Consequently, there is a problem of degraded accuracy in symbol timing recovery using the multiplier tank method.
[0006] The present invention has been achieved to solve the above problems, and an object of the present invention is to provide a transmission device that is capable of reducing variations in the amplitude between signal points of a transmission signal after having undergone DSTBC differential coding, and improving accuracy in symbol timing recovery in a reception device that recovers a symbol timing by the multiplier tank method.
Solution to Problem
[0007] To solve the problems described above and to achieve the object, a transmission device comprises a mapping processing unit to perform QPSK modulation on transmission bits, and a differential space time block coding unit to perform differential space time block coding on a modulated signal to generate a differential space time

block coded signal. The transmission device also comprises an initial-value setting unit to provide the differential space time block coding unit with elements in a combination of two symbols, by which a differential space time block coded signal to be generated can have two amplitude patterns, as a signal initial value to be used instead of a generated differential space time block coded signal when the differential space time block coding unit starts the differential space time block coding.
Advantageous Effects of Invention
[0008] The transmission device according to the present invention has an effect where the accuracy in symbol timing recovery in a reception device that recovers a symbol timing by the multiplier tank method can be improved.
Brief Description of Drawings
[0009] FIG. 1 is a diagram illustrating a configuration example of a transmission device according to a first embodiment.
FIG. 2 is a flowchart illustrating an example of an operation of an initial-value setting unit.
FIG. 3 is a diagram illustrating signal points of a signal having undergone DSTBC coding.
FIG. 4 is a diagram illustrating signal points of a signal output from a DSTBC coding unit.
FIG. 5 is a diagram illustrating amplitudes and phases of respective signal points illustrated in FIG. 4.
FIG. 6 is a diagram illustrating initial values provided by the initial-value setting unit to the DSTBC coding unit.
FIG. 7 is a diagram illustrating a configuration example of a transmission device according to a second

embodiment.
FIG. 8 is a diagram illustrating a hardware configuration example of the initial-value setting unit.
FIG. 9 is a diagram illustrating a hardware configuration example of the initial-value setting unit.
Description of Embodiments
[0010] A transmission device according to embodiments of the present invention is described in detail below with reference to the accompanying drawings. The embodiments do not limit the present invention.
[0011]
First embodiment
FIG. 1 is a diagram illustrating a configuration example of a transmission device according to a first embodiment of the present invention. A transmission device 1 according to the present embodiment includes a mapping unit 11, a DSTBC coding unit 12, an initial-value setting unit 13, filtering units 14 and 15, and quadrature modulation units 16 and 17. The transmission device 1 is a transmitter of a radio communication device, for example.
[0012] In the transmission device 1, the mapping unit 11 that is a mapping processing unit maps each of input transmission bits at any point on the I-Q plane (complex plane) to generate a modulated signal. The mapping unit 11 in the present embodiment performs QPSK modulation on the transmission bits. The DSTBC coding unit 12 that is a differential space time block coding unit generates a DSTBC signal by using a QPSK signal that is a modulated signal generated by the mapping unit 11, and using a DSTBC-coded signal generated by the immediately-previous DSTBC coding
(differential space time block coding). The initial-value setting unit 13 generates a DSTBC signal as an initial

value necessary for the DSTBC coding unit 12 to initially perform the DSTBC coding. The filtering units 14 and 15 oversample a DSTBC signal output from the DSTBC coding unit 12, and filter the oversampled DSTBC signal by using a
5 shaping filter. The quadrature modulation units 16 and 17 modulate a DSTBC signal, having been filtered by the filtering units 14 and 15, respectively, to a carrier frequency or the like, and also amplify the signal power. [0013] The whole process of transmitting transmission
D bits by the transmission device 1 illustrated in FIG. 1 is described next. Transmission bits to be input to the transmission device 1 constitute a bit sequence including ^O's and H's, such as a bit sequence in a random pattern, or an information bit sequence.
5 [0014] The mapping unit 11 performs QPSK primary
modulation on the input transmission bits. The QPSK is a modulation method to modulate two bits into one symbol. The mapping unit 11 maps transmission bits as signal points on the I-Q plane in accordance with the following equation
D (1) to generate a modulated signal. [0015] [Equation 1]
[0016] In the equation (1), "A" represents an amplitude 5 value of a modulated signal, and "j" represents an
imaginary unit. "A" is defined as 1/V2 in the following

descriptions, while any value can be used as "A". The equation (1) shows two transmission bits on the left side of the colon, while showing a modulated signal on the right side of the colon. Combinations of four transmission-bit patterns with four modulated signals are not limited to those expressed in the equation (1). Any combination can be used.
[0017] The DSTBC coding unit 12 performs the DSTBC coding on a modulated signal output from the mapping unit 11 to generate a DSTBC signal. The DSTBC coding is performed on two symbols of a modulated signal as one block. Therefore, when the first symbol of a k-th block is represented as skfi and the second symbol of the k-th block is represented as skf2/ a modulated signal matrix Sk is expressed by the following equation (2). In the equation (2), "s*" represents a complex conjugate of "s". [0018] [Equation 2]
Sk = _Sk'l Sf • • -(2)
Sk,2 Sk,l _
[0019] A DSTBC signal matrix Ck of the k-th block is expressed by the following equation (3) when, among the DSTBC signals of the k-th block, a DSTBC signal of the first symbol and a DSTBC signal of the second symbol are represented as ck,i and ckr2r respectively. [0020] [Equation 3]
Ck =\_°k'l CH •••(3)
[0021] The DSTBC coding unit 12 generates the DSTBC signal matrix Ck of the k-th block, which is expressed by the equation (3), by performing matrix multiplication using

a DSTBC signal matrix Ck-i of a (k-l)-th block and the modulated signal matrix Sk of the k-th block. This process is expressed by the following equation (4). An output of the DSTBC coding unit 12 is input back to the DSTBC coding unit 12, because Ck-i is needed to generate the DSTBC signal matrix Ck.
[0022]
[Equation 4]
Ck = SkCk_, • • -(4)
[0023] In the equation (4) that expresses the process of generating the DSTBC signal matrix Ck, multiplication, addition, and subtraction are performed as matrix computation to calculate all elements. However, it is also possible that, for example, only two elements of Ck,i and Ck,2 are calculated by matrix computation to derive c*k,i and -c*k,2 from complex conjugates and sign inversion of Ck,i and ck,2, so as to reduce the amount of computation.
[0024] A matrix C0 that is needed for generating a DSTBC signal matrix Ci, that is, the matrix C0 that is needed for initially generating a DSTBC signal matrix since the start of inputting a transmission bit sequence, cannot be obtained from the output of the DSTBC coding unit 12. Therefore, the initial-value setting unit 13 provides c0,i and c0,2 among the elements of the matrix C0 as initial values to the DSTBC coding unit 12. The DSTBC coding unit 12 uses the initial values c0,i and c0,2 having received from the initial-value setting unit 13 to generate the matrix C0, and then uses the generated matrix C0 to generate the DSTBC signal matrix Ci. It is possible that the initial-value setting unit 13 provides the initial values c0,i and c0,2 to the DSTBC coding unit 12 at any timing, for example, at the point in time when the DSTBC coding unit 12 starts generating a DSTBC signal, or at the timing at which the

leading transmission bit in a communication frame is input. It is also possible that the initial-value setting unit 13 simply stores therein the initial values, and the DSTBC coding unit 12 reads these initial values from the initial-value setting unit 13 as needed. FIG. 2 is a flowchart illustrating an example of the operation of the initial-value setting unit 13. As illustrated in FIG. 2, the initial-value setting unit 13 confirms whether a specified condition is satisfied (Step Sll). When the specified condition is not satisfied (NO at Step Sll), the initial-value setting unit 13 continues the confirmation operation. It can be considered that the specified condition is that, for example, the DSTBC coding unit 12 is detected to have started generating a DSTBC signal, or the leading transmission bit in a communication frame is input to the mapping unit 11 or to the DSTBC coding unit 12. However, the specified condition is not limited thereto. When the specified condition is satisfied (YES at Step Sll), the initial-value setting unit 13 provides the initial values c0,i and c0f2 to the DSTBC coding unit 12 (Step S12) . That is, upon determining that the specified condition is satisfied, the initial-value setting unit 13 reads the initial values c0,i and c0,2 stored in its storage circuit such as an internal memory, and outputs the read initial values Co,i and Co,2 to the DSTBC coding unit 12. [0025] In principle, it is possible to set the initial values co,i and Co,2 at any points on the complex plane. However, power of one block needs to be equal to the sum of power of two symbols of a modulated signal. That is, the initial values need to satisfy the following equation (5). Signal points that can be taken for an output of the DSTBC coding unit 2 are determined based on these initial values. However, there are an enormous number of combinations of

initial values which satisfy the equation (5). Therefore, it is desirable to find out and use a combination of initial values, which results in appropriate signal points for the transmission and reception process. [0026] [Equation 5]
I |2 I |2
\c + \c = 1 ■ ■ ■ (5)
| 0,11 | 0,21 X \ J '
[0027] For example, when Co,i is set at 1 and Co,2 is set at 0, it satisfies the condition shown by the above equation (5). In this case, signal points can be taken for an output of the DSTBC coding unit 12 as illustrated in FIG. 3. As illustrated in FIG. 3, when Co,i is set at 1 and Co,2 is set at 0, the signal points of the DSTBC signal have three amplitude patterns. That is, there are signal points [2], [4], [6], and [8] with a larger amplitude, signal points [3], [5], [7], and [9] with a smaller amplitude than the above signal points, and a signal point [1] with 0 amplitude. This shows significant variations in the amplitude between symbols. Therefore, when a reception device that receives a DSTBC signal performs timing recovery by the multiplier tank method, the symbol timing is recovered less accurately. Accordingly, in the present embodiment, in order to reduce the variations in the amplitude between symbols, the initial-value setting unit 13 sets the initial values, by using of which the signal points of a DSTBC signal can have two amplitude patterns. FIG. 4 illustrates an example of the DSTBC signal whose signal points have two amplitude patterns. Signal points [1] to [12] illustrated in FIG. 4 are smaller-amplitude signal points, while signal points [13] to [24] also illustrated in FIG. 4 are larger-amplitude signal points. The amplitude and phase of each signal point illustrated in

FIG. 4 are as illustrated in FIG. 5. The values of an amplitude Bi and an amplitude B2 illustrated in FIG. 5 are expressed by the following equation (6). [0028] [Equation 6]
B = | 1
1 "VI + 2(cos(7r/6) + cos(7r/3))2
, •••(6)
2(cos(7r/6) + cos(7r/3))2
2 "\)l + 2(cos(7r/6) + cos(7r/3))2
[0029] Each of the signal points [1] to [24] illustrated
in FIG. 4 and FIG. 5 can also be expressed as "Bi (cos (n7t/6) +j -sin (n7t/6) ) ", "B2 (cos (n7r/6+7r/12)+j -sin (n7r/6+7r/12 ) ) ", "Bi (cos (n7r/6+7r/4) +j -sin (n7r/6+7r/4) ) ", or "B2 (cos (n7r/6+7r/3) +j -sin (n7r/6+7r/3) ) " .
[0030] FIG. 6 is a diagram illustrating possible combinations of the signal points, among the signal points illustrated in FIG. 4 and FIG. 5, as the initial values Co,i and Co,2 to be provided by the initial-value setting unit 13 to the DSTBC coding unit 12. It is possible that the initial-value setting unit 13 uses, as the initial values, any combination of signal points corresponding to an intra-block symbol-combination number illustrated in FIG. 6. Some of the combinations of signal points illustrated in FIG. 6, which are denoted by the intra-block symbol-combination numbers 7 to 24, are equivalent to those obtained by rotating the other combinations of signal points denoted by the intra-block symbol-combination numbers 1 to 6 about the origin point on the complex plane by a phase of nm/2 (m=l, 2, 3). By setting any of the combinations illustrated in FIG. 6 is set as the initial values c0,i and c0f2, the DSTBC coding unit 12 generates a

DSTBC signal as illustrated in FIG. 4 and FIG. 5, so that the signal points can have two amplitude patterns. Other than the DSTBC signals illustrated in FIG. 4 and FIG. 5, DSTBC signals obtained by rotating the DSTB signal points illustrated in FIG. 4 and FIG. 5 about the origin point on the complex plane in the counterclockwise direction by a
(7t/4) phase, are also corresponding to the DSTBC signal whose signal points can have two amplitude patterns. In addition to the combinations of signal points as the initial values c0,i and c0f2 illustrated in FIG. 6, it is also possible to use a combination of signal points obtained by rotating each signal point illustrated in FIG. 6 about the origin point on the complex plane in the counterclockwise direction by a phase of an integral multiple of 7r/4 (0, 7t/4, K/2, 3TZ/A, ■ ■ •) . In this case also, there are two amplitude patterns of a DSTBC signal generated by the DSTBC coding unit 12. Therefore, it suffices that the initial-value setting unit 13 selects the initial values co,i and Co,2 from among the combinations of signal points, which correspond respectively to the intra-block symbol-combination numbers 1 to 6 illustrated in FIG. 6, and combinations of signal points obtained by rotating the above combinations about the origin point on the complex plane in the counterclockwise direction by a phase of n7r/4 (n=0, 1, • • •, 7) and outputs the selected initial values Co,i and Co,2 to the DSTBC coding unit 12.
[0031] The DSTBC signal generated by the DSTBC coding unit 12 is input to the filtering units 14 and 15. That is, the DSTBC coding unit 12 inputs a set of two symbols, either ck,i, -c*kf2 or c\,i, ckf2, to the filtering unit 14, while inputting the other set of two symbols to the filtering unit 15.

[0032] The filtering units 14 and 15 filter their respective input symbols using a shaping filter such as a Nyquist filter, and then output the filtered symbols to the quadrature modulation units 16 and 17, respectively. The signals, output from the filtering units 14 and 15, are converted to, for example, a carrier frequency in the quadrature modulation units 16 and 17, respectively. The converted signals undergo signal power amplification using a transmission amplifier or the like, and thereafter are output as a transmission signal. The quadrature modulation units 16 and 17 do not necessarily modulate the signal into a carrier frequency. It is also possible that the quadrature modulation units 16 and 17 output the signal as it is as a baseband signal, or modulate the signal into an intermediate frequency, and then output the modulated signal. Because the DSTBC is the transmission diversity technique, the transmission device in the present embodiment is configured to use two transmission antennas. However, it is allowable that the transmission device is configured by either one of the two blocks of the filtering units 14 and 15 intended for two transmission antennas, and by the corresponding quadrature modulation unit 16 or 17. In this case, a transmission signal is transmitted from a single transmission antenna.
[0033] As described above, the transmission device in the present embodiment uses initial values, by using of which signal points of a DSTBC signal can have two amplitude patterns, as the initial values to be used for DSTBC coding. This reduces variations in the amplitude between the signal points. Therefore, a reception device that receives a DSTBC signal transmitted by the transmission device in the present embodiment can recover the symbol timing with high accuracy by the multiplier tank

method. That is, the transmission device in the present embodiment can improve accuracy in the symbol timing recovery in a reception device that recovers the symbol timing by the multiplier tank method.
[0034]
Second embodiment
FIG. 7 is a diagram illustrating a configuration example of a transmission device according to a second embodiment of the present invention. A transmission device la according to the second embodiment is different from the transmission device 1 of the first embodiment in the configuration of the mapping processing unit that performs QPSK modulation on a transmission bit sequence. The transmission device la can still obtain the same effects as those in the first embodiment. In the configuration of the transmission device la, the mapping unit 11 and the DSTBC coding unit 12, which are included in the transmission device 1 according to the first embodiment illustrated in FIG. 1, are replaced with mapping units 21 and 22 and a DSTBC coding unit 12a. Further, an S/P (Serial/Parallel) conversion unit 20 is added at the previous stage of the mapping units 21 and 22. In the transmission device la, the S/P conversion unit 20, and the mapping units 21 and 22 constitute the mapping processing unit. Common constituent elements to those in the transmission device 1 according to the first embodiment are denoted by same reference signs in FIG. 7. Descriptions of the common constituent elements to those in the transmission device 1 are omitted.
[0035] The whole process of transmitting transmission bits by the transmission device la is described next. Similarly to the first embodiment, transmission bits to be input to the transmission device la are a bit sequence including ^O's and H's, such as a bit sequence in a random

pattern or an information bit sequence.
[0036] In the transmission device la, Sk,i and Sk,2 in the equation (2) described in the first embodiment are generated correspondingly by different mapping units.
[0037] In the transmission device la, transmission bits are input to the S/P conversion unit 20. The S/P conversion unit 20 outputs two leading bits among four bits to be transmitted by one block of a DSTBC signal, to the mapping unit 21, while outputting the other two bits to the mapping unit 22. That is, the S/P conversion unit 20 is a bit allocation unit that allocates the transmission bits to a first bit sequence and a second bit sequence.
[0038] The mapping units 21 and 22 are a first mapping unit and a second mapping unit, respectively, and perform QPSK primary modulation on the input transmission bits in the same manner as the mapping unit 11 in the first embodiment. It is also allowable that two trailing bits, among the four bits to be transmitted by one block, are allocated to the mapping unit 21, while two leading bits of the four bits are allocated to the mapping unit 22. That is, it is allowable that the S/P conversion unit 20 outputs, two leading bits among the four bits to be transmitted by one block, to the mapping unit 22, while outputting the other two bits to the mapping unit 21. The DSTBC coding unit 12a performs DSTBC coding on the leading symbol and the trailing symbol of the block, which are input from the mapping units 21 and 22, respectively, to generate a DSTBC signal. The procedure to generate a DSTBC signal by the DSTBC coding unit 12a, the initial-value setting method to be performed by the initial-value setting unit 13, and the initial values to be set are the same as those in the first embodiment. The DSTBC signal generated by the DSTBC coding unit 12a is input to the filtering units 14 and 15. In the

same manner as the DSTBC coding unit 12 in the first embodiment, the DSTBC coding unit 12a inputs a set of two symbols, either ck,i and -c*kf2 or c*k,i and ckf2, to the filtering unit 14, while inputting the other set of two symbols to the filtering unit 15.
[0039] In the transmission device la according to the present embodiment, signal points, at which the DSTBC signal having undergone DSTBC coding can have only two amplitude patterns, can be obtained in the same manner as the transmission device 1 in the first embodiment. This reduces variations in the amplitude between the signal points. Therefore, the transmission device la can improve accuracy in the symbol timing recovery in a reception device that recovers the symbol timing by the multiplier tank method.
[0040] The initial-value setting unit 13 that constitutes the transmission device 1 in the first embodiment, and that constitutes the transmission device la in the second embodiment is implemented by hardware illustrated in FIG. 8 or FIG. 9. FIG. 8 illustrates a configuration example when the initial-value setting unit 13 is implemented by dedicated hardware. FIG. 9 illustrates a configuration example when the initial-value setting unit 13 is implemented by a processor (which is also referred to as "CPU (Central Processing Unit)", "processing device", "computing device", "microprocessor", "microcomputer", or "DSP (Digital Signal Processor)") that executes a program stored in a memory.
[0041] In a case where the initial-value setting unit 13 is implemented by a processing circuit 51 that is dedicated hardware and illustrated in FIG. 8, the processing circuit 51 includes a storage circuit 52, a determination circuit 53, and an output circuit 54. The storage circuit 52

stores therein the initial values to be provided to the DSTBC coding unit 12 or 12a. The determination circuit 53 determines whether a specified condition is satisfied. The output circuit 54 outputs the initial values stored in the storage circuit 52 to the DSTBC coding unit 12 or 12a when the determination circuit 53 determines that the specified condition is satisfied. The processing circuit 51 is, for example, a single circuit, a combined circuit, a programmed processor, a parallel-programmed processor, an ASIC
(Application Specific Integrated Circuit), an FPGA (Field Programmable Gate Array), or a combination of any of them.
[0042] In a case where the initial-value setting unit 13 is implemented by a processor 61, a memory 62, and an output circuit 63, all of which are illustrated in FIG. 9, the processor 61 reads a program from the memory 62, which causes the processor 61 to operate as the initial-value setting unit 13 that outputs the initial values to the DSTBC coding unit 12 or 12a when the specified condition is satisfied, and then executes the read program. The memory 62 has stored therein the program for the processor 61 to operate as the initial-value setting unit 13, and also has stored therein the initial values to be provided to the DSTBC coding unit 12 or 12a. The memory 62 is, for example, a non-volatile or volatile semiconductor memory such as a RAM (Random Access Memory), a ROM (Read Only Memory), a flash memory, an EPROM (Erasable Programmable Read Only Memory), or an EEPROM (Electrically Erasable Programmable Read Only Memory), a magnetic disc, a flexible disk, an optical disc, a compact disc, a mini disc, or a DVD
(Digital Versatile Disc). The output circuit 63 is a circuit that outputs the initial values read from the memory 62 to the DSTBC coding unit 12 or 12a.
[0043] The mapping units 11, 21, and 22 are implemented

by a symbol mapper. The DSTBC coding units 12 and 12a are implemented by an encoder. The filtering units 14 and 15 are implemented by a filter. The quadrature modulation units 16 and 17 are implemented by a modulator. The S/P conversion unit 20 is implemented by a serial/parallel conversion circuit.
[0044] The configurations described in the above embodiments are merely examples of the contents of the present invention. These configurations can be combined with other known techniques, or a part of the configurations can be omitted or modified without departing from the scope of the present invention.
Reference Signs List
[0045] 1, la transmission device, 11, 21, 22 mapping unit, 12, 12a DSTBC coding unit, 13 initial-value setting unit, 14, 15 filtering unit, 16, 17 quadrature modulation unit, 20 S/P conversion unit.

CLAIMS
1. A transmission device comprising:
a mapping processing unit to perform QPSK modulation on transmission bits;
a differential space time block coding unit to perform differential space time block coding on each block, where two symbols of a modulated signal generated by the mapping processing unit are included in one block, and to generate a differential space time block coded signal; and
an initial-value setting unit to provide, when the differential space time block coding unit starts the differential space time block coding, the differential space time block coding unit with elements in a combination of two symbols, by which a differential space time block coded signal that is to be generated by the differential space time block coding unit can have two amplitude patterns, as a signal initial value to be used instead of a generated differential space time block coded signal.
2. The transmission device according to claim 1, wherein
the mapping processing unit includes
a bit allocation unit to allocate transmission bits to a first bit sequence and a second bit sequence,
a first mapping unit to perform QPSK modulation on the first bit sequence, and
a second mapping unit to perform QPSK modulation on the second bit sequence, and
the differential space time block coding unit performs differential space time block coding on each block, where one symbol of a modulated signal generated by the first mapping unit, and one symbol of a modulated signal generated by the second mapping unit are included in one block.

3. The transmission device according to claim 1 or 2,
wherein when an average amplitude of the modulated signal
is 1/V2, "n" is an integer, "j" is an imaginary unit, and
Bi and B2 are expressed by a following equation (1),
[Equation 1]
E_\ 1
1 V 1 + 2(COS(TT/6)+ COS(TT/3))2
, •••(!)
2(cos(^/6) + cos(^-/3))2
2 ~ \ 1 + 2(COS(TT/6) + COS(TT/3))2
the differential space time block coding unit generates a following signal as the differential space time block coded signal,
Bi (cos (n7t/6) + j -sin {im/6) ) ,
B2 (cos (n7r/6+7r/12) +j -sin (n7r/6+7r/12) ) ,
Bi (cos (n7t/6+7t/4) +j -sin (n7t/6+7t/4) ) , or
B2 (cos (n7t/6+7t/3) +j -sin (n7t/6+7t/3) ) .
4. The transmission device according to claim 1, 2, or 3
wherein when an average amplitude of the modulated signal
is 1/V2, "n" is an integer, "j" is an imaginary unit, and
Bi and B2 are expressed by a following equation (2),
[Equation 2]
B \ 1
1 V 1 + 2(cos(^/6)+ cos(^/3))2
, •••(2)
2(cos(^/6) + cos(^-/3))2
2 ~ \ 1 + 2(cos(^/6)+COS(TT/3))2
the initial-value setting unit provides the differential space time block coding unit with any one of following combinations [1] to [6], and combinations obtained by rotating each of the following combinations [1] to [6] by a phase of nm/2 (m=l, 2, 3), as the signal

initial value.
[1] Bi (cos (0)+j -sin(O) ) and B2 (cos (TT/4 ) + j -sin(7i/4) ) [2] Bi (cos (0)+j -sin(O) ) and B2 (cos (3TT/4 ) + j -sin (37T/4 ) ) [3] Bi (cos (7t/6) +j -sin (71/6) ) and B2 (cos (1371/12)+j -sin(137r/12) ) [4] Bi (cos (7i/6) +j -sin (71/6) ) and B2 (cos (1971/12)+j -sin (1971/12) )
[5] Bi (cos (7i/3)+j -sin(7r/3) ) and B2 (cos (57i/12 ) + j -sin (5TT/12 ) ) [6] Bi (cos (7t/3) +j -sin (TT/3) ) and B2 (cos (2 3TT/12)+J -sin(2 37r/12) )