2
FIELD OF INVENTION
The present invention relates to a method of triggering and monitoring of
thyristor valves for static VAR Compensation (SVC) applications. More
particularly, the present invention relates to a triggering and real time monitoring
system for SVC thyristor valves.
BACKGROUND OF THE INVENTION
In electrical power systems, electrical load comprises active and reactive
components. If the reactive component of the load is compensated for by
providing shunt compensation, then the steady state transmittable power can be
increased. In dynamic loads, it is imperative to use a static VAR compensation
device so that the fast changing loads can be compensated effectively. These
devices are fast acting and employ solid state switching devices like thyristors.
In SVC, normally a plurality of thryristors are used in an anti-parallel
configuration. A typical configuration is shown in Figure 1. When a plurality of
thyristors are used in series, it is the general practice to have a few redundant
thyristors, so that a single failure does not result in a disruption of the entire
system. However, it is important to monitor these devices continuously so that
corrective or protective action can be taken as required.
As there are a number of thyrrstors connected in series, it is also essential to
trigger all of them simultaneously to prevent the thyristors from being unequally

3
stressed. Each of these thyristors is at a different voltage level and hence they
need to be electrically isolated from the control electronics at ground potential.
In order to meet these requirements, the thyristors are provided with an
electronic circuit called the Thyristor Electronics that is powered by the voltage
across the thyristor. The Thryristor Electrodes is interfaced to the control
electronics at ground potential by fibre optic cables. These fibre optic cables
carry the triggering and monitoring sign a is between the Thyristor Electronics and
the control electronics.
The convention at triggering and monitoring system for thyristor valves is shown
in Figure - 2. These systems have individual thyristor electronics for each
thyristor and separate triggering and monitoring cables for each thynstor. Also a
separate triggering source is required for each thyristor and this does not have
any redundancy.
The monitoring systems of the prior art basically constitute non-real time
systems, which fail to assure accurate response times as the processing of
signals by a CPU is sequential and slow. Faults are merely recorded on a
printout, as only one printer is available to denote the status of the valve. Prior
art system is very bulky, expensive and less reliable (due to use of a large
number of components). It is also susceptible to noise and requires larger pulse
monitoring periods. Also no provision exists with the controller for data transfer
to enable a centralized display of status.

5
SUMMARY OF THE INVENTION
Accordingly, there is provided a triggering and real time monitoring system for
SVC-thyristor valves, the thyristor valve (V) comprising a plurality of anti-parallel
thyrsitors (T) having a plurality of monitoring cables (RC), the number of
thyrsitors (T) and the number of monitoring cables (RC) being atleast one more
than the number of the thyrsitor valves (V), the system comprising a controller
for receiving voltage (V) and current (I) signals from a power source (S); a
triggering and monitoring device for receiving control and commands from the
controller, the triggering and monitoring device being interfaced to the thyrsitor
valves by atleast one optic cables and a monitoring cable for triggering and
monitoring via a thyrsitor controlled reactor, coded data received from the TCR
being decoded, processed and sent to a PC connected with a printer for display.
The thyristor valve comprises a number of anti-parallel connected thyristors In
series. Each level has a pair of anti - parallel thyristors, a snubber, a voltage
sharing resistor and a Thyristor Electronics. In a preferred embodiment, two
thyristors share one Thyristor Electronics. The thyristors that share one Thyristor
Electronics is selected such that the voltages on the Thyristor Electronics are less
than 100 V, which helps to ease the design of the Thyristor Electronics. Such a
configuration also results in reduction in the number of thyristor electronics and
the monitoring cables. The proposed system has only "N+1" thyristor electronics
and monitoring cables in the conventional system a thyristor valve comprising
"N" anti parallel levels has "2N" thyristors, and hence "2N" thyristor electronics
and monitoring cabtes reduces the number to almost half. This configuration also
helps to obtain a more detailed information of the level.

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The use of FPGAs in the triggering circuit helps in generating windows of time
and sending coded pulses in these windows to trigger and monitor the pulses.
The use of cables with multiple inputs and multiple outputs helps in reducing the
number of triggering sources. As shown In the example only one triggering
source is adequate to trigger 7 thyristors, a 100% redundancy is also achieved
by this configuration by sending the triggering pulses through two sources
simultaneously. To monitor the health of the trigger sources some of the
monitoring pulses are transmitted only through a selected source.
The use of FPGAs and microcontrollers help in latching and processing the data
in real time in order to have a real time control over the monitoring system. The
window generated are used to segregate the data coming from the thyristor
valve. These windows are also used to generate interrupts for the micro-
controller to enable real time data collection and processing,
The present invention thus provides a novel method of sending coded monitoring
pulses along with the triggering pulses is used. The coding of the pulses are
carried out by a triggering module of the control electronics using Field
Programmable Gate Arrays (FPGAs), Such coded pulses are converted to optical
pulses and sent to the Thyristor Electronics. The Thyristor Electronics decodes
these pulses and triggers the thyristors. The Thyristor Electronics further sends
feedback monitoring pulses to the control electronics via return fibre optic cables.
The feedback pulses are decoded FPGAs and interfaced to microcontrollers to
obtain a detailed status of the health of the thyristors, the fibre optic cables, the
thyristor electronics and the triggering circuit in real time. This real time
monitoring helps in taking protective action before any cascading of failures
results. The health of the system is then sent to a PC through a serial link and

7
provided to the operator though a Graphical User Interface (GUI). This
information is also stored in files on the PC for future analysis and record. The
data is also printed using a standard parallel printer for the records.
BRIEF DESCRIPTION OF THE ACCOMPANYING DRAWINGS
Figure 1 - shows a conventional configuration for Thyristor Electronics in SVC.
Figure 2 - shows a diagram for a typical Thyristor Electronics catering to two
anti-parallel thyristors.
Figure 3 - shows a configuration of shared Thyristor Electronics for two anti-
parallel thyrtstors.
Figure 4 - shows Thyristor Controlled reactor (TCR) for SVC according to the
present invention.
Figure 5 - shows a 2/7 Fibre optic cable used to trigger 7 thyristor in the positive
direction according to the present invention,
Figure 6 - shows a block diagram of the real time triggering and monitoring
system for a SVC thyristor valve system according to the present
invention.
Figure 7 - shows the main page of the thyristor monitoring GUI according to
present invention.
Figure 8 - shows the details of thyristor failure in R-phase.

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DETAILED DESCRIPTION OF A PREFERRED EMBODIMENT OF
THE PRESENT INVENTION
The configuration of Figure - 1 shows a thyristor valve comprising "N" anti
parallel levels has "2N" thyristors (T), and hence "2N" thyristor electronics (TE)
and monitoring cables (RC). For example, 4 levels of anti-parallel thyristors
require 8 thyristor electronics (TE) and 8 return fibre optic cables (RC).
As shown in Figure - 2, the controller (1) generates the Input control pulses
synchronized to the line voltage- With respect to the control voltage firing pulses,
the status pulses and LED pulses are generated. At the rising edge of the control
pulse a firing pulse is generated. The firing pulse is a double pulse, two 5μs
pulses separated by 18 us. At falling edge of the control pulse a status pulse is
generated. The static pulse is a 5ΜS pulse. After a time interval of 120μs an LED
pulse (a 5μs pulse) is generated. The Thyristor Electronics echoes the status and
LED pulses to the control electronics. To capture these echoed pulses, windows
are generated in the control electronics. The status window is a 100μs pulse
generated at the falling edge of the control pulse. The LED window is a 100μs
pulse generated at the falling edge of the status pulse. The OVP window is a
100μs pulse generated 30μs after the rising edge of the control pulse. In the
negative half cycle this same pulse pattern is generated with respect to the
corresponding control pulse.
As shown in Figure - 3, a thyristor valve (V) at "N" anti parallel levels has "N+1"
thyristor electronics (TE) and "N+1" monitoring cables (RC), Here 4 levels of
anti-parallel thyristors require 5 thyristor electronics and 5 return fibre optic
cables.

9
As shown in Figure - 4, the TCR (4) is normally connected in delta with the
thyristor valve (V) connected in series with the main reactor (L), The main
reactor is split into two and is connected on either side of the thyristor valve (V),
The thyristor valve (V) as shown in Figure - 4 comprises a number of anti-
parallel thyristors (T) connected in series; a saturated reactor (R ) in series to
limit the di/dt; and an arrestor (A) in parallel to limit the voltage across the
thyristor valve.
As shown in Figure - 5, in the conventional system, it would require 7 sources to
trigger 7 thyristors and there is no provision for redundancy, one trigger source
is adequate to trigger 7 thyristors, 100% redundancy can be provided by using
two sources.
As shown in Figure - 6, a controller (1) receives voltage (V) and current (I)
signal for a power source (S) and issues control pulses and block/deblock
commands to a triggering and monitoring device (2). The triggering and
monitoring device (2) is interfaced to the thyristor valves (3) via 3 thyristor
controlled reactor (3a) by a 2/7 fibre optic cables (4) for triggering and 1/1
cables (5) for monitoring. The data received from the thyristor valves are
decoded, processed and sent to a PC (6) and printer (7) connected to it
As shown in Figure - 7, on the main page of GUI (8), the thyristor valves for
each phase is represented as a single block. The colour of this block is green if
all the components of that particular phase are healthy. If there is a minor
problem on that phase, which does not warrant a disruption of the SVC system,

10
then It turns yellow. This problem can be attended to during a plant shut down
or maintenance. If there is a serious problem in any of the phases then it turns
red.
As shown in Figure - 8, the GUI page (8) indicates the exact location of the fault
by changing the colour of the component that has failed.
The triggering system is configured based on the concept that the conduction
interval is the time interval during which the thyristor has to be retriggered if it
becomes off. As this time interval is small the remaining time interval can be
used to communicate the status of the thynstors and fibre optic cables to the
control electronics. Hence the firing pulse and the other monitoring pulses are
coded as shown in Figure - 6. The firing pulse is a double puise as described
earlier. This indicates the start of conduction interval to the thyristor electronics
on receipt of the firing pulse triggers the thyristor and set a flip-flop to indicate
start of conduction interval. The status pulse is used to indicate end of
conduction interval. The thyrfstor electronics on receipt of the status pulse resets
the flip-flop to indicate end of the conduction interval.
If one of the thyristor does not get the triggering pulse then as tfte Voltage
across the other thyristors collapse, the voltage across this thyristor will build up.
As the voltage reaches dose to its voltage withstand limit, trie thyristcr
electronics issues a protective triggering pulse called the Over Voltage Protection
(OVP) pulse. This prevents the thyristor from failure. But the occurrence of OVP
\s communicated to the control electronics by a 5j.is pulse.

11
In the control electronics the control pulses are given to two separate FPGAs that
generates the coded pulse train and sends it two different trigger sources, Either
one of the circuits is adequate to trigger the thyristors. Hence 100% redundancy
of the triggering circuit is achieved, as a failure of any one does not affect the
aval lability of the system. The trigger pulses are interfaced to the thyristor
electronics by means of 2/7 fibre optic cables as shown in Figure - 4.
The present system accomplishes the monitoring operation based on the concept
that the OVP pulse will occur only during the 10μs time interval of the OVP
window. The control electronics thus uses OVP window to capture and latch the
occurrence of the OVP pulses. The status pulse is echoed by the thyristor
electronics and the status window captures this pulse. The LED pulse is
transmitted only through one selected transmitter at a time which ensures
monitoring the healthiness of the transmitters. An FP6A is used to segregate
these data pulses from and is arranged as an 8 bit as shown in the table below.
Bit Number Data
1 OVP +ve direction
2 Status +ve direction
3 LED +ve direction
4 OVP -ve direction
5 Status -ve direction
6 LED -ve direction
7 Counter LSB
8 Counter MSB

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The valve data is arranged in the 6 lower bits and the two upper bits are used as
a two bit counter. This data in interfaced to the micro-controller through a data
bus. The micro-controller reads the FPGA like a memory device. From the same
address location, four reads can be done to collect data of four different levels.
This is achieved by incrementing the counter with the read pulse and using a 4:1
multiplexer to present the data of different thyristors each time. The reading of
valve data is controlled by interrupts based on the control pulses. The micro
controller then processes the data and based on different combinations of data
received, it is possible to pin-point the exact nature of the fault. Thus the
following types of faults are identified,
a. Thyristor failure.
b. Triggering fibre optic cable failure
c. Monitoring fibre optic cable failure.
d. Triggering source failure.
e. Thyristor electronics failure.
These failures with its exact location are communicated to a PC connected to the
monitoring system. Figure - 7 and Figure - 8 show how the faults are displayed
to the operator.
EXAMPLES / PREFERRED EMBODIMENT
The system in accordance with the present invention comprises triggering
modules having redundant trigger sources and FPGAs. The modules accept
control pulses and control signals from the controller and send coded firing and
monitoring pulses to the thyristor electronics.

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The system further comprises monitoring modules that collect data from the
thyristor valves. This data is segregated by FPGAs and fed to the
microcontrollers. This data is read and processed in real time by the
microcontrollers to take protective action. The health of thyristor valve is
communicated to the operator through a graphical user interface residing on a
PC connected to the thyristor monitoring hardware,
A few sample displays of the thyristor monitoring are shown in Figure -7 and
Figure - 8.

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We Claim
1. A triggering and rea} time monitoring system for SVC-thyristor valves, the
thyristor valve (V) comprising a plurality of anti-parallel thyrsitors (T)
having a plurality of monitoring cables (RC), the number of thyrsitors (T)
and the number of monitoring cables (RC) being atleast one more than
the number of the thyristor valves (V), the system comprising a controller
(1) for receiving voltage (V) and current (I) signals from a power source
(S); a triggering and monitoring device (2) for receiving control and
commands from the controller (1), the triggering and monitoring device
(2) being interfaced to the thyrsitor valves (3) by atleast one optic cables
(4) and a monitoring cable (5) for triggering and monitoring via a thyrsitor
controlled reactor (3a), coded data received from the TCR (3a) being
decoded, processed and sent to a PC (4) connected with a printer (7) for
display.
2. The system as claimed in claim 1, wherein the triggering and monitoring
device (2) comprises atleast one triggering module having redundant
trigger source and atleast one field programmable rate array for receiving
control pulses from the controller and transmitting coded firing and
monitoring pulses to the thyristor electronics,
3. The system as claimed in claim 1, comprising monitoring modules that
collect data from the thyrsitor valve (V) which data being fed to the
thyrsitor electronics via the FPGA.

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4. Trie systems as claimed in cfairn 1, comprising a graphical user interface
(GUI) for providing decoded data to the operator
5. A triggering and real time monitoring system for SVC thyristor vaJves as
substantially described herein with reference to the accompanying
drawings.

Accordingly, there is provided a triggering and real time monitoring system for
SVC-thyristor valves, the thyristor valve (V) comprising a plurality of anti-parallel
thyrsitors (T) having a plurality of monitoring cables (RC), the number of
thyrsitors (T) and the number of monitoring cables (RC) being atleast one more
than the number of the thyrsitor valves (V), the system comprising a controller
for receiving voltage (V) and current (I) signals from a power source (S); a
triggering and monitoring device for receiving control and commands from the
controller, the triggering and monitoring device being interfaced to the thyrsitor
valves by atleast one optic cables and a monitoring cable for triggering and
monitoring via a thyrsitor controlled reactor, coded data received from the TCR
being decoded, processed and sent to a PC connected with a printer for display.
The thyristor valve comprises a number of anti-parallel connected thyristors In
series. Each level has a pair of anti - parallel thyristors, a snubber, a voltage
sharing resistor and a Thyristor Electronics. In a preferred embodiment, two
thyristors share one Thyristor Electronics. The thyristors that share one Thyristor
Electronics is selected such that the voltages on the Thyristor Electronics are less
than 100 V, which helps to ease the design of the Thyristor Electronics. Such a
configuration also results in reduction in the number of thyristor electronics and
the monitoring cables. The proposed system has only "N+1" thyristor electronics
and monitoring cables in the conventional system a thyristor valve comprising
"N" anti parallel levels has "2N" thyristors, and hence "2N" thyristor electronics
and monitoring cabtes reduces the number to almost half. This configuration also
helps to obtain a more detailed information of the level.
The use of FPGAs in the triggering circuit helps in generating windows of time
and sending coded pulses in these windows to trigger and monitor the pulses.
The use of cables with multiple inputs and multiple outputs helps in reducing the
number of triggering sources. As shown In the example only one triggering
source is adequate to trigger 7 thyristors, a 100% redundancy is also achieved
by this configuration by sending the triggering pulses through two sources
simultaneously. To monitor the health of the trigger sources some of the
monitoring pulses are transmitted only through a selected source.
The use of FPGAs and microcontrollers help in latching and processing the data
in real time in order to have a real time control over the monitoring system. The
window generated are used to segregate the data coming from the thyristor
valve. These windows are also used to generate interrupts for the micro-
controller to enable real time data collection and processing,
The present invention thus provides a novel method of sending coded monitoring
pulses along with the triggering pulses is used. The coding of the pulses are
carried out by a triggering module of the control electronics using Field
Programmable Gate Arrays (FPGAs), Such coded pulses are converted to optical
pulses and sent to the Thyristor Electronics. The Thyristor Electronics decodes
these pulses and triggers the thyristors. The Thyristor Electronics further sends
feedback monitoring pulses to the control electronics via return fibre optic cables.
The feedback pulses are decoded FPGAs and interfaced to microcontrollers to
obtain a detailed status of the health of the thyristors, the fibre optic cables, the
thyristor electronics and the triggering circuit in real time. This real time
monitoring helps in taking protective action before any cascading of failures
results. The health of the system is then sent to a PC through a serial link and
provided to the operator though a Graphical User Interface (GUI). This
information is also stored in files on the PC for future analysis and record. The
data is also printed using a standard parallel printer for the records.