TUNABLE TRUE-TIME-DELAY ELEMENT USING A VARIABLE-ORDER
ALL-PASS FILTER
CROSS-REFERENCES TO RELATED APPLICATIONS
[0001] None
Field of the Invention
[0002] The present invention relates generally to time delay elements and specifically to a tunable true time delay element that includes active components for providing tunable delays over wideband signals.
Description of the Related Art
[0003] Delay lines are important building blocks of analog signal processing circuits such as beamforming systems and continuous-time equalizers. Many of these applications process wideband signal sand need true-time-delay elements that are widely tunable. In beamforming systems the signal received by each element of an antenna array is delayed and combined to introduce directionality to transmission or reception. The same can also be done post downconversion for signal shaving lower bandwidth than the carrier. The spatial resolution of the beamforming systems improves as the number of antenna elements increases. This eventually increases the required maximum delay. The maximum delay is equal to the time taken by an electromagnetic wave to traverse the width of the array. In a continuous-time equalizer, the longer the impulse response of the channel, the longer must be the delay span of the equalizer. For a broadband signal, the group delay has to be uniform over the signal bandwidth. Therefore true-time-delay elements with large delay-bandwidth product that could maintain a large, flat group delay over a wide bandwidth need to be realized.
[0004] A true-time-delay element has a transfer function ofe_sTd. This is realizable with transmission lines terminating with the characteristic impedance. At low frequencies, the

length of the transmission line is impractically long for integrated circuit realizations. Hence lumped passive or active realizations are used. In such cases, a finite-order low-pass or all-pass filter (APF) with an approximately constant delay over the signal bandwidth, is used. These mainly use passive components as their building blocks. Use of active circuits can substantially reduce chip area. But, the active delay cells have been limited to first and second order APFs, which limit the delay-bandwidth product.
[0005] "A l-to-2.5GHz Phased-Array IC Based on gm-RC All-Pass Time-Delay Cells" (Garakoui et al, 2012) proposes an improved gm-C delay cell that realizes an accurate integrated time delay over a wide frequency band, at an acceptable power dissipation. Another publication "Implementation Of CMOS RF Circuits With Octave And Multi-Octave Bandwidth for Phased Array Antennas" (Hu Feng, 2014) proposes a second order all pass networks (APNs), that could achieve wide bandwidth, flatter group delay and occupies small area.
[0006] This invention discloses an area-efficient tunable true time delay element for providing widely tunable delays over wideband signals that could overcome the drawbacks of the existing systems.

SUMMARY OF THE INVENTION
[0007] The disclosure relates to an all pass filter architecture for providing tunable delays over wideband signals. The all pass filter architecture includes an all pass filter architecture that includes an all pass function comprising a weighted sum of a first input voltage and a second input voltage
VAP(S) = ±(2V1(s)-Vi)
where Vt is the first input voltage comprising transmission signals to be delayed before transmission,^^ is the second input voltage from a one port network and VAP(S) is the all pass filter output voltage. The second input voltage Vi(s) given by
V>(S)=V'Z^TR
where R is the resistance connected in series to the first input voltage and Zu(s) is the driving point impedance. In various embodiments the all pass circuit introduces a tunable delay in the first input voltage Vt prior to transmission.
[0008] In some other embodiments the one port network of the all pass filter architecture may include at least one of a lumped circuit that includes an LC network that includes LC elements or active elements. The one port network may also include distributed parameter network comprising transmission lines.
[0009] In various embodiments the one port network is a lumped parameter LC network that includes a LC ladder circuit that comprises one or more stages of a combination of one or more capacitors and inductors. The number of stages represents the order of the ladder circuit that is varied by turning ON or OFF the stages of the ladder circuit and the order is either odd or even.
[0010] In some embodiments the one port network with an odd order LC ladder is characterized by a driving point impedance of

where Ne(s) is a polynomial comprising the even powers of s, D0(s) is a polynomial comprising the odd powers of s and s is the complex frequency. The delay could be varied by varying the inductor or capacitor elements. The transfer function of the all pass filter is given by
and the gain has a magnitude of unity.
[0011] In some embodiments the one port network with an even order LC ladder is characterized by a driving point impedance of
Where N0(s) is a polynomial comprising the odd powers of s, De(s) is a polynomial comprising the even powers of s and s is the complex frequency.
The delay is varied by varying the inductor or capacitor elements. The transfer function of the all pass filter is given by
and the gain has a magnitude of unity.
[0012] In some embodiments the one port network that includes the LC network comprises either a lossless LC ladder circuit or a lossy LC ladder circuit with a constant loss factor.
[0013] In some embodiments the all pass filter architecture includes a lossless or lossy distortionless transmission line terminated either by an open circuit or a short circuit.

[0014] In various embodiments the lossless transmission line terminated by an open circuit is characterized by a driving point impedance of
transmission line, L0 is the inductance per unit length of the transmission line, C0 is the capacitance per unit length of the transmission line.The delay introduced in the transmission of the first input voltage
The delay is varied by varying the length of the transmission line. The transfer function of the all pass filter is given by
and the gain has a magnitude of unity at all frequencies.
[0015] In some other embodiments the one port network with a lossless transmission line terminated by a short circuit is characterized by a driving point impedance of
characteristic impedance, length of the transmission line, L0 is the inductance per unit length of the transmission line, C0 is the capacitance per unit length of the transmission line. The delay introduced in the transmission of the first input voltage
The delay is varied by varying the length of the transmission line. The transfer function of the all pass filter is given by and the gain has a magnitude of unity at all frequencies.
[0016] In some embodiments the one port network with a lossy distortionless transmission line terminated by an open circuit is characterized by a driving point impedance of

characteristic impedance, is the length of the transmission line, L0 is the inductance
per unit length of the transmission line, C0 is the capacitance per unit length of the transmission line. The delay introduced in the transmission of the first input voltage Vt is
The delay is varied by varying the length of the transmission line. The transfer function of the true time delay element is given by
The gain has a magnitude of at all frequencies.
[0017] In some other embodiments the one port network with a lossy distortionless transmission line terminated by a short circuit is characterized by a driving point impedance of characteristic impedance, is the length of the transmission line, L0 is the inductance per unit length of the transmission line, C0 is the capacitance per unit length of the transmission line. The delay introduced in the transmission of the first input voltage Vt is
The delay is varied by varying the length of the transmission line. The transfer function of the all pass filter is given by
and the gain has a magnitude of e~2al at all frequencies.
[0018] In various embodiments the one port network includes a ladder circuit that includes one or more stages. Each stage may comprise a pair of active elements and one or more variable capacitances. The characteristic impedance is given by

where Ne(s) is a polynomial comprising the even powers of s, D0(s) is a polynomial comprising the odd powers of s and s is a Complex frequency. The delay introduced in the transmission of the first input voltage V; is a step-wise function of the number of stages in the ladder circuit and wherein the number of stages could be switched ON or OFF to either increase or decrease the delay. The transfer function of the all pass filter is given by
where HAP is the transfer function of the all pass filter, Ne(s) is a polynomial comprising
the even powers of s, D0(s) is a polynomial comprising the odd powers of s and s is a
Complex frequency and the gain has a magnitude of unity.
[0019] In various embodiments the active elements could be operational
transconductance amplifiers (OTA) or operational amplifiers based integrators.
[0020] In some embodiments the bandwidth is a function of the transconductance of the
OTA and the fine delay resolution is a continuous inverse function of bandwidth. In
some embodiments the all pass filter comprises summing taps supplied with a variable
voltage to vary gain.
[0021] In various embodiments the all pass filter is incorporated in a tunable true time
delay element. The tunable true time delay element introduces a delay in the input signal.
In some embodiments the group delay is uniform over all frequencies of the input signal.
In some other embodiments the delay in the tunable true time delay element is varied
coarsely and is a function of the order of the circuit. In some other embodiments the fine
delay resolution of the tunable true time delay element is a continuous inverse function
of bandwidth.
[0022] In various embodiments the tunable true time delay element is incorporated in
beamforming systems that delays the signal received by each element of an antenna array
prior to transmission.

[0023] In some other embodiments the tunable true time delay element is incorporated in
continuous time equalizer systems that provide a long delay span for long impulse
response of the channel.
[0024] In various embodiments the invention is an integrated circuit chip for providing
widely tunable delays over a wideband signal that includes a tunable true time delay
element comprising a variable order all pass filter architecture comprising one or more
operational transconductance amplifiers and a summing tap to provide a weighted sum of
an input voltage to be transmitted, with a node voltage that is a function of the input
voltage and the drive point impedance of a ladder circuit;
[0025] In various embodiments the ladder circuit comprises at least a first stage and one
or more other stages comprising a pair of operational transconductance amplifiers and
one or more integrating variable capacitances where each stage represents the order of
the all pass filter.
[0026] In various embodiments the integrated circuit chip includes an order select digital
logic to program the filter's order by either turning ON or OFF the number of stages of
the ladder circuit and to program the integrating capacitances.
[0027] In various embodiments the integrated circuit chip on receiving an input signal is
configured to produce an output signal at a delayed time and the delay is tunable as a
function of the order of the filter and the bandwidth.
[0028] In some embodiments the supply voltage to the summing tap is varied to vary
gain. In various embodiments the delay is a step-wise function of the number of stages.
In some embodiments an increase in step increases the delay by a predetermined time
period. In some embodiments the delay is a continuous inverse function of the bandwidth
and is tuned by tuning the reference current to the bias generator.

BRIEF DESCRIPTION OF THE DRAWINGS
[0029] The invention has other advantages and features which will be more readily apparent from the following detailed description of the invention and the appended claims, when taken in conjunction with the accompanying drawings, in which:
[0030] FIG. 1A illustrates an all pass filter.
[0031] FIG. IB illustrates an APF realised using transconductors and resistors.
[0032] FIG. 2A shows an odd order capacitor first LC ladder.
[0033] FIG. 2B shows an even order capacitor first LC ladder.
[0034] FIG. 2C shows an odd order inductor first LC ladder.
[0035] FIG. 2D shows an even order inductor first LC ladder.
[0036] FIG.3A illustrates an all pass filter having a lossless LC ladder as one port
network.
[0037] FIG. 4A illustrates an all pass filter having a transmission line terminated by an
open circuit as one port network.
[0038] FIG. 4B shows an all pass filter having a transmission line terminated by short
circuit as one port network.
[0039] FIG. 4C shows reflected pulse in phase with the incident pulse received after a
time delay of 2Td.
[0040] FIG. 4D shows reflected pulse out of phase with the incident pulse received after
a time delay of 2Td.
[0041] FIG. 5 illustrates an all pass filter having an active ladder as one port network.
[0042] FIG. 6 shows the internal circuitry used in each OTA element of the all pass filter
architecture to obtain near-ideal characteristics.
[0043] FIG. 7 illustrates tuning of transconductance Gm fixed to a value alref /AV
through the circuit.
[0044] FIG. 8A shows a first order APF.

[0045] FIG. 8B shows an active first order all pass delay cell.
[0046] FIG. 8C illustrates an active second order all pass delay cell.
[0047] FIG. 8D illustrates obtaining large delays using cascading of first and second
order delay cells.
[0048] FIG. 9A shows the beamforming system incorporating the true time delay
element.
[0049] FIG. 9B shows continuous time equalizer system incorporating the true time
delay element.
[0050] FIG. 10 illustrates the block diagram of the integrated circuit chip that could
provide widely tunable delay over a wideband signal.
[0051] FIG. 11 shows the die of the integrated circuit chip fabricated in a standard 0.13
urn CMOS process.
[0052] FIG. 12A illustrates the measured magnitude of the variable order APF for coarse
delay settings.
[0053] FIG. 12B shows the measured group delay of the variable order APF coarse delay
settings.
[0054] FIG. 12C shows the measured magnitude of the variable order APF for fine delay
settings.
[0055] FIG. 12D illustrates the measured group delay of the variable order APF for fine
delay settings.
[0056] FIG. 13A illustrates the measured (from two chips) and back annotated group
delay response for coarse delay settings.
[0057] FIG. 13B shows the systematic Gm variation of the filters' OTAs to reproduce the
response in FIG. 13A.
[0058] FIG. 14A illustrates the measured coarse delay resolution response to a Gaussian
3.2 ns wide (FWUM) monopulse.
[0059] FIG. 14B illustrates the measured fine delay resolution response to a Gaussian
3.2 ns wide monopulse.

[0060] FIG. 15A shows the transient plots demonstrating monotonically varying true-time-delay when a monopulse of 1 ns width is fed to the filter.
[0061] FIG. 15B illustrates computed rms error between the outputs and delayed and scaled input of FIG. 15 A.
[0062] FIG. 16A shows the magnitude of ninth order APF gain for different summing tap voltages VDDH-
[0063] FIG. 16B shows the group delay frequency characteristics of ninth order APF for different summing tap voltages, VDDH-
[0064] FIG. 17A illustrates the measured input referred noise spectral density. [0065] FIG. 17B shows the measured integrated noise figure vs order of the filter. [0066] FIG. 18A illustrates the measured peak to peak differential input voltage for which IM3 falls 40 dB below the applied tones for nominal delay setting. [0067] FIG. 18B shows the 1 dB compression points corresponding to the measured peak to peak differential input voltage which IM3 falls 40 dB below the applied tones for nominal delay setting.
[0068] FIG. 18C illustrates the measured peak to peak differential input voltage for which EVI3 falls 40 dB below the applied tones for increased delay setting post fine tuning.
[0069] FIG. 18D shows the 1 dB compression points corresponding to the measured peak to peak differential input voltage for which IM3 falls 40 dB below the applied tones for increased delay setting post fine tuning.
[0070] FIG. 19 illustrates the computed radiation pattern for a four element array with uniform spacing of 7.5 cm(fmax/2). [0071] Referring to the drawings, like numbers indicate like parts throughout the views.

DETAILED DESCRIPTION
[0072] While the invention has been disclosed with reference to certain embodiments, it will be understood by those skilled in the art that various changes may be made and equivalents may be substituted without departing from the scope of the invention. In addition, many modifications may be made to adapt to a particular situation or material to the teachings of the invention without departing from its scope.
[0073] Throughout the specification and claims, the following terms take the meanings explicitly associated herein unless the context clearly dictates otherwise. The meaning of "a", "an", and "the" include plural references. The meaning of "in" includes "in" and "on." Referring to the drawings, like numbers indicate like parts throughout the views. Additionally, a reference to the singular includes a reference to the plural unless otherwise stated or inconsistent with the disclosure herein.
[0074] The invention in its various embodiments proposes an all pass filter architecture that introduces a tunable delay in an input signal. The all pass filter architecture is incorporated in a tunable true time delay element that provides widely tunable delays over wideband signals. Further an area efficient integrated circuit chip could be fabricated for producing tunable true time delay in transmission signals.
[0075] In various embodiments an all pass filter architecture 100 as shown in FIG. 1A is disclosed that could produce tunable delays over wideband signals. The all pass filter architecture 100 includes an all pass function that includes a weighted sum of a first input signal that is to be transmitted and a second input signal from a one port network 120 that is a function of the first input signal and the driving point impedance. The one port network 120 may include a lumped parameter LC network that includes LC elements or active elements, or the one port network 120 may also include distributed parameter network that includes transmission line. In various embodiments the all pass function receives a first input voltage Vt 131 and a second input voltage Vi 121. The first

input voltage Vt 131includes transmission signals to be delayed before transmission. The second input voltage Vi 121includes voltage drop across the one port network that is a function of the driving point impedance Zn(s) 123 that includes the equivalent impedance looking into the one port network 120 and is given by: The all pass function produces an all pass filter output voltage VAP 130 that is a weighted sum of the first input voltage 131 and the second input voltage 121and is given by:
[0076] In various embodiments on receiving the first input voltage V;(s) 131 that is to be transmitted, the all pass filter introduces a delay in the first input voltage V;(s) 131, prior to transmission. The delay introduced by the all pass filter is a function of the elements of the one port network 120 and the delay bandwidth of the filter.
[0077] In various embodiments the all pass filter architecture 200 as shown in FIG. IB
that produces tunable delays over wideband signals includes active components 151, 152
and 153. The active components 151, 152 and 153 could be operational transconductance
amplifiers having Gm as transconductance. In some embodiments the transconductance where R is the resistance included in the circuit. In various embodiments the one
port network could include a lumped parameter LC network 300 that includes LC elements as shown in FIG. 2A, FIG. 2B, FIG. 2C and FIG. 2D or distributed parameter network that includes transmission lines as shown in FIG. 4A, FIG. 4B or a lumped parameter circuit having active components as shown in FIG 5. In some embodiments the number of stages could be turned ON or OFF to either increase or decrease the order of the all pass filter.
[0078] In some embodiments the all pass filter architecture 400 could include a lumped parameter delay line that includes a LC ladder circuit as shown in FIG. 3A and FIG.

3B.In various embodiments the LC ladder circuit comprises one or more stages that include at least one inductor and one capacitor in each stage. The number of stages determines the order of the APF filter architecture. The LC ladder circuit in various embodiments could have odd order or even order depending on the number of stages. The odd order LC ladder circuit as shown in FIG. 2A and FIG. 2C is characterized by a driving point impedance of whereNe(s) is a polynomial comprising the even powers of s, D0(s) is a polynomial
comprising the odd powers of s and s is a Complex frequency. The delay introduced in
the transmission of the first input voltage Vt is determined by the L and C element values
in the one-port network and the delay could in some embodiments be varied by varying
the inductor or capacitor elements. The transfer function HAp of the all pass filer 400 is
given by
and has a gain of unity. The all pass output voltage VAp for an odd order LC ladder circuit as one port network is given by
[0079] In some other embodiments the even order LC ladder circuit as shown in FIG. 2B and FIG. 2D is characterized a driving point impedance of
where N0(s) is a polynomial comprising the odd powers of s, D0(s) is a polynomial comprising the even powers of s and s is a Complex frequency. The delay introduced in the transmission of the first input voltage Vt is determined by the L and C element values in the one-port network and the delay could be varied by varying the inductor or capacitor elements. The transfer function HAp of the all pass filer 400 is given by

and has a gain of unity. The all pass output voltage VAp for an even order LC ladder
circuit as delay line is given by
[0080] In various embodiments the LC ladder circuit 300 could be an odd order capacitor first LC ladder as shown in FIG. 2A or an even order capacitor first LC ladder as shown in FIG. 2B or it could be an odd order inductor first LC ladder as shown in FIG. 2C or could be an even order inductor first LC ladder as shown in FIG. 2D.The LC ladder circuits could either be lossless as shown in FIG. 3A or could be lossy with a constant loss factor as shown in FIG. 3B.
[0081] In some embodiments the one port network of the all pass filter architecture 500 could include transmission lines as shown in FIG. 4A and FIG. 4B. The transmission line 401could terminate with an open circuit as shown in FIG. 4A or could terminate with a short circuit as shown in FIG.4B.The transmission line terminating with either a short circuit or an open circuit could be either lossless or could be lossy and distortionless.
[0082] In various embodiments the one port network having a lossless transmission line
terminated by an open circuit as shown in FIG. 4A is characterized a driving point
impedance of
whereZ0 = /— is the characteristic impedance, /? = o)JL0C0,l is the length of the \ Q>
transmission line, L0 is the inductance per unit length of the transmission line and C0 is
the capacitance per unit length of the transmission line. The delay introduced in the
transmission of the first input voltage Vt is given by
The transfer function of the true time delay element is given by

and the gain has a magnitude of unity at all frequencies.
[0083] In various embodiments the one port network having a lossless transmission line
terminated by a short circuit as shown in FIG. 4B is characterized by a driving point
impedance of
whereZ0 = /— is the characteristic impedance, /? = o)JL0C0, I is the length of the
transmission line, L0 is the inductance per unit length of the transmission line, C0 is the capacitance per unit length of the transmission line. The delay introduced in the transmission of the first input voltage Vt is 2l^L0C0. The transfer function of the true time delay element is given by
and the gain has a magnitude of unity at all frequencies.
[0084] In various embodiments the one port network having the lossy distortionless
transmission line terminated by an open circuit is characterized by a driving point
impedance of is the characteristic impedance, is the length of the transmission line, L0 is the inductance
per unit length of the transmission line and C0 is the capacitance per unit length of the transmission line. The delay introduced in the transmission of the first input voltage Vt is
The transfer function of the all pass filter architecture is given by
and the gain has a magnitude of e~2al at all frequencies.

[0085] In various embodiments the one port network having a lossy distortionless transmission line terminated by a short circuit is characterized by a driving point impedance of
per unit length of the transmission line, C0 is the capacitance per unit length of the transmission line. The delay introduced in the transmission of the first input voltage Vt is
function of the all pa filter architecture is given by and the gain has a magnitude of e~2al at all frequencies.
[0086] In various embodiments, on receiving the first input voltage V; 41 las shown in FIG. 4C the all pass filter architecture having transmission line terminated by a open circuit as the one port network would produce a reflected pulse 421 that is in phase with the incident pulse and could produce an all pass output voltage VAP= 2VI-V; at a delayed time 2Td. In some other embodiments, on receiving the first input voltage V;461 as shown in FIG. 4D the all pass filter architecture having transmission line terminated by a short circuit as the one port network would produce a reflected pulse 471 that is out of phase with the incident pulse and could produce an all pass output voltage VAP= V;-2VI at a delayed time 2Td. The delay in the transmission line could be varied by varying the length of the transmission line or the termination condition.
[0087] In various embodiments the all pass filter architecture could include a ladder circuit having active components as shown in FIG. 5. The ladder circuit includes one or more stages 510, 520, 530 and 550 where each stage includes a pair of active elements

515-1...515-n, 517-1...517-n and one or more integrating capacitances 519-2...519-
n.The driving point impedance is given by
whereNe(s) is a polynomial comprising the even powers of sD0(s) is a polynomial comprising the odd powers of s and s is a Complex frequency;
[0088] In some embodiments when the all pass filter circuit 501 receives the first input voltage signal Vt to be transmitted, a delay is introduced in the signal. The delay introduced is a function of the number of stages in the ladder circuit and the delay bandwidth of the filter. The number of stages could be turned ON or OFF to either increase or decrease the delay. The transfer function of the all pass filter architecture is given by
wherein is the transfer function of the all pass filter, Ne(s) is a polynomial comprising the even powers of s, D0(s) is a polynomial comprising the odd powers of s and s is a Complex frequency. The transfer function has a gain of unity.
[0089] The delay in some embodiments could be tuned between a maximum and minimum value. Delay could be tuned coarsely or could be fine-tuned to have a fine delay resolution. Coarse tuning is a stepwise function that is done by either switching ON or OFF the number of stages in the ladder circuit. The delay increases as the number of stages in the ladder circuit increase. The delay bandwidth is varied to have a finer resolution of delay. The delay is an inverse function of the delay bandwidth.
[0090] In some embodiments the active elements in the circuit could be operational transconductance amplifiers (OTA) 515-1...515-n, 517-1...517-n as shown in FIG. 5, or operational amplifiers based integrators. In various embodiments a transconductor with a high DC gain, no parasitic poles and small output capacitance is realized by canceling

the output conductance Gm of the transconductor 601 using an incremental negative conductance GN 61 las shown in FIG. 6.
[0091] In some embodiments the transconductance Gm of the OTA 701, 702 is fixed at a predetermined value as shown in FIG. 7 and is given by:
where Iref 711, 712 is a reference current, a is the mirroring ratio and AV 731 is an incremental voltage at the input of the OTA 701, 702. Gm is tuned by tuning the mirroring ratio,a or the reference current Iref 711, 712 thus tuning the bandwidth of the filter.
[0092] In various embodiments the all pass filter 110 includes summing taps that have a supply voltage that could be tuned. Tuning the supply voltage changes the output conductance of the OTAs that could vary the gain of the all pass filter and hence is used for gain programmability.
[0093] In various embodiments the all pass filter architecture is incorporated in a tunable true time delay element as shown in FIG. 8A, FIG. 8B, and FIG. 8C that introduces a delay in the input signal that is to be transmitted. FIG. 8B and FIG. 8C shows tunable true time delay element incorporating an active first order and second order APF respectively. The tunable true time delay element incorporating the all pass filter could introduce large delays by cascading delay cells of different order as shown in FIG. 8D. In some other embodiments the group delay in the tunable true time delay element is uniform over all frequencies of the input signal.
[0094] The delay in some embodiments could be tuned between a maximum and minimum value. Delay could be tuned coarsely or could be fine-tuned to have a fine delay resolution. Coarse tuning is a stepwise function that is done by either switching ON or OFF the number of stages to vary the order of the ladder circuit. The delay

increases as the number of stages in the ladder circuit increase. The delay bandwidth is varied to have a finer resolution of delay. The delay is an inverse function of the delay bandwidth.
[0095] In various embodiments the tunable time delay element is incorporated in a beamforming system as shown in FIG. 9A that independently tunes the gain and delay settings of each signal path. The delay tunability allows the beamforming system to operate in a stable manner by correcting mismatches between different signal paths.
[0096] In various embodiments the tunable time delay element is incorporated in a continuous time equalizer as shown in FIG. 9B. The large, uniform group delay maintained by the integrated circuit chip makes it possible for the equalizer to provide a long delay span for long impulse response of the channel.
[0097] In various embodiments the invention includes an integrated circuit chip 800 as shown in FIG. 10 that provides widely tunable delays over a wideband signal. The integrated circuit chip as shown in FIG. 10 includes a variable order all pass filter architecture 810. The all pass filter architecture 810 includes one or more operational transconductance amplifiers and a summing tap that provides a weighted sum of the input voltage Vt and the node voltage across the one port network to produce an output signal at a delayed time. The delay in the output signal in the integrated circuit chip is tunable and is a function of the order of the filter and the bandwidth.
[0098] In various embodiments the integrated circuit chip 800 further includes an order select digital logic820, a bias generator 830 and an output MUX 840. The order select820digital logic programs the filter's order by either tuning ON or tuning OFF the number of stages of the ladder circuit. The filter's order could be programmable to any order. The order select digital logic 820 also programs the integrating capacitances to reduced values to realize higher bandwidth. In various embodiments the delay introduced by the integrated circuit chip is a step-wise function of the order of the all pass filter and

each step increases the delay by a predetermined time. In some embodiments the delay is also a continuous function of the bandwidth. The delay increases as the bandwidth is decreased by tuning the reference current Iref to the bias generator 830. The reference current 831 as shown in FIG. 10 is tuned by tuning an external resistor.
[0099] EXAMPLES
[00100] Example 1 : Working of the integrated circuit chip providing tunable time delay over a wideband signal
[00101] The test chip was fabricated in a standard 0.13 urn CMOS process. The die photograph is showing FIG. 11. The chip occupies an active area of 0.55mm2, out of which the APF takes up 0.3mm2.The chip was tested with a ladder supply voltage (VDD) of 1.4V, and common mode voltage, Vcm, of 860mV. The summing tap supply voltage (VDDH) was varied from 0.95 to 1.75V to vary the gain. FIG. 12A, FIG. 12B, FIG. 12C and FIG. 12D shows the measured magnitude, phase, and the group delay response of the APF for VDDH ofl.75V. The filter's response has been extracted. Each color corresponds to the frequency response of a respective filter order between two and nine. Multiple plots in the same color as shown in FIG. 12A, FIG. 12B correspond to the filter's response post fine tuning the group delay by changing the bandwidth. FIG. 12C and FIG. 12D corresponds to the filter's response after fine tuning the group delay. The APF achieves a group delay range of 250 ps to 1.7 ns over a worst case group delay bandwidth of 2 GHz. This makes the maximum delay bandwidth product equal to 3.4.
[00102] The absolute delay variation within the bandwidth for the maximum and the minimum delay settings are ±140 ps (±8%), and ±30 ps (±12%) respectively. As the filter's order is swept from two to nine, the power consumption increases from 112 mW to 364 mW. With a unit increment in the filter's order, the coarse delay increases approximately by 200 ps. The finer delay increments are obtained by reducing the filter's bandwidth by reducing the Gms of the ladder OTAs. The granularity of the finer delay

resolution is limited by the granularity with which the filter Gms is changed. The peak-to-peak magnitude response deviation for all delay settings is within 1.4 dB. The difference between the measured and the simulated group delay is attributed to the systematic mismatch between the filter's OTAs as they are spread over a wide area. FIG. 13A shows the group delay responses from two chips and the simulated response obtained with Gm values of FIG. 13B in the filter's core for all orders. The close match between the plots validates this assumption. The filter's magnitude response for all delay settings varies within ±0.7 dB. FIG. 14A shows the measured output of the filter demonstrating coarse tuning when excited by a Gaussian monopulse having FWHM=3.2 ns as the order of the filter is changed from 2 to 9. The input has transients beyond the pulse duration mainly due to cabling between the pulse generator board and the test board for the all-pass filter. Similar transients are seen in the delayed outputs as well. The inset shows an observable delay resolution of 200 ps.
[00103] FIG. 14B shows the measured delays with fine tuning. The filter faithfully retains the shape of the input pulse and delays it. The monotonicity of the true-time-delay with change in delay settings is evident from the transient plots, thus corroborating the delay tuning nature of the architecture. Since the pulse generation setup could not generate pulses narrower than 3.2 ns, to ascertain the wideband behavior of the filter, the transient response is computed for a 1 ns wide Gaussian monopulse by convolving it with the filter's impulse response which is extracted from the measured frequency response. FIG. 15A shows these computed responses. They behave similarly to the measured responses in FIG. 14A and FIG. 14B and confirm the true-time-delay behavior for wideband pulses. The worst case rms error in twice the FWUM range for the outputs in FIG. 14A and FIG. 14B is 33 dB below the peak to peak input pulse and is shown in FIG. 13B.
[00104] The filter's gain was trimmed by varying VDDH (summing tap supply voltage). FIG. 16A and FIG.16Bshow the measured frequency response for the ninth

order APF with VDDH as a parameter. The filter's gain varies between -8 dB to 0.6 dB, for VDDH from 0.95V to 1.75V. The group delay characteristics remain almost identical across all gain settings. This allows the beamformer to independently tune the gain and delay settings of each signal path.FIG.17A, and FIG.17B show the measured input referred noise power spectral density for all orders, and the integrated noise figure vs order respectively. The noise figure is maximum for the delay settings corresponding to the highest delay (order=9) and is equal to 23 dB. The worst case NF improves to 17.5 dB when the order is decreased to 2. The technique has been used to de-embed the noise and the frequency dependent effects of the measurement paths.
[00105] The total output integrated noise in the range of 100MHz-2.5GHz varies from 357 uV(order=2) to 635 uV(order=9).For measuring distortion the filter was excited with two tones, 1MHz apart and their third order intermodulation (EVI3) component observed as their center frequency is varied. FIG.18A shows the measured maximum input voltage for which the output IM3 falls 40 dB below the fundamental tone, the strength of which varies from 81mVppd (order=2) to 44mVppd (order=9) at the respective nominal bandwidth settings. The observed worst case IIP3, which corresponds to the highest delay setting, was -3.1 dBm. FIG. 18B shows the measured ldB compression points (PldB) for all orders across frequency.PldB varies from -4 dBm to -13.3 dBm as the filter's order varies from 2 to 9.
[00106] Distortion increases when bias current is reduced to reduce the bandwidth for fine tuning. The worst case occurs when the delay of the eighth order configuration is increased to match the nominal delay of the ninth order. The maximum input voltage for -40 dB IM3 is 37mVppd in that case. For the same configuration PldB falls to -14.5 dBm. These are shown in FIG. 18C and FIG. 18D.The delays obtained from the measured frequency response of FIG. 12 A, FIG. 12B, FIG. 12C and FIG. 12D were used to compute the radiation pattern for a four element antenna array with an uniform

spacing of 7.5 cm (fmax/2),using a monopulse width of 1 ns. The peak of the received pulse was used to estimate the strength of the received signal.
[00107] FIG. 19 shows the radiation pattern as the delays in signal paths are varied. With same delay settings for all the APFs the radiation pattern has maximum intensity normal to the array, whereas a delay difference of 250 ps between adjacent antennas steers the beam by 90° off broadside. ±90°beam steering can be realized as the delay range of the filter (1.45 ns) exceeds the time required for the EM wave to traverse the antenna array in the endfire direction (3/2 x fimax/c). The steering resolution is limited by the fine delay steps, which is in turn controlled by the resolution of the bias current which controls the transconductances of the APF Gms.
[00108] Table. 1 compares the performance of the proposed all-pass filter with other existing time delay elements. The proposed architecture, due to its higher order APF achieves a high delay bandwidth product (maximum delay for a given bandwidth) among the lumped LC or Gm-C architectures. It also achieves the highest delay rangexbandwidth product among such architectures. The filter achieves a delay per unit area of 5.7 ns/mm2. The filter maintains its all-pass form across all delay settings and hence, it achieves minimum gain deviation across the delay tuning range.
Table 1: Performance comparison of the proposed all-pass filter with other existing time

[00109] The strengths of the proposed architecture are its large delay bandwidth product, large delay per unit area, and a magnitude response which is independent of the filter's delay. The performance of the chip is summarized in Table. 2.

WE CLAIM:
1. An all pass filter architecture comprising:
a variable order all pass function comprising a weighted sum of a first input voltage and a second input voltage
VAP(S) =±(2Vi(s)-Vi) wherein
VAP(S) is the all pass filter output voltage; Vi is the first input voltage comprising signals to be transmitted; Vi(s) is the second input voltage from a one port network wherein; the second input voltage Vi(s) is given by
wherein R is the resistance connected in series to the first input voltage and Zu(s) is the driving point impedance wherein the all pass circuit introduces a tunable delay in the first input voltage Vt, prior to transmission that is a function of the elements of the one port network.
2. The all pass filter architecture of claim 1 wherein the one port network comprises at least one of a lumped parameter LC network comprising LC elements or active elements, or distributed parameter network comprising transmission line.
3. The all pass filter architecture of claim 1 wherein the one port network is a lumped parameter LC network, the LC elements being arranged in a LC ladder comprising one or more stages wherein the number of stages represents an order of the ladder circuit and wherein the order is varied by turning ON or OFF the stages of the ladder circuit and thereby the order is either odd or even.

4. The all pass filter architecture of claim 3, wherein when the LC ladder is of
odd order the one port network is characterized by
where Ne(s) is a polynomial comprising the even powers of s;
D0(s) is a polynomial comprising the odd powers of s; and
s is a complex frequency;
b) the delay is varied by varying the inductor or capacitor elements;
and
c) the transfer function of the all pass filter is given by
5. The all pass filter architecture of claim 3, wherein when the LC ladder is of
even order the one port network is characterized by
a) a driving point impedance of
where N0(s) is a polynomial comprising the odd powers of s;
De(s) is a polynomial comprising the even powers of s; and
s is complex frequency;
b) the delay is varied by varying the inductor or capacitor elements;
and
c) the transfer function of the all pass filter is given by

6. The one port network comprising lumped parameter LC network of claim 3
comprises either a lossless LC ladder or a lossy LC ladder circuit.
7. The all pass filter architecture of claim 1 wherein the one port network is a
distributed parameter network comprising either a lossless or lossy distortionless transmission line with a constant loss factor terminated either by an open circuit or a short circuit.
8. The all pass filter architecture of claim 7, wherein the lossless transmission
line terminated by an open circuit is characterized by
lis the length of the transmission line;
L0is the inductance per unit length of the transmission line;
C0is the capacitance per unit length of the transmission line; and
b) the delay introduced in the transmission of the first input voltage
Vj is 21TJL0C0 and wherein the delay is varied by varying the
length of the transmission line; and wherein
c) the transfer function of the all pass filter is given by
and wherein the gain has a magnitude of unity at all frequencies.

9. The all pass filter architecture of claim 7, wherein the lossless transmission line
terminated by a short circuit comprises
a) a driving point impedance of
is the characteristic impedance;
is the length of the transmission line; L0is the inductance per unit length of the transmission line; C0is the capacitance per unit length of the transmission line;
b) the delay introduced in the transmission of the first input voltage
Vt is 2l^L0C0 and wherein the delay is varied by varying the
length of the transmission line; and wherein
c) the transfer function of the all pass filter is given by
and wherein the gain has a magnitude of unity at all frequencies.
10. The all pass filter architecture of claim 7, wherein the lossy distortionless
transmission line terminated by an open circuit comprises
/is the length of the transmission line;
L0is the inductance per unit length of the transmission line;
C0is the capacitance per unit length of the transmission line; and

b) the delay introduced in the transmission of the first input voltage Vt is 2l^L0C0 and wherein the delay is varied by varying the length of the transmission line; and wherein c) the transfer function of the all pass filter architecture is given by
and wherein the gain has a magnitude of e~2al at all frequencies.
11. The all pass filter architecture of claim 7, wherein the lossy distortionless
transmission line terminated by a short circuit comprises
a) a driving point impedance of
the characteristic impedance;
is the length of the transmission line; L0is the inductance per unit length of the transmission line; C0is the capacitance per unit length of the transmission line; and
b) the delay introduced in the transmission of the first input voltage
and wherein the delay is varied by varying the
length of the transmission line; and wherein
c) the transfer function of the all pass filter is given by
and wherein the gain has a magnitude of e~2al at all frequencies.
12. The all pass filter architecture of claim 1 wherein the one port network is a
lumped parameter network comprising active elements, the elements being arranged in a

ladder comprising one or more stages wherein each stage comprises a pair of active elements and one or more variable capacitances wherein
a) the characteristic impedance is given by
where Ne(s) is a polynomial comprising the even powers of s; D0(s) is a polynomial comprising the odd powers of s; and s is a Complex frequency;
b) the delay introduced in the transmission of the first input voltage Vi is a step-wise function of the number of stages in the ladder circuit and wherein the number of stages could be switched ON or OFF to either increase or decrease the delay.
c) the transfer function of the all pass filter is given by
where HAP is the transfer function of the all pass filter
Ne(s) is a polynomial comprising the even powers of s; D0(s) is a polynomial comprising the odd powers of s and s is a Complex frequency; and wherein the gain has a magnitude of unity.
13. The one port network of claim 12 wherein the active elements are operational transconductance amplifiers (OTA) based, or operational amplifiers based integrators.
14. The all pass filter architecture of claim 1 wherein the active element is an OTA and the bandwidth is a function of the transconductance of the OTA.

15. The all pass filter architecture of claim 1 wherein the all pass filter comprises summing taps supplied with variable voltage to vary gain.
16. A tunable true time delay element incorporating the all pass filter of claim 1 wherein a delay is introduced in the input signal.
17. The tunable true time delay element of claim 16 wherein the group delay is uniform over all frequencies of the input signal.
18. The tunable true time delay element of claim 16 wherein the delay could be varied coarsely and is a function of the order of the circuit.
19. The tunable true time delay element of claim 16 wherein the fine delay resolution is a continuous inverse function of bandwidth.
20. Beamforming systems incorporating the tunable true time delay element of claim 16 wherein the tunable true time delay element delays the signal received by each element of an antenna array prior to transmission.
21. Continuous time equalizer systems incorporating the tunable true time delay element of claim 16 wherein the tunable true time delay element provides a long delay span for long impulse response of the channel.
22. An integrated circuit chip for providing widely tunable delays over a wideband signal comprising:
A tunable true time delay element comprising:
a variable order all pass filter architecture comprising:

one or more operational transconductance amplifiers and a summing tap to provide a weighted sum of an input voltage to be transmitted, with a node voltage that is a function of the input voltage and the drive point impedance of a ladder circuit; wherein
the ladder circuit comprises at least a first stage and one or
more other stages comprising a pair of operational
transconductance amplifiers and one or more integrating
variable capacitances wherein each stage represents the
order of the all pass filter;
an order select digital logic to program the filter's order by either turning
ON or OFF the number of stages of the ladder circuit and to program the
integrating capacitances;
a bias generator configured to receive an external reference current and a
chopping clock to produce a bias current for the OTAs wherein
transconductance of the OTA is a function of the bias current and is
maintained constant; and
the integrated circuit chip on receiving an input signal is configured to produce an
output signal at a delayed time wherein the delay is tunable as a function of the
order of the filter and the bandwidth.
23. The integrated circuit chip of claim 22 wherein the delay is a step-wise
function of the number of stages wherein an increase in step increases the delay by predetermined time period.

24. The integrated circuit chip of claim 22 wherein the delay is a continuous
inverse function of the bandwidth and is tuned by tuning the reference current to the bias generator.