FIELD OF THE INVENTION

The present invention discloses a two channel Transmitter Driver and Receiver pairs (Transceiver) connected to a terminated bus for transmitting and receiving signals following MIL-STD-1553B standard. The Monolithic ASIC operates on a Single 5V DC supply and drives the transformer which connects the bus.

BACKGROUND AND PRIOR ART

A transceiver is a combination of transmitter / receiver functions in which both transmission and reception of signals happen. A transceiver IC contains both a transmitter and a receiver, which are combined and the circuitry for both share common resources in a single housing. The term transceiver generally applies to wireless communications devices such as cellular telephones, cordless telephone sets, handheld two-way radios, mobile two-way radios and also wired communication devices such as control instruments and data equipments. The transmission and reception can occur simultaneously or one at a time. For the later operation the receiver is deactivated while transmitting and vice versa. An electronic switch allows the transmitter and receiver to be connected to the same antenna / bus, and prevents the transmitter output from damaging the receiver. With a transceiver of this kind, at any time, either of the receiver or transmitter is active. This mode is called half duplex. Transmission and reception often, but not always, are done on the same frequency. Some transceivers are designed to allow reception of signals during transmission periods. This mode is known as full duplex, and requires that the transmitter and receiver operate on substantially different frequencies so the transmitted signal does not interfere with reception.

In the wired equipments, the data or signal are driven on a common path called a data bus.

The bus is connected with multi equipments ant it carries transmit or receive signals at any time meant for relevant equipments that follows the protocol of the networked system.

MIL-STD-1553 is a military standard that defines the mechanical, electrical, and functional characteristics of a serial data bus. This standard is commonly employed in spacecraft on-board data handling (OBDH) subsystems and in aircraft internal control and communication systems.

In the spacecraft and military application, different coding methods are being employed on the data.
Manchester code is one of them. The Manchester code (also known as Phase Encoding or PE) is a line code in which the encoding of each data bit has at least one transition and occupies the same time. It therefore has no DC component, and is self clocking, which means that it may be inductively or capacitively coupled, and that a clock signal can be recovered from the encoded data. The present invention, BE5063, is a two channel Transmitter Driver and Receiver pairs (Transceiver) on a monolithic substrate. This Monolithic IC is capable of driving a load up to 900mA at 5V DC supply. Transmitter is enabled by TXINH control pin and receiver is enabled by RXEN control pin. Either transmitter or receiver is enabled at any time by enabling their respective control pins.

The present invention, BE5063, is designed and developed addressing the bipolar process technology and it operates on a single power supply. The BE5063, as a receiver, accepts input data from the data bus, processes it and provides two output complementary signals and as a transmitter, accepts Transistor Transistor Logic (TTL) compatible transmit data, processes it and drives the transformer / stub. Design of this transceiver calls for attention to waveform purity and minimal zero crossover distortion. A unique circuit design has been employed to boost the voltage level at the input of the transmit driver. The output driver has in built load short circuit protection feature. The physical layout has been specially designed to take care of the drive and internal thermal power dissipation. Each channel of the dual transceiver is completely separate from the other and fully independent. Each channel has a separate supply pins, a feature that enables to operate from different power lines. Hence, each channel may be connected to drive different data bus independently.

US8050750 titled "Event discrimination using unipolar and bipolar signal differences" describes a method of sensing a unipolar and bipolar signal at the tissue site and detects a response to these signals. It discriminates the near field and far field events and compares the event features determined from the unipolar and bipolar signals, therefore, has medical application.

US7881323 titled "Configurable ASIC for use with a programmable I/O module" describes the application specific integrated circuit (ASIC) that can be used with an I/O device. The ASIC includes a pin interface, data interface, digital section and an analog section wherein the pin interface supports the analog and digital signal communication and the data interface supports the digital signal communication. This programmable circuitry enables the ASIC to support various I/O functions.

SUMMARY OF THE INVENTION
This invention proposes an improved monolithic Two Channel Transceiver Bipolar Application Specific Integrated Circuit (ASIC) device having two separate, identical channels 101, 102 of transceiver pairs, having two pair of TTL inputs, two pair of differential inputs, two control inputs, two enable inputs and two pair of TTL out puts and two pairs complementary outputs being MIL-STD-1553B compliant wherein each channel comprises of one or more transmit sub blocks (Transmitter) The building blocks in this invention include a logic unit 101a, one or more wave shaping networks 101b and 101c, and one or more output drivers 101d and 101e.

Additionally, each channel comprises one or more receiving sub blocks (Receiver) including a limiter and input amplifier101f, a reference101g, an active filter 101j, one or more comparators 101h, 101k and one or more output logic blocks 101i, 1011.

BRIEF DESCRIPTION OF THE DRAWINGS

Figure 1 shows the block diagram of the two channel Transmitter Driver and Receiver pairs (Transceiver) for MIL-STD-1553B applications.

Figure 2 shows the physical design view of the Application Specific Integrated Circuit (ASIC).

Figure 3 shows the pin diagram of the packaged Two Channel Transceiver ASIC device with signal names.

Figure 4 shows the typical application circuit of the Two Channel Transceiver ASIC device with the direct and transformer coupling configurations

DETAILED DESCRIPTION OF THE ACCOMPANYING EMBODIMENTS

Figure 1: Illustrates a block diagram 100, with two similar channel transceivers 101 and 102. Channel 101 consists of transmit sub blocks such as logic unit 101a, wave shaping network 101b and 101c, output drivers 101d and 101e, receiver sub blocks such as limiter and input amplifier 101f, reference 101g, active filter 101j, comparators 101h, 101k and output logic blocks 101i, 1011. In the transmitter portion, the TTL compatible inputs at TXINA 101p and TXINA_B 101q are fed to the logic unit. The output TXOUT 101u and TXOUT_B 101v directly drive the transformer / stub loads. TXINH named as 101y is a control signal. Power Supplies VCCA 101m, VDDA 101n, bootstrap ABS 101o, and GNDA 101t are other pins.

The supplies of logical unit VCCA 101m and high current output drivers VDDA 101n are isolated. The receiver inputs RXINA 101r and RXINA_B 101s are fed to the limiter and amplifier 101f. The receiver section accepts biphasic-modulated Manchester II coded Bipolar data from a MIL-STD-1553 data bus and produces TTL compatible outputs RXOUTA 101w and RXOUTA_B 101x which are enabled by the control signal RXENA 101. The Monolithic IC operates on a Single 5V DC supply. The transmitter section accepts Manchester II biphasic TTL Data at the inputs and converts this data into differential phase modulated signals TXOUTA 101u and TXOUTA_B 101 v that drives the MIL-STD-1553 Data bus through a short stub or through a transformer. Transmitter output is disabled by asserting TXINHA 101y at logic "1" or by placing both TXINA 101p and TXINA_B 101q at the same logic level.

Figure 2 illustrates a physical design of the ASIC. The physical design topography of the ASIC exhibits innovation in its layout by incorporating layer isolations and protection guards required for providing higher current drive capability to the devices through a process of fabrication. The chip size of the integrated circuit is approximately estimated as 3.988 mm against 5.193mm and includes 28 pads in the design.

Figure 3 illustrates the pin configuration of an ASIC device fabricated with a bipolar dual channel transceiver. The tested die is attached to a substrate of lead frame and connected by gold bond wires from the bond pads to the external leads and then encapsulated to form a 28 pin device. The device is packaged as a 28 pin ceramic DIP and involves a bipolar process. The input pins of the two channels transceiver TXINA, TXINA_B, TXINHA, TXINB, TXINB_B, TXINHB, RXINA, RXINA_B, RXINB, RXINB_B, RXENA and RXENB correspond to 301, 302, 303, 314, 313, 312, 323, 322, 320, 321, 307 and 308 respectively. Similarly, the output pins of the two channel transceiver TXOUTA, TXOUTA_B, RXOUTA, RXOUTA_B, TXOUTB, TXOUTB_B, RXOUTB, and RXOUTB_B correspond to 327, 326, 310, 309, 316, 317, 305 and 306 respectively. 315 and 328 indicate the grounding for the pin. VCCA, VCCB, VDDA, VDDB, ABS and BBS correspond to 304, 311, 324, 319,325 and 318 respectively are the supplies of the device.

The present invention 100 has two channels 101 and 102.Each channel consists of transmitter and receiver pair. Transmitter section accepts bi-phase TTL data at the inputs TXIN and TXIN_B. The transmitter output drives the data bus either through a short Stub (1:2.5 ratio transformers) or a long Stub.

The signal is typically 7.0 Volts P-P across the Bus load. The signal at "TXINH" 101y controls the transmitter output irrespective of TX input data. Logic "1" applied to the "TXINH" 101y takes priority over the condition of the data inputs and disables the transmitter and puts the Transmitter in the high impedance state. When both data inputs are held logic low or high, the transmitter output attains high impedance state.

Receiver section accepts bi-phase differential data at the input and produces TTL signals at the output. The input is not a pure square wave, and it is converted into square wave by input circuitry and wave shaping network. The limiter has a protection circuit in the event of high input voltage. The outputs of the receiver represent positive and negative excursions of the input beyond a pre-determined threshold. The pre-set internal thresholds will detect data bus signals exceeding 720mV P-P across the input terminals of the receiver. The receiver has a Band Gap voltage references and fast comparators for accurate comparison. A logic low signal (logic "0") at the "RXEN" keeps the both RXOUT signals at logic "0". Each receiver channel can recognize as low as 170 mv pp signals to produce a standard output levels. It has a no response range of 0-120mV, a feature wherein, the noise level below 120 mV will be suppressed and will not hinder the performance of the circuit.

Figure 4: Illustrates the typical application circuit of two-channel transceiver ASIC device. The transmitter output TXOUT 401a, TXOUT_B 401b drive the data bus either through a short Stub corresponds to 401(direct coupling,! :2.5 ratio transformers) or a Long Stub corresponds to 402(transformer coupling). The signal is typically 7.0 Volts P-P across the Bus load. Short stub 401 connection is used when the distance to the data bus doesn't exceed a one foot maximum and Long stub 402 connection is used when the distance is longer.

WE CLAIM

1. An improved monolithic Two Channel Transceiver Bipolar Application Specific Integrated Circuit (ASIC) device having two separate, identical channels 101 and 102 of transceiver pairs, having two pair of TTL inputs, two pair of differential inputs, two control inputs, two enable inputs and two pair of TTL out puts and two pairs complementary outputs being MIL-STD- 1553B compliant wherein:

a. Each channel comprises of one or more transmit sub blocks (transmitter) including:

i. A logic unit 101a;

ii. One or more wave shaping networks 101b and 101c; and iii. One or more output drivers 101d and 101e;

b. Each channel comprises one or more receiving sub blocks (receiver) including:

i. A limiter and input amplifier101f;

ii. A reference101g;
iii. An active filte101j;
iv. One or more comparators 101h, 101k; and
v. One or more output logic blocks 101i, 1011.

2. An improved monolithic Two Channel Transceiver Bipolar Application Specific Integrated Circuit (ASIC) device as claimed in Claim 1 wherein the transmit sub blocks further has TTL compatible inputs at TXINA 101p and TXINA_B 101q which are fed to the logic unit.

3. An improved monolithic Two Channel Transceiver Bipolar Application Specific Integrated Circuit (ASIC) device as claimed in Claim 1 wherein the output TXOUT 101u and TXOUT_B 101v directly drive the transformer and stub loads.

4. An improved monolithic Two Channel Transceiver Bipolar Application Specific Integrated Circuit (ASIC) device as claimed in Claim 1 further comprising Power Supply VCCA 101m, VDDA 101n , bootstrap ABS 101o, and GNDA 101t pins.

5. An improved monolithic Two Channel Transceiver Bipolar Application Specific Integrated Circuit (ASIC) device as claimed in Claim 1 wherein the supplies of logical unit VCCA 101m and high current output drivers VDDA 101n are isolated.

6. An improved monolithic Two Channel Transceiver Bipolar Application Specific Integrated Circuit (ASIC) device as claimed in Claim 1 wherein the receiver inputs RXINA 101r and RXINA_B 101s are fed to the limiter and amplifier 101f.

7. An improved monolithic Two Channel Transceiver Bipolar Application Specific Integrated Circuit (ASIC) device as claimed in Claim 1 wherein the receiver section accepts biphasic-modulated Manchester II coded Bipolar data from a MIL-STD-1553 data bus and produces TTL compatible outputs RXOUTA 101w and RXOUTA_B 101x which are enabled by the control signal RXENA 101.

8. An improved monolithic Two Channel Transceiver Bipolar Application Specific Integrated Circuit (ASIC) device as claimed in Claim 1 wherein the Monolithic IC operates on a Single 5V DC supply.

9. An improved monolithic Two Channel Transceiver Bipolar Application Specific Integrated Circuit (ASIC) device as claimed in Claim 1 wherein the transmitter section accepts Manchester II biphasic TTL Data at the inputs and converts this data into differential phase modulated signals, TXOUT 101u and TXOUT_B 101v that drives the MIL-STD-1553 Data bus through a short stub or through a transformer.

10. An improved monolithic Two Channel Transceiver Bipolar Application Specific Integrated Circuit (ASIC) device as claimed in Claim 1 wherein the transmitter output is disabled by asserting TXINH 101y at logic "1" or by placing both TXIN and TXIN_B at the same logic level.

11. An improved monolithic Two Channel Transceiver Bipolar Application Specific Integrated Circuit (ASIC) device as claimed in Claim 1 wherein the device has fully independent channels and each channel has a separate Transmitter and Receiver pair such that each channel has separate power supply pins which enables operation from different power lines and to drive different data bases with no interaction.

12. An improved monolithic Two Channel Transceiver Bipolar Application Specific Integrated Circuit (ASIC) device as claimed in Claim 1 wherein the receiver can accept as low as 170mVpp differential inputs to produce a standard output and has a noise thresh hold level of 120mvpp.

13. An improved monolithic Two Channel Transceiver Bipolar Application Specific Integrated Circuit (ASIC) device as claimed in Claim 1 wherein the circuitry in the device can clamp a large input signal that arrive at the inputs where the outputs from the receiver are TTL compatible and operates on a Single 5V DC supply.

14. An improved monolithic Two Channel Transceiver Bipolar Application Specific Integrated Circuit (ASIC) device as claimed in Claim 1 wherein each transmitter channel is provided with independent bootstrapping pins, ABS for channel A 101 and BBS of channel B 102 to enable higher input voltage to be
available for the drive circuit by pulling these pins externally through a capacitor.

15. An improved monolithic Two Channel Transceiver Bipolar Application Specific Integrated Circuit (ASIC) device as claimed in Claim 1 wherein the output drivers 101d and 101e are designed for a peak drive current of 900mA and have a load short circuit protection feature such that the circuit accepts TTL compatible inputs and operates on a Single 5V DC supply.

16. An improved monolithic Two Channel Transceiver Bipolar Application Specific Integrated Circuit (ASIC) device as claimed in Claim 1 wherein, the dual Transceivers 101 and 102 with all features, is physically designed to form the layout, fabricated using Bipolar process, tested and assembled in a single 28pin DIP package.

17. An improved monolithic Two Channel Transceiver Bipolar Application Specific Integrated Circuit (ASIC) device as claimed in Claim 1 wherein the device operates in a wider temperature range of - 55 °C to 125 °C.