DESC:TECHNICAL FIELD
[0001] The present disclosure relates, in general, to memory devices and semiconductors, and more specifically, relates to a two-dimensional (2D) transition metal dichalcogenide-based analog memory device.

BACKGROUND
[0002] The development of next-generation More-than-Moore computing architectures, built upon novel materials, necessitates the realization of onboard memories with enhanced capabilities. A fast and robust memory scheme has always been desirable which is power efficient, has multiple program states, capable of heterogeneous integration and have non-volatile states.
[0003] Conventional fast memories, like cache, static random access memory (SRAM), and dynamic random access memory (DRAM), are volatile in nature, demanding frequent refreshing for memory to be retained. While rapid SRAM is costly to manufacture and occupies substantial space, more efficient DRAM is more economical and denser but necessitates faster refresh rates. Meanwhile, non-volatile memory options such as flash memory are more affordable but operate at slower speeds. The emerging consideration of true non-volatility in computing memories like cache, SRAM, and DRAM presents an opportunity for substantial performance improvements. Given the significance and potential for enhancing existing memory technologies, it becomes essential for forthcoming technologies to subsequently address these existing challenges. Furthermore, a few existing studies in this field have demonstrated a memory effect in MoS2-based devices and attributed it to the involvement of trap states. The fabrication of such demonstrated devices required intricate processes and specific working architectures to drive the memory phenomenon.
[0004] 2D materials provide a versatile platform for future devices and circuits that are highly scalable and compatible with multiple functional blocks. These materials offer a range of properties suitable for encoding memory, including resistivity, magnetic moment, charge, and spin, among other well-known and documented parameters. Transition Metal Dichalcogenides (TMDs) represent a specific class of 2D materials with semiconducting characteristics, making them an attractive option for logic and memory applications.
[0005] Therefore, there is a desire to develop a memory solution that harnesses the phenomenon of inverse piezoelectricity in TMDs as it can function as memory. TMDs exhibit a significant piezoelectric coefficient, which quantifies the crystal deformation resulting from an applied electric field. This deformation in the crystal structure induces alterations in the resistance of device contacts, thereby enabling the programming of memory states within the TMD-based devices.

OBJECTS OF THE PRESENT DISCLOSURE
[0006] An object of the present disclosure is to provide a device that leverages the distinct attributes of two-dimensional materials to achieve memory states, ushering in enhanced data storage capabilities compared to traditional methods.
[0007] Another object of the present disclosure is to provide a device where optimal performance is achieved through the utilization of the bottom program gate and the top sense gate configuration, enhancing switching efficiency and power efficiency.
[0008] Another object of the present disclosure is to provide a device that brings forth dual functionality, enabling the device to function as both a memory component and a field-effect transistor (FET), thereby streamlining circuit design and enhancing resource utilization.
[0009] Another object of the present disclosure is to provide a device with an associated roadmap outlining strategies for elevating performance, scalability, and compatibility with existing complementary metal-oxide-semiconductor (CMOS) technologies.
[0010] Yet another object of the present disclosure is to provide a device that highlights a comprehensive approach to further advancements in the field of memory and transistor integration.

SUMMARY
[0011] The present disclosure relates in general, to memory devices and semiconductors, and more specifically, relates to a two-dimensional (2D) transition metal dichalcogenide-based analog memory device. The main objective of the present disclosure is to overcome the drawbacks, limitations, and shortcomings of the existing device and solution, by providing a two-dimensional (2D) memory device is disclosed, that includes a source terminal in electrical contact with one or more layers of transition metal dichalcogenide (TMD) material, and a drain terminal in electrical contact with the one or more layers of TMD material. The device includes a channel region formed by the one or more layers of TMD material, which is defined between the source terminal and the drain terminal. A control terminal is formed on the substrate and is configured to operate as both a program gate and a sense gate. The program gate and the sense gate are positioned either at the bottom or top of the one or more layers of TMD material. An electric field is applied between the drain terminal, the source terminal, and the control terminal to induce strain in the one or more layers of TMD material through inverse piezoelectric effects. This induced strain modulates the electronic properties of the TMD material, enabling the memory device to operate in a plurality of distinct resistance states. The memory effect is achieved through the modulation of these electronic properties.
[0012] Further, the control terminal may include a program gate oxide and a sense gate oxide as insulating materials between the channel region and the corresponding gates. The one or more layers of TMD material of form MX2 (M-Transition Metal, X-Chalcogen) can be selected from materials such as Molybdenum Disulfide (MoS2), Tungsten Disulfide (WS2), Molybdenum Diselenide (MoSe2), Tungsten Diselenide (WSe2), or any combination thereof. The TMD material is realised in the channel region through methods, including but not limited to, chemical vapor deposition (CVD), molecular beam epitaxy (MBE), or exfoliation. The memory state can be accessed by performing electrical operations through the source terminal and drain terminal, with or without using the control terminal.
[0013] The electric field can be applied in vertical, horizontal, or combined directions across the TMD material to modulate its electronic properties and switch between at least two distinct resistance states, which correspond to a low resistance state (LRS) and a high resistance state (HRS). The strain induced between the source terminal, drain terminal, and control terminal is configured to provide the plurality of distinct resistance states when subjected to an electric field with varying intensity, duration, and polarity. The strain can be either in-plane, out-of-plane, or a combination of both relative to the TMD material, and is modulated to achieve discrete resistance states for volatile, non-volatile memory, or any combination thereof. The memory device operates as a field-effect transistor (FET), with the memory states controlled by resistance changes induced through inverse piezoelectricity.
[0014] Various objects, features, aspects, and advantages of the inventive subject matter will become more apparent from the following detailed description of preferred embodiments, along with the accompanying drawing figures in which like numerals represent like components.

BRIEF DESCRIPTION OF THE DRAWINGS
[0015] The following drawings form part of the present specification and are included to further illustrate aspects of the present disclosure. The disclosure may be better understood by reference to the drawings in combination with the detailed description of the specific embodiments presented herein.
[0016] FIG. 1A to FIG. 1C illustrates exemplary bandgap modulation in monolayer MoS2 using biaxial strain.
[0017] FIG. 2A illustrates an exemplary device architecture capable of functioning as memory and FET and fabrication process overview, in accordance with an embodiment of the present disclosure.
[0018] FIG. 2B illustrates an unstrained MoS2 under contact, in accordance with an embodiment of the present disclosure.
[0019] FIG. 2C illustrates application of programming field from top to bottom results in uniaxial tensile strain in X-axis, in accordance with an embodiment of the present disclosure.
[0020] FIG. 2D illustrates reversed programming field results in Y-axis uniaxial strain, in accordance with an embodiment of the present disclosure.
[0021] FIG. 3A illustrates an exemplary graphical view of memory signature in CVD MoS2 FETs invoked using inverse piezoelectric programming and erase pulses leading to Low Resistance State (LRS) and High Resistance States (HRS) while functioning as a FET with superimposed memory state, in accordance with an embodiment of the present disclosure.
[0022] FIG. 3B illustrates an excellent separation in LRS and HRS state graphically when memory state is read out across the device, in accordance with an embodiment of the present disclosure.
[0023] FIG. 3C illustrates an exemplary graphical view of separation of LRS and HRS states as a function of switching field intensity to program memory, in accordance with an embodiment of the present disclosure.
[0024] FIG. 3D illustrates an exemplary graphical view of separation of LRS and HRS with change in peak field and range shifting from program gate towards contacts till failure, in accordance with an embodiment of the present disclosure.
[0025] FIG. 4A illustrates an exemplary graphical view of relationship between the switching ratio and the duration of program/erase times, in accordance with an embodiment of the present disclosure.
[0026] FIG. 4B depicts a plot showing the results of conducting 100 program/erase cycles with state sensing after each cycle, in accordance with an embodiment of the present disclosure.
[0027] FIG. 4C depicts a result of 100 program/erase pulse operations of 200ns with subsequent read operation show enduring pulse programming trend with stabilized switching ratio after about 30 cycles, in accordance with an embodiment of the present disclosure
[0028] FIG. 4D depicts the concept of redundant programming using 200ns pulses to successively program and erase the memory for high switching ratio, in accordance with an embodiment of the present disclosure.
[0029] FIG. 5A depicts a graphical view that demonstrates relationship between channel length and switching ratio, in accordance with an embodiment of the present disclosure.
[0030] FIG. 5B depicts a graphical view that demonstrates the effect of contact width on the switching ratio, in accordance with an embodiment of the present disclosure.
[0031] FIG. 5C and FIG. 5D depicts a graphical view that demonstrates the concept of achieving multiple memory states by varying program fields while keeping the erase field constant, in accordance with an embodiment of the present disclosure.
[0032] FIG. 6A depicts a graphical view that demonstrates time-dependent behavior of HRS and LRS, in accordance with an embodiment of the present disclosure.
[0033] FIG. 6B depicts a graphical view that demonstrates temperature dependency of switching ratio, in accordance with an embodiment of the present disclosure.
[0034] FIG. 6C depicts a graphical view that demonstrates the impact of applying the same program/erase pulses on devices in ambient conditions. in accordance with an embodiment of the present disclosure.
[0035] FIG. 6D depicts a graphical view that demonstrates memory state switching using unipolar pulses applied for program/erase in accordance with an embodiment of the present disclosure.
[0036] FIG. 7 depicts a graphical view that demonstrates the programming characteristics and switching behavior of various Transition Metal Dichalcogenide (TMD) devices, in accordance with an embodiment of the present disclosure.
[0037] FIG. 8A depicts a contact mode atomic force microscopy (AFM) scan with program/erase field across conductive tip and sample to mimic LRS and HRS switching without contacts, in accordance with an embodiment of the present disclosure.
[0038] FIG. 8B and FIG. 8C depicts Kelvin Probe Force Microscopy (KPFM) work function maps of the LRS programmed region, in accordance with an embodiment of the present disclosure.
[0039] FIG. 8D and FIG. 8E depicts Kelvin Probe Force Microscopy (KPFM) work function maps of the HRS programmed region, in accordance with an embodiment of the present disclosure.
[0040] FIG. 9A depicts Raman spectra from pristine, Low Resistance State (LRS), and High Resistance State (HRS) regions, in accordance with an embodiment of the present disclosure.
[0041] FIG. 9B depicts the photoluminescence (PL) signal from pristine, LRS, and HRS regions, in accordance with an embodiment of the present disclosure.
[0042] FIG. 10 illustrates a roadmap towards high performance CMOS compatible inverse piezoelectricity governed RRAM memories and FETs, in accordance with an embodiment of the present disclosure.

DETAILED DESCRIPTION
[0043] The following is a detailed description of embodiments of the disclosure depicted in the accompanying drawings. The embodiments are in such detail as to clearly communicate the disclosure. If the specification states a component or feature “may”, “can”, “could”, or “might” be included or have a characteristic, that particular component or feature is not required to be included or have the characteristic.
[0044] As used in the description herein and throughout the claims that follow, the meaning of “a,” “an,” and “the” includes plural reference unless the context clearly dictates otherwise. Also, as used in the description herein, the meaning of “in” includes “in” and “on” unless the context clearly dictates otherwise.
[0045] Memories in computing systems are very crucial. The computing logic downscaling has been much more aggressive than the memory cell downscaling. Emerging trend of 3D power scaling scheme has accelerated the memory downscaling leading to denser memories. Yet the present CMOS compatible memories are largely non-volatile in nature and a suitable solution in emerging materials is being searched. A memory platform based out of novel 2D TMD materials whose growth and CMOS compatibility has been developed to an industrially acceptable extent is encouraged. The 2D layered nature of these materials allows for the 3D power scaling leading to a new class of memories with potential to dominate memory market for a long time to come.
[0046] The present disclosure relates, in general, to memory devices and semiconductors, and more specifically, relates to a two-dimensional (2D) TMD-based analog memory device. The memory platform to launch the memory technology in a proper 3D power scalable regime and heterogeneous integrability is provided in this disclosure beneficial to VLSI reliant technologies as well. The memory programming scheme and governing physics has been explored to such extent for the first time to suggest a roadmap to industry when these memories are commercialized.
[0047] The present disclosure relates to analog memory devices using 2D TMDs that are programmed using inverse piezoelectricity induced in-plane strain under the contact region. The analog memory devices utilizing 2D TMDs rely on in-plane strain through an out-of-plane program/erase field, operating on the same fundamental principle for other combinations of causation using field and resulting strain leading to memory effect. A memory program/erase field scheme is developed, accompanied by design guidelines, to attain multiple resistance states and robust programmability. Memories based on inverse piezoelectricity utilize in-plane or out-of-plane straining facilitated by an electric field in orthogonal direction and varying strengths to program the states. A technology improvement roadmap outlines the memory effect concerning program/erase field amplitude and its trends in relation to the peak field location between contacts and the program gate is given. The scalability trends pertinent to general device dimensions are explored to enhance the memory performance of the demonstrated devices. Process variations and treatments leading to improved memory performance relying on reported operating principles in this art have been suggested. The underlying physics behind observed memory phenomena in electronic devices due to piezoelectricity is developed.
[0048] The present disclosure outlines the significance of two-dimensional (2D) transition metal dichalcogenide (TMD) materials in the realm of novel materials surpassing conventional bulk semiconductors in memory functionality. The material governed transistor property control is a promising way to realize memories and control various electrical performance parameters of such field-effect transistors (FETs). 2D TMD-based memories have been demonstrated using MoS2 before, which had its origins believed to be in the trap states in the material. A robust physical explanation and model of such phenomena have been missing preventing the advent of commercially scalable memory technology. Carefully designed experiments and analysis reveal inverse piezoelectricity to be at play behind the working of such memories and provide a deterministic roadmap to scale the technology to be commercially viable. The technology must be Complementary Metal-Oxide-Semiconductor (CMOS) compatible for the most efficient and profitable adoption by existing industries and the processes used comply to them. Such a technology paves the way to use properties of novel materials and design FETs in a way that memory functionality can be realized. Better understanding and control of material properties can be used to design and maximize the device's performance.
[0049] The present disclosure involves both the utilization of inverse piezoelectricity-induced straining under contacts for the resistive random-access memory (RRAM) effect and a memory-switching scheme enabling the use of 2D material FETs for memory applications. The device is fabricated through the integration of backgated structures onto chemical vapor deposition (CVD) grown monolayer molybdenum disulfide (MoS2) on silicon dioxide (SiO2) substrates. The device can include a bottom program gate and a top sense gate arrangement, enhancing switching efficiency and power efficiency. However, the memory scheme was found to be universal and the MoS2 can be interchanged with similar 2D-TMDs.
[0050] In an aspect, the device operation relies on the utilization of inverse piezoelectricity achieved by applying a program/erase field between drain, source (VD=VS), and program gate (VG), leading to the establishment of a low resistance state (LRS) or high resistance state (HRS) based on the intensity and/or polarity of the applied field and majority carrier. In another aspect, changing the intensity and/or polarity of the applied field reverses the resistance state and the channel material under contact experiences controlled strain. This strain modifies the electronic affinity of the two-dimensional material (TMD) situated beneath the contacts, thus altering the resistance state of the device.
[0051] The present disclosure provides two-dimensional (2D) memory device is disclosed, that includes a monolayer or multilayer of transition metal dichalcogenide (TMD) material disposed on a substrate. The device includes a source electrode (also referred to as source terminal) and a drain electrode (also referred to as drain terminal), both in electrical contact with the monolayer of TMD material, with a channel region defined between these electrodes. A backgate (also referred to as control terminal) is formed on the substrate, configured to function both as a program gate and a sense gate, with the program gate positioned at the bottom of the monolayer of TMD material and the sense gate positioned at the top. An electric field is applied between the drain electrode, the source electrode, and the program gate to induce a strain in the monolayer of TMD material, wherein this strain modulates the bandgap of the TMD material.
[0052] The induced strain enables the memory device to operate in at least two distinct resistance states, thereby providing a memory effect through modulation of the electronic properties of the TMD material via an inverse piezoelectric effect. The TMD material can be selected from monolayer molybdenum disulfide (MoS2) or any combination thereof. The strain induced in the monolayer or multilayer of TMD material is uniaxial tensile strain along an axis defined by the source and drain electrodes. The source and drain electrodes are configured to isolate the program and sense gates from one another, preventing coupling between switching fields during memory operations. The program gate and sense gate are further configured to apply a vertical electric field across the monolayer of TMD material to modulate its electronic properties and switch between at least two distinct resistance states, namely a low resistance state (LRS) and a high resistance state (HRS). The strain induced in the monolayer of TMD material under the program gate provides the LRS when a positive programming field is applied and the HRS when a negative programming field is applied.
[0053] Further, strain modulation in the monolayer of TMD material is achieved by applying inverse piezoelectric programming pulses that vary in intensity and duration, allowing for a plurality of distinct resistance states. The program and sense gates are configured to operate with a vertical electric field of about 0.7 V/nm to achieve a high resistance state to low resistance state switching ratio of at least 10³. The induced strain in the monolayer of TMD material can be modulated to obtain a plurality of discrete resistance states for analog memory applications. The monolayer of TMD material is grown by chemical vapor deposition (CVD) on the substrate, and the device is fabricated using a back-gated structure. The memory device operates as a field-effect transistor (FET) with a gate-induced memory effect, wherein the memory state is maintained through strain-induced modulation of the bandgap in the monolayer of TMD material.
[0054] The advantages achieved by the device of the present disclosure can be clear from the embodiments provided herein. The device leverages the distinct attributes of two-dimensional materials to achieve memory states, ushering in enhanced data storage capabilities. Optimal performance is achieved through the utilization of a bottom program gate and a top sense gate configuration, enhancing switching efficiency and power efficiency. Moreover, the device brings forth dual functionality, enabling the devices to function as both memory components and Field-Effect Transistors (FETs), thereby streamlining circuit design and enhancing resource utilization. The associated roadmap outlines strategies for elevating performance, scalability, and compatibility with existing complementary metal-oxide-semiconductor (CMOS) technologies, highlighting a comprehensive approach to further advancements in the field. The invention discloses both the novel memory device architecture and the operating principal, as well as is the possible integration in VLSI circuits. The description of terms and features related to the present disclosure shall be clear from the embodiments that are illustrated and described; however, the invention is not limited to these embodiments only. Numerous modifications, changes, variations, substitutions, and equivalents of the embodiments are possible within the scope of the present disclosure. Additionally, the invention can include other embodiments that are within the scope of the claims but are not described in detail with respect to the following description.
[0055] FIG. 1A to FIG. 1C illustrates exemplary bandgap modulation 100 in monolayer MoS2 using biaxial strain.
[0056] FIG. 1A to FIG. 1C illustrates the impact of biaxial strain on the bandgap of monolayer molybdenum disulfide (MoS2). The graph depicts the bandgap energy levels of strained MoS2 under different conditions, with tensile strain (shown in FIG. 1A) and compressive strain (shown in FIG. 1C) exhibiting distinct trends in comparison to the unstrained structure (shown in FIG. 1B). Such bandgap modulation opens possibility to modulate electronic properties of MoS2 which motivated observing memory effect in MoS2 field-effect transistor (FETs) using strain induced using inverse piezoelectric effect.
[0057] The inverse piezoelectric coefficients, like d11, d12, d26, d31, d33 among known coefficients, coupled with direction of applied state switching pulses allow for excellent separation between memory states at lower programming fields. The universality of the inverse piezoelectricity effect-based memory is demonstrated using all popular TMDs and commonly used metal contacts.
[0058] The studies have shown the strain to govern the available carries in a region. The in-plane strain is programmed under the contacts with the vertically applied field between the source/drain and program gate. Material analysis confirms the strain to be uniaxial and tensile in nature. Apart from the piezoelectricity, the anisotropy in armchair and zigzag directions in TMDs allows two distinct uniaxial tensile strains dominant in x or y direction depending upon the direction of applied programming fields.
[0059] FIG. 2A illustrates an exemplary device architecture capable of functioning as memory and FET and fabrication process overview, in accordance with an embodiment of the present disclosure.
[0060] Referring to FIG. 2A, the 2D TMD-based analog memory device 100 harnessing the strain-induced resistance modulation in two-dimensional (2D) materials is disclosed. The present disclosure involves both the utilization of inverse piezoelectricity-induced straining under contacts for the RRAM memory effect and a memory-switching scheme enabling the use of 2D material FETs for memory applications.
[0061] The device 100 is fabricated through the integration of backgated structures onto chemical vapor deposition (CVD) grown monolayer molybdenum disulfide (MoS2) on silicon dioxide (SiO2) substrates 110. Extensive exploration of this memory technology has been performed, leveraging SiO2 backgate for programming and sense gate (106, 108). Optimal performance is achieved through the utilization of a bottom program gate 106 and a top sense gate 108 configuration, enhancing switching efficiency and power efficiency. The device operation relies on the utilization of inverse piezoelectricity, achieved by applying a program/erase field between drain 104-2, source 104-1 (VD=VS) and program gate (VG) 106 to achieve a low resistance state (LRS) or high resistance state (HRS) state based on field intensity and/or polarity and majority carrier. Changing the intensity and/or reversing the polarity of the field switches resistance to other state. The channel material under contact gets strained which modulates the electronic affinity of the TMD under the contacts and changes the resistance state of the device.
[0062] By utilizing the SiO2 backgate as the programming gate, an exceptional high resistance state to low resistance state ratio of 103 using vertical programming fields of about 0.7V/nm is achieved. Apart from the memory behaviour demonstration, the scalability of the technology, operational limits, and pathways to improve the switching performance is investigated. The detailed understanding of operating physics down to the material level helps us to predict the extent of usability of reported technology. A suggested schematic illustrating the strain resulting from an applied field is presented below. It is noted that in the context of zigzag and armchair directions, anisotropy contributes to the disparity in strain observed upon field reversal.
[0063] The analog memory device 100 utilizing 2D TMDs includes contact region inducing an in-plane strain in the 2D TMD material through inverse piezoelectricity and a memory state associated with the induced in-plane strain in the 2D TMD material under the contact region. A program/erase field inducing out-of-field strain in the 2D TMD material and a memory state associated with the out-of-field strain induced in the 2D TMD material through the program/erase field. A design framework for achieving multiple resistance states in analog memory devices utilizing 2D TMDs and relying on piezoelectricity-induced in-plane or out-of-plane straining using electric fields.
[0064] In an embodiment, the two-dimensional (2D) memory device 100 is disclosed, that includes a source terminal in electrical contact with one or more layers of transition metal dichalcogenide (TMD) material 102 (also referred to as monolayer or multilayer of TMD material), and a drain terminal in electrical contact with the one or more layers of TMD material 102. The device 100 includes a channel region formed by the one or more layers of TMD material 102, which is defined between the source terminal 104-1 and the drain terminal 104-2. A control terminal is formed on the substrate 110 and is configured to operate as both a program gate 106 and a sense gate 108. The program gate 106 and the sense gate 108 are positioned either at the bottom or top of the one or more layers of TMD material. 102. An electric field is applied between the drain terminal 104-2, the source terminal 104-1, and the control terminal to induce strain in the one or more layers of TMD material through inverse piezoelectric effects. This induced strain modulates the electronic properties of the TMD material, enabling the memory device to operate in a plurality of distinct resistance states. The memory effect is achieved through the modulation of these electronic properties.
[0065] Further, the control terminal may include a program gate oxide and a sense gate oxide as insulating materials between the channel region and the corresponding gates. The one or more layers of TMD material 102 can be selected from materials such as Molybdenum Disulfide (MoS2), Tungsten Disulfide (WS2), Molybdenum Diselenide (MoSe2), Tungsten Diselenide (WSe2), or any combination thereof. The TMD material is used as a channel region through methods including chemical vapor deposition (CVD), molecular beam epitaxy (MBE), or exfoliation. The memory state can be accessed by performing electrical operations through the source terminal and drain terminal, with or without using the control terminal.
[0066] The electric field can be applied in vertical, horizontal, or combined directions across the TMD material 102 to modulate its electronic properties and switch between at least two distinct resistance states, which correspond to a low resistance state (LRS) and a high resistance state (HRS). The strain induced between the source terminal 104-1, drain terminal 104-2, and control terminal is configured to provide the plurality of distinct resistance states when subjected to an electric field with varying intensity, duration, and polarity. The strain can be either in-plane, out-of-plane, or a combination of both relative to the TMD material, and is modulated to achieve discrete resistance states for volatile, non-volatile memory, or any combination thereof. The memory device 100 operates as a field-effect transistor (FET), with the memory states controlled by resistance changes induced through inverse piezoelectricity.
[0067] FIG. 2B illustrates an unstrained MoS2 under contact, in accordance with an embodiment of the present disclosure. FIG. 2B depicts the unstrained MoS2 layer in its pristine state, positioned between the source and drain electrodes.
[0068] FIG. 2C illustrates application of programming field from top to bottom results in uniaxial tensile strain in X-axis, in accordance with an embodiment of the present disclosure. The application of programming field results in the generation of uniaxial tensile strain along the X-axis of the MoS2 lattice.
[0069] FIG. 2D illustrates reversed programming field results in Y-axis uniaxial strain, in accordance with an embodiment of the present disclosure. FIG. 2D presents the consequence of reversing the programming field direction, causing uniaxial strain along the Y-axis of the MoS2 lattice. These strains affect electrical properties of MoS2 in different ways to allow to use these FETs as memory devices.
[0070] FIG. 3A and FIG. 3B illustrates an exemplary graphical view of memory signature in CVD MoS2 FETs invoked using inverse piezoelectric programming and erase pulses leading to low resistance state (LRS) and high resistance states (HRS), in accordance with an embodiment of the present disclosure. The channel material under contact gets strained, which modulates electronic affinity of the TMD under the contacts and changes the resistance state of the device shown in FIG. 3A and FIG. 3B. FIG. 3A illustrates the device operating as an FET while storing atleast 2 distinct states as LRS and HRS. FIG. 3B illustrates the distinct resistance states of the device when programmed in LRS or HRS states.
[0071] The memory performance is analysed electrically and benchmarked the behavior by varying a parameter at a time. The switching ratio (HRS state/LRS state ratio) can be seen to be a function of applied field intensity for switching. Distinction in states can be seen for fields as low as 0.25V/nm, >4 ratio is seen at higher fields (~0.7V/nm) shown in FIG. 3B. Field concentration near the contacts switch states more efficiently than the higher field in oxide shown in FIG. 3C.
[0072] In one embodiment of the present disclosure, a memory operation is carried out using a field-effect transistor (FET) with a channel length (LC) of 4 µm and a width (W) of 10 µm, tested in a vacuum at room temperature (RT) using 1-second pulses. As illustrated in FIG. 3A, the transistor's transfer characteristics (ID?VG) were measured for the pristine state, low-resistance state (LRS), and high-resistance state (HRS), wherein the voltage sweep direction for the LRS was from VG = -60V to 60V and reversed for the HRS, with the gate voltage (VG) applied during the sweep capable of programming the contacts. FIG. 3B demonstrates the output characteristics (ID?VD) of a device operated under successive program/erase cycles at VG = 0V, which is achievable as the MoS2 FETs remain in the ON state at VG = 0V. FIG. 3C shows the dependence of the switching ratio on the program/erase fields, revealing that the memory effect starts to manifest at program/erase fields as low as 0.25V/nm, with a sharp increase in switching ratio as higher fields are applied. Finally, FIG. 3D depicts the impact of varying the location of the peak of a constant program/erase field near the contacts, resulting in a significantly high switching ratio.
[0073] FIG. 4A illustrates an exemplary graphical view of relationship between the switching ratio and the duration of program/erase times, in accordance with an embodiment of the present disclosure. As the program/erase times become shorter, the switching ratio decreases. Specifically, it mentions that a switching ratio of 2 is observed when using 200ns programming pulses, indicating fast memory operation. Memory performance with state switching time scales can be performed to determine the highest operating frequency of the memory. Pulses ranging from 200ns to 1s were used to program/erase the devices resistive random-access memory (RRAMs) and the switching is observed across all time scales and a better switching ratio is seen for longer switching pulses.
[0074] FIG. 4B depicts a plot showing the results of conducting 100 program/erase cycles with state sensing after each cycle, in accordance with an embodiment of the present disclosure. It demonstrates that the memory's performance remains stable over a large number of cycles. The switching ratio tends to stabilize after approximately 30 cycles. Endurance of the switching in devices can be tested for 100 switching cycles using 1s and 200ns programming pulses, respectively. Repeated program/erase operations do not degrade the memory behavior and the switching ratio gets stabilized for both slow and fast switching after a few switching cycles shown in FIG. 4B and FIG. 4C respectively.
[0075] FIG. 4C depicts a result of 100 program/erase pulse operations of 200ns with subsequent read operation show enduring pulse programming trend with stabilized switching ratio after about 30 cycles, in accordance with an embodiment of the present disclosure.
[0076] FIG. 4D depicts the concept of redundant programming using 200ns pulses to successively program and erase the memory for high switching ratio, in accordance with an embodiment of the present disclosure. The usage of redundant switching pulses leads to a higher switching ratio leading to robust and reliable memory behavior shown in FIG. 4D.
[0077] FIG. 5A depicts a graphical view that demonstrates relationship between channel length and switching ratio, in accordance with an embodiment of the present disclosure. As the channel length increases, the switching ratio also increases. It is suggested that isolating the program/erase field between the source and drain could potentially enhance memory performance. Better resolution in memory states is found as channel length increases.
[0078] The longevity of technology is contingent upon the degree of scalability the technology possesses. The channel lengths and contacting areas are varied to determine the scalability trends of the memory. Long channel length devices exhibit a higher switching ratio (4.5 µm channel device showed a 33% better HRS/LRS ratio compared to a 1 µm channel).
[0079] FIG. 5B depicts a graphical view that demonstrates the effect of contact width on the switching ratio, in accordance with an embodiment of the present disclosure. Minor improvement in switching ratio for 500nm wide contact finger suggesting an overall trend of better switching ratio as contact width decreases. Field peaking under thinner electrode is seen as a reason.
[0080] The isolation of contacts in longer channels is attributed to aiding in the prevention of coupling between the switching fields applied to the source and drain during the memory operation. Scalability trends regarding contacting area (with fixed channel width) revealed that the smaller the programming area under the electrode (i.e., thinner electrode) gives the better memory performance. This phenomenon can be attributed to the peaking concentration of switching fields under a smaller electrode area leading to more efficient programming. The trends suggest that higher contact resistance allows for higher field drop at contacts leading to more efficient switching behavior. The ability of multibit storage in any memory technology is an added advantage allowing for analog memory behavior and the possibility of highly dense memories.
[0081] FIG. 5C and FIG. 5D depicts a graphical view that demonstrates the concept of achieving multiple memory states by varying program fields while keeping the erase field constant, in accordance with an embodiment of the present disclosure.
[0082] Five stable states are achieved as a demonstration using a high erase field (LRS) and 4 different program fields (varied HRS fields). Multibit memories are possible in the reported technology due to control in the extent of straining that can be achieved by using distinct programming fields.
[0083] In one embodiment of the present disclosure, the scalability of the memory device was tested in a vacuum at room temperature (RT) using 1-second program/erase pulses. As shown in FIG. 5A, the switching ratio increases as the channel length increases, indicating that source and drain program/erase field isolation may contribute to enhanced memory performance. Furthermore, better resolution in memory states is observed with longer channel lengths. FIG. 5B demonstrates a minor improvement in switching ratio for a contact finger width of 500 nm, suggesting an overall trend of improved switching ratio as the contact width decreases, which may be attributed to field peaking under thinner electrodes. Additionally, as depicted in FIG. 5C and FIG. 5D, multiple memory states are achievable by varying the program fields while maintaining a constant erase field.
[0084] FIG. 6A depicts a graphical view that demonstrates time-dependent behavior of HRS and LRS, in accordance with an embodiment of the present disclosure. The FIG. 6A displays a time-dependent behavior of a device, where both the High Resistance State (HRS) and Low Resistance State (LRS) are monitored for over 3600 seconds. The graph reveals a trend of increasing resistance in LRS and decreasing resistance in HRS over time. This behavior is attributed to crystal relaxation under the device contacts. Consequently, the switching ratio stabilizes after approximately 2000 seconds.
[0085] Non-volatility of memory can lead to huge energy savings when a large heterogeneous integration is being considered and very high retention of bistable states in the programmed and erased state of the device is reported. Both states show an initial drift that eventually stabilizes. The crystal relaxation in the MoS2 under contacts allows for state drift which settles in ~2000s.
[0086] FIG. 6B depicts a graphical view that demonstrates temperature dependency of switching ratio, in accordance with an embodiment of the present disclosure. The switching ratio is dependent on straining the MoS2 crystal which becomes easier and more prominent as temperature rise and similar can be seen as improved memory behavior with increasing temperature. The MoS2 crystal has more freedom at higher temperatures to get strained and to a greater extent.
[0087] Furthermore, the switching behavior at different temperatures can be observed in the devices ranging from -73 °C to 73 °C and stable switching can be observed overall temperature range. The switching ratio visibly goes up with the operating temperature of memory operation as higher temperatures let the crystal relax quicker and to a greater extent.
[0088] FIG. 6C depicts a graphical view that demonstrates the impact of applying the same program/erase pulses on devices in ambient conditions, in accordance with an embodiment of the present disclosure. This leads to a notably high switching ratio of around 655.
[0089] These devices were operated in a high vacuum environment devoid of ambient adsorbates. The switching ability of these devices is tested in an ambient environment with ~40% relative humidity. The devices programmed in ambient exhibited an exceptional switching ratio of ~655, much higher than in vacuum operation.
[0090] FIG. 6D depicts a graphical view that demonstrates all the pulses applied for program/erase have exploited the higher possible field using a bipolar voltage scheme, in accordance with an embodiment of the present disclosure. Unipolar program/erase can also induce memory effect in FETs. P-type devices respond to negative unipolar scheme more efficiently. Modified interaction with ambient particles due to program/erase fields near contact edges assist in better switching as the electrostatic interaction is adversely affected due to strain-induced in and near contacts. The applicability of the unipolar voltage scheme is tested to induce switching in the memory state of devices as the proposed physics behind the operation of this memory lies in the inverse piezoelectricity effect which is dependent on the applied field intensity to switch the memory state. A scheme with positive polarity yields a better HRS/LRS ratio than a negative polarity scheme in the intrinsically n-type MoS2 devices and this trend is predicted to be reversed for p-type devices.
[0091] FIG. 7 depicts a graphical view that demonstrates the programming characteristics and switching behavior of Transition Metal Dichalcogenide (TMD) devices, in accordance with an embodiment of the present disclosure. The programming pulses shown to be universally operable on monolayer, multilayer TMD devices and independent from contact metal as well. Multilayer TMDs devices have switching ratio in 103 range. In the plot, Material (Contacting metal) is shown. P-type operation showed a reverse state switching which is well explained by findings from material analysis
[0092] To test the universality of this memory effect across other TMDs, the memory state switching fields were tested on other TMDs, and both monolayer and multilayer channels were contacted using different metals. All combinations exhibited competent HRS/LRS switching ratios where multilayer devices were found to be capable of a very high switching ratio in the order of 103 under similar operating conditions.
[0093] FIG. 8A depicts a contact mode atomic force microscopy (AFM) scan with program/erase field across conductive tip and sample to mimic LRS and HRS switching without contacts, in accordance with an embodiment of the present disclosure. Isolate the contact region effects from channel region effects contributing to the realization of the memory state switching behavior is proposed. A ‘contactless’ memory state switching scheme is investigated by using the electrostatic contact mode AFM method. A 5x5 µm2 region of MoS2 is programmed using a conductive AFM tip in contact mode with potentials on tip and program gate to mimic program (HRS) and erase (LRS) operation in 2 distinct regions.
[0094] FIG. 8B and FIG. 8C depicts Kelvin Probe Force Microscopy (KPFM) work function maps of the LRS programmed region, in accordance with an embodiment of the present disclosure. It is evident that LRS programming pulses increases the electron affinity of MoS2 by about 100 meV and has a uniform affinity distribution, resulting in lower resistance under the LRS programmed contacts.
[0095] Once the regions are programmed in specific states, Kelvin Probe Force Microscopy (KPFM) is performed to determine the work function change in the region. The LRS region shows a uniform increase in electron affinity by ~82meV and a highly continuous region results in less resistance under the electrode. This type of band alignment under the contact contributes to the overall lower resistance in the LRS state.
[0096] FIG. 8D and FIG. 8E depicts Kelvin Probe Force Microscopy (KPFM) work function maps of the HRS programmed region, in accordance with an embodiment of the present disclosure.
[0097] The line scan in FIG. 8D highlights that the electron affinity is not continuous across the HRS region. Some parts of the region exhibit electron affinities around 500 meV and -250 meV, creating unfavorable barriers for electron transport. Line scan A in FIG. 8E showcase a unique scenario where a grain of the MoS2 crystal exhibits a very high electron affinity, while the corresponding part in the pristine region has a very low electron affinity. This leads to the creation of very high barriers for electron transport.
[0098] The region programmed to mimic the HRS region exhibits a discontinuous distribution of electron affinity across the area resulting in local potential barriers due to affinity mismatch in close proximities leading to higher resistance in the region. Apart from the small local barriers within HRS programmed region, very high-affinity mismatches (~5.6eV) were seen in grains shared between HRS and pristine regions. Such discontinuity in electron affinity across HRS and shared regions between pristine and HRS regions presents very high electron affinity mismatch scenarios leading to a very high device resistance state.
[0099] FIG. 9A depicts raman spectra from pristine, Low Resistance State (LRS), and High Resistance State (HRS) regions, in accordance with an embodiment of the present disclosure. The spectra reveal an increased separation between the A1g and E2g modes. This separation is attributed to a decrease in carrier concentration. It is observed that more carriers are depleted in the HRS region. Both the A1g and E2g modes exhibit a blue shift, with the shift being higher in the HRS region compared to the LRS region. The higher I (A1g/E2g) ratio strongly suggests that the LRS and HRS regions experience uniaxial tensile strain along the x and y directions, respectively.
[00100] The change in electron affinity can be due to changes in band alignments which can have an origin to extrinsic doping or change in the crystal structure. Raman spectroscopy and photoluminescence (PL) analysis is used to ascertain changes in crystal if any dopants are not introduced in the system. A typical Raman spectrum for monolayer MoS2 has 2 peaks, A1g (~405 cm-1) and E2g (~385 cm-1) separated by ~20 cm-1. The Raman spectra reveal blue shifts in both A1g and E2g modes, ~0.7 cm-1 and ~0.13 cm-1 for HRS region and ~0.46 cm-1 and ~0.06 cm-1 for LRS region, respectively. These shifts in Raman peaks are characteristic of either uniaxial or biaxial in-plane tensile strain. An increase in separation between A1g and E2g modes (~0.57 cm-1 and ~0.4 cm-1 for HRS and LRS regions, respectively) compared to the pristine region is evident of decrease in carrier concentration in both regions which rules out the doping phenomena to cause fermi level shifts. The intensity ratio I (A1g/E2g) increases to 2.15 and 2.37 in HRS and LRS regions, respectively (1.70 in pristine), which signifies an emergence of in-plane tensile strain. The decrease of FWHM A1g and E2g modes signifies the emergence of tensile strain in LRS and HRS regions and leads to sharpening of these phonon modes accompanied with decrease in respective FWHMs. Individual behaviors of Raman modes suggest in-plane uniaxial tensile strain in LRS and HRS regions on the x-axis and y-axis, respectively. The HRS region is more carrier depleted than the LRS region.
[00101] FIG. 9B depicts the photoluminescence (PL) signal from pristine, LRS, and HRS regions, in accordance with an embodiment of the present disclosure. The PL signal unveils an increased bandgap in both the LRS and HRS regions, with a slightly more significant increase observed in the HRS region. This confirms the presence of y-axis uniaxial tensile strain. The inset highlights an increase in the B-A separation, where the LRS region has a higher value. This suggests that there are more carriers in the LRS state compared to the HRS state.
[00102] A typical PL spectroscopy shows monolayer MoS2 to have A (~1.88 eV), B (2.04 eV) and trion (1.72 eV) peaks. These peaks reveal important trends based on changes in bandgap due to emerging uniaxial tensile strain in LRS and HRS regions. The y-axis uniaxial tensile strain in HRS region results in a greater bandgap increase (~15.68 meV) than the x-axis uniaxial tensile strain in LRS region (~14.36 meV). These trends of increased bandgaps are approximately due to in plane tensile strain in either x or y-direction till ~3% strain. Furthermore, the energy separation between A and B peaks gives a qualitative value of carriers in the region. Pristine, HRS and LRS regions show a separation of ~152meV, ~153 meV, and 161 meV, respectively. This suggests the LRS region is richer in electrons as compared to the HRS region, whereas the increased separation of A and B peaks suggests a decrease in carrier concentration. This is in accordance with the increased electron affinities observed in KPFM scans as well.
[00103] FIG. 10 illustrates a roadmap towards high performance CMOS compatible inverse piezoelectricity governed RRAM memories and FETs, in accordance with an embodiment of the present disclosure.
[00104] The cause of the switching in memory states is identified which finds their roots in the inverse piezoelectrically induced strains in the MoS2 crystal under the contacts. This identification of operating physics helps us to predict the scope of improvement in this technology and extents till which similar trends can explain the functioning of memory. Benchmarking and analyzing these MoS2 device-based memories suggest that an exceptional switching ratio (>103) can be achieved by using high-k program gate dielectric, high field peak near small width contacts over a low defect long TMD channel in specific ambient/adsorbate. These RRAMs show a better switching ratio at elevated temperatures. From material analysis, it is observed ~1% tensile strain to be existing in program/erase regions, these trends and properties are reported to be consistent even at higher tensile strains and higher performance can be expected if such strains are achieved with advancements in material growth and processing. In this current scheme of fabrication and operation, these memories are reported to be CMOS compatible and highly scalable for future electronics needs.
[00105] Thus, the present invention overcomes the drawbacks, shortcomings, and limitations associated with existing solutions, and introduces a device that leverages the distinct attributes of two-dimensional materials to achieve memory states, ushering in enhanced data storage capabilities compared to traditional methods. Optimal performance is achieved through the utilization of the bottom program gate and the top sense gate configuration, enhancing switching efficiency and power efficiency. Moreover, the innovation brings forth dual functionality, enabling the devices to function as both memory components and field-effect transistors (FETs), thereby streamlining circuit design and enhancing resource utilization. The associated roadmap outlines strategies for elevating performance, scalability, and compatibility with existing complementary metal-oxide-semiconductor (CMOS) technologies, highlighting a comprehensive approach to further advancements in the field.
[00106] It will be apparent to those skilled in the art that the device of the disclosure may be provided using some or all of the mentioned features and components without departing from the scope of the present disclosure. While various embodiments of the present disclosure have been illustrated and described herein, it will be clear that the disclosure is not limited to these embodiments only. Numerous modifications, changes, variations, substitutions, and equivalents will be apparent to those skilled in the art, without departing from the spirit and scope of the disclosure, as described in the claims.

ADVANTAGES OF THE PRESENT INVENTION
[00107] The present disclosure provides a device that leverages the distinct attributes of two-dimensional materials to achieve memory states, ushering in enhanced data storage capabilities compared to traditional methods.
[00108] The present disclosure provides a device where optimal performance is achieved through the utilization of the bottom program gate and the top sense gate configuration, enhancing switching efficiency and power efficiency.
[00109] The present disclosure provides a device that brings forth dual functionality, enabling the device to function as both a memory component and a field-effect transistor (FET), thereby streamlining circuit design and enhancing resource utilization.
[00110] The present disclosure provides a device with an associated roadmap outlining strategies for elevating performance, scalability, and compatibility with existing complementary metal-oxide-semiconductor (CMOS) technologies.
[00111] The present disclosure provides a device that highlights a comprehensive approach to further advancements in the field of memory and transistor integration.

,CLAIMS:1. A two-dimensional (2D) memory device (100) comprising:
a source terminal (104-1) in electrical contact with one or more layers of Transition Metal Dichalcogenide (TMD) material;
a drain terminal (104-2) in electrical contact with the one or more layers of TMD material;
a channel region formed by the one or more layers of TMD material defined between the source terminal (104-1) and the drain terminal (104-2); and
a control terminal of the one or more layers of TMD material formed on the substrate (110) and configured to operate as both a program gate (106) and a sense gate (108), wherein the program gate and the sense gate are positioned in a combination of either bottom or top, of the one or more layers of TMD material (102), wherein an electric field is applied between the drain terminal (104-2), the source terminal (104-1), and the control terminal to induce strain through inverse piezoelectric in the one or more layer of TMD material (102), wherein the strain is configured to modulate electronic properties of the one or more layers of TMD material (102), and
wherein based on the induced strain in the one or more layer of TMD material (102), the memory device (100) is configured to operate in a plurality of distinct resistance states, providing a memory effect through the modulation of the electronic properties of the TMD material.

2. The device (100) as claimed in claim 1, wherein the control terminal comprises a program gate oxide and a sense gate oxide as insulating material between the channel region and corresponding gates (106, 108).

3. The device (100) as claimed in claim 1, wherein the one or more layers of the TMD material (102) is selected from MX2 (M-Transition Metal, X-Chalcogen) materials, like Molybdenum Disulfide (MoS2), Tungsten Disulfide (WS2), Molybdenum Diselenide (MoSe2), Tungsten Diselenide (WSe2), or any combination thereof.

4. The device (100) as claimed in claim 1, wherein the one or more layers of TMD material (102) is used as the channel region realised using any method not limited to combination of chemical vapor deposition (CVD), molecular beam epitaxy (MBE), and exfoliation.

5. The device (100) as claimed in claim 1, wherein memory state is accessed by performing electrical operations through the source terminal (104-1) and the drain terminal (104-2) with or without using the control terminal.

6. The device (100) as claimed in claim 1, wherein the electric field is applied in a vertical direction, a horizontal direction, or a combination thereof across the one or more layers of the TMD material (102) to modulate the electronic properties of the one or more layers TMD material so as to switch between at least two distinct resistance states of the plurality of distinct resistance states.

7. The device (100) as claimed in claim 6, wherein the at least two distinct resistance states correspond to a low resistance state (LRS) and a high resistance state (HRS).

8. The device (100) as claimed in claim 1, wherein the strain induced in the one or more layers of the TMD material (102) between the source terminal, (104-1), the drain terminal (104-2), and the control terminal is configured to provide the plurality of distinct resistance states, when subjected to the electric field with a combination of distinct intensity, duration and polarity.

9. The device (100) as claimed in claim 1, wherein the strain being either in-plane or out-of-plane, or a combination of in-plane and out-of-plane relative to the one or more layers of TMD material, wherein the induced strain in the TMD material (102) is modulated to obtain the plurality of discrete resistance states for volatile memory, non-volatile memory or any combination thereof.

10. The device (100) as claimed in claim 1, wherein the memory device operates as field-effect transistor (FET), with the memory states being controlled by resistance changes induced through the inverse piezoelectricity.