[0001] The present invention relates generally to the field of semiconductors. More particularly, the present disclosure relates to a layered controlled two-dimensional perovskite double gate junction-less heterojunction tunnel field-effect transistor.

BACKGROUND
[0002] Background description includes information that may be useful in understanding the present invention. It is not an admission that any of the information provided herein is prior art or relevant to the presently claimed invention, or that any publication specifically or implicitly referenced is prior art.
[0003] With technology getting smarter, gadgets are becoming smaller day-by-day. In order to make processing of such devices faster and to make them more efficient, components, such as Field Effect Transistors (FETs), Tunnel Field Effect Transistors (TFETs), Junction Field Effect Transistors (JFETs), Bipolar Junction Transistors (BJTs), and the like are used to configure said devices.
[0004] TFETs have proven their ability to be the next generation fast electronic device by making use of quantum mechanical tunneling as a switching mechanism. Many researches have been carried out on different types of TFET structures to enhance the performance of logic and analog devices. Heterojunction (HJ)-TFET has appeared to be one of the promising TFET structures in which lower work function material is used in the source and large work function material is used in channel/drain region of TFET to enhance tunneling probability and device performance. Moreover, various researchers have worked upon different materials, especially Silicon (Si), Germanium (Ge), Carbon, and graphene for formation of HJ-TFETs. However, there are various problems associated with HJ-TFET, such as fabrication challenges, interface problems and poor device performance.
[0005] Three dimensional (3D) perovskite material, such as Methyl ammonium lead iodide (CH3NH3PbI3) is characterized by tunable work function and thus, this material can be used to make homo junction TFET structure instead of two dimensional (2D) perovskite materials. However, this material is less stable than 2D perovskite in all environmental conditions.
[0006] Thus, there is a need in the art to provide a means to overcome above-mentioned and other problems, a device made up of low-cost material to gain the advantages of Heterojunction and to solve fabrication challenges for TFETs.

OBJECTS OF THE PRESENT DISCLOSURE
[0007] Some of the objects of the present disclosure, which at least one embodiment herein satisfies are as listed herein below.
[0008] It is an object of the present disclosure to provide a layered controlled two-dimensional perovskite double gate junction-less heterojunction tunnel field-effect transistor.
[0009] It is another object of the present disclosure to provide a transistor to enhance switching performance of a device by using material having lower work function in the source region and material having higher work function in the channel/drain region without any heterojunction.
[00010] It is another object of the present disclosure to provide a technique to mitigate fabrication challenges related to interface problems and lattice mismatches in formation of a heterojunction transistor.
[00011] It is another object of the present disclosure to provide a transistor for carrying out supercomputing applications.
[00012] It is another object of the present disclosure to provide a cost-effective, efficient, and low power consuming transistor.

SUMMARY
[00013] The present invention relates generally to the field of semiconductors. More particularly, the present disclosure relates to layered controlled two-dimensional perovskite double gate junction-less heterojunction tunnel field-effect transistor.
[00014] An aspect of the present disclosure pertains to layered controlled two-dimensional perovskite double gate junction-less heterojunction tunnel field-effect transistor. This transistor comprises a source region, a drain region, and a control region, where the control region may be configured to facilitate controlled flow of the charge carriers between the source region and the drain region. The transistor can be configured from bis-(phenethyl ammonium)-methyl ammonium lead iodide (C6H5(CH2)2NH3)2(CH3NH3)n-1PbnI(3n+1)), where the source region, the drain region, and the control region may be constituted from a first set of layers having a first work function, and a second set of layers and a third set of layers having a second work function distinct from the first work function, thereby facilitating the flow of the charge carriers between the source region and the drain region.
[00015] In an aspect, said transistor enhances switching performance of a device by using material having lower work function in the source region and material having higher work function in the channel/drain region without any heterojunction.
[00016] In an aspect, by creating junction-less transistor mitigate fabrication challenges related to interface problems and lattice mismatches in formation of said transistor can be mitigated.
[00017] In an aspect, said transistor is used for carrying out supercomputing applications.
[00018] In an aspect, the transistor is cost-effective, efficient, and low power consuming.

BRIEF DESCRIPTION OF DRAWINGS
[00019] The accompanying drawings are included to provide a further understanding of the present disclosure, and are incorporated in and constitute a part of this specification. The drawings illustrate exemplary embodiments of the present disclosure and, together with the description, serve to explain the principles of the present disclosure. The diagrams are for illustration only, which thus is not a limitation of the present disclosure.
[00020] FIG. 1 illustrates exemplary structural diagram of the proposed layered controlled two-dimensional perovskite double gate junction-less heterojunction tunnel field-effect transistor to illustrate its overall working in accordance with an embodiment of the present disclosure.

DETAILED DESCRIPTION
[00021] The following is a detailed description of embodiments of the disclosure depicted in the accompanying drawings. The embodiments are in such detail as to clearly communicate the disclosure. However, the amount of detail offered is not intended to limit the anticipated variations of embodiments; on the contrary, the intention is to cover all modifications, equivalents, and alternatives falling within the spirit and scope of the present disclosure as defined by the appended claims.
[00022] Each of the appended claims defines a separate invention, which for infringement purposes is recognized as including equivalents to the various elements or limitations specified in the claims. Depending on the context, all references below to the "invention" may in some cases refer to certain specific embodiments only. In other cases it will be recognized that references to the "invention" will refer to subject matter recited in one or more, but not necessarily all, of the claims.
[00023] The present invention relates generally to the field of semiconductors. More particularly, the present disclosure relates to a layered controlled two-dimensional perovskite double gate junction-less heterojunction tunnel field-effect transistor.
[00024] According to an aspect, the present disclosure discloses a layered controlled two-dimensional perovskite double gate junction-less heterojunction tunnel field-effect transistor , the transistor includes: a source region; a drain region; and a control region coupled between the source region and the drain region, and configured to facilitate controlled flow of the plurality of charge carriers between the source region and the drain region; wherein the source region, the drain region, and the control region of said transistor can be configured from a pre-defined material, such that the source region, the drain region, and the control region can be constituted from a first set of layers, a second set of layers, and a third set of layers of said material, respectively, wherein the first set of layers can have a first work function, and the second set of layers and the third set of layers can have a second work function that is distinct from the first work function, thereby facilitating the flow of the plurality of charge carriers between the source region and the drain region.
[00025] In an embodiment, the holes and electrons can be induced into the source region and control/drain region through the charge plasma technique.
[00026] In an embodiment, the source region, the drain region, and the channel region include metal electrodes with the specific metal work function to achieve desired profile i.e. p+-n-n+.
[00027] In another embodiment, the metal electrodes associated with the source region include Platinum and the metal electrodes associated with the drain region may include Aluminium.
[00028] In an embodiment, the transistor includes an insulating material, wherein the insulating material can be configured between the metal electrodes associated with the source region, the drain region, and the channel region to provide insulation between said regions.
[00029] In another embodiment, the insulating material can be Lithium Fluoride.
[00030] In an embodiment, the pre-defined material can include Ammonium Lead Iodide radical, Methyl radical, and Phenyl radical.
[00031] In an embodiment, the first set of layers can have three-dimensional (3D) structure, wherein the second set of layers and the third set of layers can have two-dimensional (2D) structure.
[00032] In an embodiment, number of layers in the second set of layers and the third set of layers are identical, and distinct from number of layers in the first set of layers.
[00033] In an embodiment, the plurality of charge carriers include any or a combination of electrons and holes.
[00034] FIG. 1 illustrates exemplary structural diagram of the proposed layered controlled two-dimensional perovskite double gate junction-less heterojunction tunnel field-effect transistor to illustrate its overall working in accordance with an embodiment of the present disclosure.
[00035] In an embodiment, as illustrated in FIG. 1, the proposed layered controlled two-dimensional perovskite double gate junction-less heterojunction tunnel field-effect transistor 100 (interchangeably referred to as junction-less transistor 100, or transistor 100, hereinafter) having a plurality of charge carriers (also, collectively referred to as charge carriers, and individually referred to as charge carrier, hereinafter). In an exemplary embodiment, the charge carriers can include any or a combination of electrons and holes.
[00036] In an embodiment, the layered controlled two-dimensional perovskite double gate junction-less heterojunction tunnel field-effect transistor 100 includes source region 108-1, a drain region 108-3, and a channel region 108-2, where the channel region 108-2 is coupled between the source region 108-1 and the drain region 108-3, thereby facilitating controlled flow of the charge carriers between the source region 108-1 and the drain region 108-3.
[00037] In an embodiment, the source region 108-1, and the drain region 108-3, respectively and, channel region 108-2 of said transistor 100 can be configured from a pre-defined material that includes Ammonium Lead Iodide radical, Methyl radical, and Phenyl radical. In an exemplary embodiment, the pre-defined material can be bis-(phenethyl ammonium)-methyl ammonium lead iodide (C6H5(CH2)2NH3)2(CH3NH3)n-1PbnI(3n+1)) .
[00038] In an embodiment, the source region 108-1 can be constituted from a first set of layers, the drain region 108-3 can be constituted from a second set of layers, and the channel region 108-2 can be constituted from a third set of layers of said material. In another embodiment, the first set of layers can have a first work function whereas the second set of layers and the third set of layers can have a second work function. In an exemplary embodiment, the second work function can be distinct from the first work function, thereby facilitating the flow of the charge carriers between the source region 108-1 and the drain region 108-3. In another exemplary embodiment, the first set of layers can be having three-dimensional (3D) structure, whereas the second set of layers and the third set of layers can be having two-dimensional (2D) structure. In yet another exemplary embodiment, number of layers in the second set of layers and the third set of layers can be equal to each other, but distinct from number of layers in the first set of layers.
[00039] Further, in yet another embodiment, (C6H5(CH2)2NH3)2(CH3NH3)n-1PbnI(3n+1)) can be used to design double gate junction-less (DG-JL) TFET. In an embodiment, the work function of this material can be varied with its dimensionality (n), for example, the work function of (C6H5(CH2)2NH3)2(CH3NH3)n-1PbnI(3n+1)) is 1.55 eV for n = infinity, and 2.32 eV for n = 2. In an exemplary embodiment, n can represents the number of layers of the aforementioned material used. Therefore, in order to enhance tunnelling probability at source and drain (interchangeably, referred to as channel, hereinafter) interface, bulk layers, i.e., n = infinity in the source region 108-1 and bi-layers, i.e. n= 2 of (C6H5(CH2)2NH3)2(CH3NH3)2(MA)n-1PbnI(3n+1) in the channel/drain region 108-2/108-3of the DG-JL TFET 100.
[00040] In an embodiment, the layered controlled two-dimensional perovskite double gate junction-less heterojunction tunnel field-effect transistor 100 can be configured using charge plasma technique. In an exemplary embodiment, by employing the charge plasma technique, p+-source, n-channel, and n+-drain region can be induced in the (C6H5(CH2)2NH3)2(CH3NH3)n-1PbnI(3n+1)) bar, by using source polarity gate metal 102, control gate metal electrodes 106 and drain polarity gate metal 104 of pre-defined work functions.
[00041] In an implementation, due to difference in work functions of the source region 108-1, the drain region 108-3, and the channel region 108-2, the charge carriers can flow between the source region 108-1 and the drain region 108-3 in on-state. In another implementation, a channel 108-2 can be formed between the source region 108-1 and the drain region 108-3, where the formation of the channel 108-2 can be controlled by the control gate metal electrode 106, thereby facilitating controlled flow of the charge carriers between said regions.
[00042] In an exemplary embodiment, the metal electrodes 110-1 associated with the source region 108-1 can be made of Platinum and the metal electrodes 110-2 associated with the drain region 108-3 can be made of Aluminium.
[00043] In an embodiment, the layered controlled two-dimensional perovskite double gate junction-less heterojunction tunnel field-effect transistor 100 includes an insulating material 112 that can be configured between the metal electrodes 102, 104, and 106 associated with the source region 108-1, the drain region 108-3, and the channel region 108-2 to provide insulation between said regions. In an exemplary embodiment, the insulating material 112 can be made from Lithium Fluoride (LiF).
[00044] In an embodiment, said transistor 100 can enhance switching performance of a device by using material having lower work function in the source region 108-1 and material having higher work function in the channel/drain region 108-2 and 108-3 without any heterojunction. In another embodiment, said transistor 100 can be used for carrying out supercomputing applications.
[00045] In an embodiment, by creating junction-less transistor fabrication challenges related to interface problems and lattice mismatches in formation of said transistor 100 can be mitigated.
[00046] In an embodiment, said transistor 100 is cost-effective as only a single material is used in the formation. In another embodiment, said transistor 100 can be efficient and low power consuming.
[00047] While the foregoing describes various embodiments of the invention, other and further embodiments of the invention may be devised without departing from the basic scope thereof. The scope of the invention is determined by the claims that follow. The invention is not limited to the described embodiments, versions or examples, which are included to enable a person having ordinary skill in the art to make and use the invention when combined with information and knowledge available to the person having ordinary skill in the art.

ADVANTAGES OF THE PRESENT DISCLOSURE
[00048] The present disclosure provides layered controlled two-dimensional perovskite double gate junction-less heterojunction tunnel field-effect transistor.
[00049] The present disclosure provides a transistor to enhance switching performance of a device by using material having lower work function in the source region and material having higher work function in the channel/drain region without any heterojunction.
[00050] The present disclosure provides a technique to mitigate fabrication challenges related to interface problems and lattice mismatches in formation of a transistor.
[00051] The present disclosure provides a transistor for carrying out supercomputing applications.
[00052] The present disclosure provides a cost-effective, efficient, and low power consuming transistor.

Claims:1. A junction-less transistor having a plurality of charge carriers, the transistor comprising:
a source region;
a drain region; and
a control region coupled between the source region and the drain region, and configured to facilitate controlled flow of the plurality of charge carriers between the source region and the drain region;
wherein the source region, the drain region, and the control region of said transistor are configured from a pre-defined material, such that the source region, the drain region, and the control region are constituted from a first set of layers, a second set of layers, and a third set of layers of said material, respectively,
wherein the first set of layers is having a first work function, and the second set of layers and the third set of layers are having a second work function that is distinct from the first work function, thereby facilitating the flow of the plurality of charge carriers between the source region and the drain region.
2. The junction-less transistor as claimed in claim 1, wherein the plurality of charge carries are being induced at the source region and the control region through charge plasma technique.
3. The junction-less transistor as claimed in claim 1, wherein the source region, the drain region, and the control region comprise metal electrodes.
4. The junction-less transistor as claimed in claim 2, wherein the metal electrodes associated with the source region comprise Platinum and the metal electrodes associated with the drain region comprise Aluminium.
5. The junction-less transistor as claimed in claim 2, wherein the transistor comprises an insulating material, wherein the insulating material is configured between the metal electrodes associated with the source region, the drain region, and the control region to provide insulation between said regions.
6. The junction-less transistor as claimed in claim 4, wherein the insulating material is Lithium Fluoride.
7. The junction-less transistor as claimed in claim 1, wherein the pre-defined material comprises bis-(phenethyl ammonium)-methyl ammonium lead iodide (C6H5(CH2)2NH3)2(CH3NH3)n-1PbnI(3n+1)).
8. The junction-less transistor as claimed in claim 1, wherein the first set of layers is having three-dimensional (3D) structure, wherein the second set of layers and the third set of layers are having two-dimensional (2D) structure.
9. The junction-less transistor as claimed in claim 1, wherein number of layers in the second set of layers are equal to a number of layers in the third set of layers, and distinct from number of layers in the first set of layers.
10. The junction-less transistor as claimed in claim 1, wherein the plurality of charge carriers comprise any or a combination of electrons and holes.