Claims:1. A two-transistor dynamic random access memory (DRAM) cell comprising:
a read bit line;
a write bit line
a read word line
a write word line
a first indium-gallium-zinc-oxide (IGZO) transistor with a first gate region coupled to the write word line, a first controlled node region coupled to the write bit line, and a second controlled node region;
a second IGZO transistor with a second gate region, a third controlled node region coupled to the read word line, and a fourth controlled node region coupled to the read bit line, the second gate region of the second IGZO transistor coupled to the second controlled node region of the first IGZO transistor,
wherein the first IGZO transistor is included in a first layer created in a back end (BE) metal process stack of an integrated circuit chip and the second IGZO transistor is included in a second layer created in the BE metal process stack.
, Description:TECHNICAL FIELD
[0002] Examples described herein are generally related to two transistor (2T) gain dynamic random access (DRAM) memory cell with indium gallium zinc oxide (IGZO).
BACKGROUND
[0003] High density memories are becoming an increasingly important piece of a large level-4/ last-level cache (L4/LLC) memory between a processor and main or system memory. An ability to fabricate dense memories with a low impact on a semiconductor process to manufacture processors and associated L4/LLC memories are of great interest. Multi-core processors have magnified the need to provide adequate memory bandwidth, e.g., higher density and closer proximity to cores of these multi-core processors. Types of memories intended for integration on a same die as a processor include static random access memory (SRAM) that may add little to no process costs to one transistor, one capacitor (1T-1C) embedded dynamic random access memory (eDRAM) that do add process costs but may have a higher bit density (e.g., smaller memory cell dimensions).
BRIEF DESCRIPTION OF THE DRAWINGS
[0004] FIG. 1 illustrates an example first cell.
[0005] FIG. 2 illustrates an example second cell
[0006] FIG. 3 illustrates example third cell.
[0007] FIG. 4 illustrates an example fourth cell.
[0008] FIG. 5 illustrates an example 3-dimensional view of the example fourth cell.
[0009] FIG. 6 illustrates an example layout scheme.
[0010] FIGS. 7A-L illustrate an example process to build an IGZO transistor.
[0011] FIG. 8 illustrates an example computing device.
DETAILED DESCRIPTION
[0012] In some examples, as mentioned above, 1T-1C eDRAM may be used as a type of high density on-die L4/LLC memory for a multi-core processor. However, concerns with a cost associated with this type of memory in terms of impacts on advanced complementary metal-oxide-semiconductor (CMOS) manufacturing process technologies may outweigh density benefits. Large silicon (Si) based dies that may approach or exceed 600 square millimeters (mm2) potentially have severely impacted process yields when including 1T-1C eDRAM as on-die L4/LLC memory. The severely impacted process yields may unacceptably add to a total system cost. Therefore, a need exists to have a type of memory for L4/LLC that has less of an impact on process costs and may also have simpler process steps that are closer to older types of CMOS manufacturing process technologies.