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TWO WIRE SERIAL VOLTAGE IDENTIFICATION PROTOCOL
RELATED APPLICATIONS
[0001] This application is related to commonly assigned and copending U.S.
Patent Application Serial No. 12/912,924 to Kraipak, et al, entitled Data Negotiation
Using Serial Voltage Identification Communication, which published as U.S. Patent
Application Publication No. 2011/015075. This application is related to commonly
assigned and copending U.S. Patent Application Serial No. 12/912,952 to Kraipak, et
al, entitled Time Negotiation Using Serial Voltage Identification Communication,
which published as U.S. Patent Application Publication No. 2011/015076. The
respective disclosures of these applications are incorporated herein by reference in
their respective entireties.
BACKGROUND
[0002] The subject matter described herein relates generally to the field of
electronic devices and more particularly to a system and method to implement a two
wire serial voltage identification protocol in electronic devices.
[0003] Electronic devices such as computer systems may include onboard
systems that consume significant amounts of power. In some situations, a user may
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be using the computer system for tasks that do not require the use of each onboard
system or that do not require each onboard system to function at fiiil power. In this
situation, the computer system may want to reduce power to specific onboard
systems by sending a signal from a processor to a voltage regulator associated with
the specific onboard systems.
[0004] In conventional computer systems, each voltage regulator must be
configured to communicate with the processor at a set frequency that is predetermined
by the processor. For example, if the processor is configured to
communicate at a frequency of 25 MHz, then each voltage regulator must
communicate at 25 MHz. If a voltage regulator is not capable of communicating at
the processor's pre-determined frequency, then the voltage regulator will not be able
to communicate with the onboard processor.
[0005] Accordingly systems and techniques to manage communication
between a processor and one or more voltage regulators may find utility.
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BRIEF DESCRIPTION OF THE DRAWINGS
[0006] The detailed description is described with reference to the
accompanying figures.
[0007] Fig. 1 is a schematic illustration of an exemplary electronic system
may be adapted to include a two-wire serial voltage identification protocol in
accordance with some embodiments.
[0008] Figs. 2A and 2B are timing diagrams which provide a schematic
illustration of an exemplary technique to establish communication by driving a data
bus, in accordance with some embodiments.
[0009] Fig. 3 is a flowchart illustrating operations in a method to implement a
two-wire serial voltage identification protocol in accordance with some
embodiments.
[0010] Fig. 4 is a timing diagram which provides a schematic illustration of an
exemplary technique for address-time negotiation in accordance with some
embodiments.
[0011] Fig. 5 is a timing diagram which provides a schematic illustration of an
exemplary technique for data rate negotiation in accordance with some
embodiments.
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[0012] Fig. 6 is a schematic illustration of an electronic device which may be
adapted to implement a two-wire serial voltage identification protocol in accordance
with some embodiments.
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DETAILED DESCRIPTION
[0013] Described herein are exemplary systems and methods to implement
transaction integrity in electronic devices. In the following description, numerous
specific details are set forth to provide a thorough understanding of various
embodiments. However, it will be understood by those skilled in the art that the
various embodiments may be practiced without the specific details. In other
instances, well-known methods, procedures, components, and circuits have not been
illustrated or described in detail so as not to obscure the particular embodiments.
[0014] Fig. 1 is a schematic illustration of an exemplary electronic system 100
which may be adapted to include a two-wire serial voltage identification protocol in
accordance with some embodiments. Referring now to Fig. 1, system 100 may
comprise a processor 101 (e.g., a central processing unit or an integrated circuit), a
plurality of voltage regulators 102/103/104/105, an open drain serial voltage
identification (SVID) data bus 106 and an open drain alert bus 108. In some
embodiments, the voltage regulators 102/103/104/105 may comprise any slave
device that is coupled to the SVID data bus 106 and the alert bus 108.
[0015] The processor 101 may be electrically coupled to each of the plurality
of voltage regulators 102/103/104/105 via the SVID data bus 106 and the alert bus
108. The SVID data bus 106 and the SVID clock bus 107 may facilitate serial
communication between the processor 101 and the plurality of voltage regulators
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102/103/104/105. In some embodiments of Fig. 1, a first one of the plurality of
voltage regulators 102/103/104/105 may communicate with the processor 101 at a
different frequency than a second one of the plurality of voltage regulators
102/103/104/105. For example, the voltage regulator VR-0 102 may communicate
with the processor 101 at 15 MHz, voltage regulator VR-1 103 may communicate
with the processor 101 at 20 MHz, voltage regulator VR-2 104 may communicate
with the processor 101 at 22 MHz, and voltage regulator VR-1 103 may
communicate with the processor 101 at 25 MHz, while the CPU may communicate
at 25 MHz.
[0016] In some embodiments the system 100 may implement a serial voltage
identification protocol which enables clock signal to be embedded in the
SVIDDATA bus 106. In operation, to establish communication, the CPU will drive
the SVID line to a logic low voltage. As soon as the SVID line goes low, the voltage
regulators will also start to drive the same SVID line low. All devices including the
CPU will hold the SVID line low based on their respective data rate (i.e., each
device stops driving the SVID line at a point in time determined by its individual
data rate). Thus, the SVID line will be held low for the maximum time by the
slowest device coupled to the SVIDDATA bus.
[0017] In some embodiments the system implements a protocol referred to
herein as a "Retum-to-Zero" format. Figs. 2A and 2B are timing diagrams which
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provide a schematic illustration of an exemplary technique to drive logic low or
logic high on a data bus, in accordance with some embodiments.
[0018] Referring to Fig. 2A, if the processor 101 wants to drive the
SVIDDATA bus 106 to a logic low (i.e., "0") then the processor drives the
SVIDDATA bus 106 to a logic high (i.e., "1") voltage for an amount of time
corresponding to one-quarter (1/4) of a bit time (i.e., a clock period) and then drives
the SVIDDATA bus 106 to a logic low (i.e., "0") voltage for an amount of time
corresponding to three-quarters (3/4) of a bit time.
[0019] By contrast, referring to Fig. 2B, if the processor 101 wants to drive
the SVIDDATA bus 106 to a logic high (i.e., "1") then the processor drives the
SVIDDATA bus 106 to a logic high (i.e., "1") voltage for an amount of time
corresponding to three-quarters (3/4) of a bit time (i.e., a clock period) and then
drives the SVIDDATA bus 106 to a logic low (i.e., "0") voltage for an amount of
time corresponding to one-quarter (1/4) of a bit time.
[0020] The pulse patterns depicted in Figs. 2A and 23 allows the system 100
to communicate with the plurality of voltage regulators in the system without a
formal clock bus. Fig. 3 is a flowchart illustrating operations in a method to
implement a two-wire serial voltage identification protocol in accordance with some
embodiments. Referring to Fig. 3, at operation 310 the processor 101 transmits a
wake-up signal on the SVIDDATA bus 106. In some embodiments the wake up
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signal may correspond to the logic low signal depicted in Fig. 2A. When the
respective voltage regulators 102-105 detect that the processor 106 is driving a logic
low signal on the SVIDDATA bus 106, the respective voltage regulators 102-105
may wake up from to start communication or perform other functions.
[0021] At operation 315 the processor initiates an address-time negotiation
process. One exemplary address-time negotiation process is described in commonly
assigned and co-pending U.S. Patent Application 2011/0154076. To initiate the
negotiation process the processor 106 again drives a logic "low" on the
SVIDDATAbus 106, as described with reference to Fig. 2 A.
[0022] Fig. 4 is a timing diagram which provides a schematic illustration of an
exemplary technique for address-time negotiation in accordance with embodiments
in which the processor 106 and the voltage regulators, operate at the data rates
described above. Referring to Fig. 4, the processor 101 will drive logic on the
SVIDDATA bus 106 for a time period corresponding to a point in time demarcated
by PI. Voltage regulator VR-0 will drive logic on the SVIDDATA bus 106 for a
time period corresponding to a point in time demarcated by P2, Voltage regulator
VR-1 will drive logic on the SVIDDATA bus 106 for a time period corresponding
to a point in time demarcated by P3. Voltage regulator VR-2 will drive logic on the
SVIDDATA bus 106 for a time period corresponding to a point in time demarcated
by P4. Voltage regulator VR-3 will drive logic on the SVID_DATA bus 106 for a
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time period corresponding to a point in time demarcated by P5. In the example
depicted in Fig. 4 the voltage regulator VR-0 is the slowest device so it will drive
logic on the SVIDDATA bus 106 for extra time as shown in the Fig. 4.
[0023] In operation, the devices coupled to the SVIDDATA bus 106 may
monitor the SVIDDATA bus 106 after they have stopped driving for logic low.
When each of the devices starts driving a logic low on the SVIDDATA bus 106,
each respective device may start an internal time negotiation counter till the device
detects a logic "low" on the bus. This time value on the internal time negotiation
counter corresponds to the l/4th t-bit time for each respective device. This value will
be shifted by 2-bits (multiplied by 4) to give the complete t-bit time (i.e., clock cycle
time) for the device.
[0024] In the embodiment depicted in Fig. 4, the voltage regulator VR-0 has
the slowest speed and the longest time period P2. Therefore the t-bit time calculated
will be equal to the VR-0 t-bit time, and the processor 101 may communicate with
the respective voltage regulators 102-105 at a data rate corresponding to the data rate
of VR-0. This ensures that all the devices are able to negotiate in the Address
Negotiation period
[0025] Referring back to Fig. 3, at operation 320 the processor 101 transmits
an Address Packet on the SVIDDATA bus 106. By way of example if the addressed
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device is VR-3 tiien each voltage regulator controller will receive the address, but
only VR-3 will respond and participate in the rest of the communication.
[0026] At operation 325 the processor initiates a data rate negotiation process.
Fig. 5 is a timing diagram which provides a schematic illustration of an exemplary
technique for data rate negotiation in accordance with some embodiments. Referring
to Fig. 5, to initiate the process, the processor drives logic low on SVIDDATA bus
106. At this point only VR-3 will drive Logic "low" on the bus (i.e., only VR3
participates in the data rate timing negotiation with processor 101). Therefore, the tbit
time will be established using the VR-3 t-bit time as shown in Figure 5. The
processor 101 and VR-3 may now communicate with each other at the new data rate
for the rest of the communication
[0027] In some embodiments a system 100 may be incorporated into an
electronic device which may be embodied as a computer system. Fig. 6 is a
schematic illustration of a computer system 600 in accordance with some
embodiments. The computer system 600 includes a computing device 602 and a
power adapter 604 (e.g., to supply electrical power to the computing device 602).
The computing device 602 may be any suitable computing device such as a laptop
(or notebook) computer, a personal digital assistant, a desktop computing device
(e.g., a workstation or a desktop computer), a rack-mounted computing device, and
the like.
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[0028] Electrical power may be provided to various components of the
computing device 602 (e.g., through a computing device power supply 606) from
one or more of the following sources: one or more battery packs, an alternating
current (AC) outlet (e.g., through a transformer and/or adaptor such as a power
adapter 604), automotive power supplies, airplane power supplies, and the like. In
some embodiments, the power adapter 604 may transform the power supply source
output (e.g., the AC outlet voltage of about llOVAC to 240VAC) to a direct current
(DC) voltage ranging between about 7VDC to 12.6VDC. Accordingly, the power
adapter 604 may be an AC/DC adapter.
[0029] The computing device 602 may also include one or more central
processing unit(s) (CPUs) 608. In some embodiments, the CPU 608 may be one or
more processors in the Pentium® family of processors including the Pentium® II
processor family, Pentium® III processors, Pentium® IV , CORE2 Duo processors,
or Atom processors available from Intel® Corporation of Santa Clara, California.
Alternatively, other CPUs may be used, such as Intel's Itanium®, XEONF"^, and
Celeron® processors. Also, one or more processors from other manufactures may be
utilized. Moreover, the processors may have a single or multi core design.
[0030] A chipset 612 may be coupled to, or integrated with, CPU 608. The
chipset 612 may include a memory control hub (MCH) 614. The MCH 614 may
include a memory controller 616 that is coupled to a main system memory 618. The
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main system memory 618 stores data and sequences of instructions that are executed
by the CPU 608, or any other device included in the system 600. In some
embodiments, the main system memory 618 includes random access memory
(RAM); however, the main system memory 618 may be implemented using other
memory types such as dynamic RAM (DRAM), synchronous DRAM (SDRAM),
and the like. Additional devices may also be coupled to the bus 610, such as multiple
CPUs and/or multiple system memories.
[0031] The MCH 614 may also include a graphics interface 620 coupled to a
graphics accelerator 622. In some embodiments, the graphics interface 620 is
coupled to the graphics accelerator 622 via an accelerated graphics port (AGP). In
some embodiments, a display (such as a flat panel display) 640 may be coupled to
the graphics interface 620 through, for example, a signal converter that translates a
digital representation of an image stored in a storage device such as yideo memory
or system memory into display signals that are interpreted and displayed by the
display. The display 640 signals produced by the display device may pass through
various control devices before being interpreted by and subsequently displayed on
the display.
[0032] A hub interface 624 couples the MCH 614 to an platform control hub
(PCH) 626. The PCH 626 provides an interface to input/output (I/O) devices coupled
to the computer system 600. The PCH 626 may be coupled to a peripheral
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component interconnect (PCI) bus. Hence, the PCH 626 includes a PCI bridge 628
that provides an interface to a PCI bus 630. The PCI bridge 628 provides a data path
between the CPU 608 and peripheral devices. Additionally, other types of I/O
interconnect topologies may be utilized such as the PCI Express^** architecture,
available through Intel® Corporation of Santa Clara, California.
[0033] The PCI bus 630 may be coupled to an audio device 632 and one or
more disk drive(s) 634. Other devices may be coupled to the PCI bus 630. In
addition, the CPU 608 and the MCH 614 may be combined to form a single chip.
Furthermore, the graphics accelerator 622 may be included within the MCH 614 in
other embodiments.
[0034] Additionally, other peripherals coupled to the PCH 626 may include,
in various embodiments, integrated drive electronics (IDE) or small computer
system interface (SCSI) hard drive(s), universal serial bus (USB) port(s), a
keyboard, a mouse, parallel port(s), serial port(s), floppy disk drive(s), digital output
support (e.g., digital video interface (DVI)), and the like. Hence, the computing
device 602 may include volatile and/or nonvolatile memory.
[0035] Thus, there is described herein an architecture and associated methods
to implement transaction integrity in electronic devices. In some embodiments the
architecture uses hardware capabilities embedded in an electronic device platform to
provide assurances to transaction-authorizing parties that a transaction is being made
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by an authorized individual. In the embodiments described herein authentication and
persistence are based processing that occurs within a trusted environment, separate
from the host operating system. The execution environment may be implemented in
a trusted execution engine, which obtains and verifies user identity, then provides
proof of identity verification, and may provide other elements required to satisfy
transaction requirements. The result is a platform-issued token that represents
fulfillment of these required elements to relying parties. In some embodiments the
trusted execution engine may be implemented in a remote device, e.g., a dongle,
[0036] The terms "logic instructions" as referred to herein relates to
expressions which may be understood by one or more machines for performing one
or more logical operations. For example, logic instructions may comprise
instructions which are interpretable by a processor compiler for executing one or
more operations on one or more data objects. However, this is merely an example of
machine-readable instructions and embodiments are not limited in this respect.
[0037] The terms "computer readable medium" as referred to herein relates to
media capable of maintaining expressions which are perceivable by one or more
machines. For example, a computer readable medium may comprise one or more
storage devices for storing computer readable instructions or data. Such storage
devices may comprise storage media such as, for example, optical, magnetic or
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semiconductor storage media. However, this is merely an example of a computer
readable medium and embodiments are not limited in this respect.
[0038] The term "logic" as referred to herein relates to structure for
performing one or more logical operations. For example, logic may comprise
circuitry which provides one or more output signals based upon one or more input
signals. Such circuitry may comprise a finite state machine which receives a digital
input and provides a digital output, or circuitry which provides one or more analog
output signals in response to one or more analog input signals. Such circuitry may be
provided in an application specific integrated circuit (ASIC) or field programmable
gate array (FPGA). Also, logic may comprise machine-readable instructions stored
in a memory in combination with processing circuitry to execute such machinereadable
instructions. However, these are merely examples of structures which may
provide logic and embodiments are not limited in this respect.
[0039] Some of the methods described herein may be embodied as logic
instructions on a computer-readable medium. When executed on a processor, the
logic instructions cause a processor to be programmed as a special-purpose machine
that implements the described methods. The processor, when configured by the
logic instructions to execute the methods described herein, constitutes structure for
performing the described methods. Alternatively, the methods described herein may
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be reduced to logic on, e.g., a field programmable gate array (FPGA), an application
specific integrated circuit (ASIC) or the like.
[0040] In the description and claims, the terms coupled and connected, along
with their derivatives, may be used. In particular embodiments, connected may be
used to indicate that two or more elements are in direct physical or electrical contact
with each other. Coupled may mean that two or more elements are in direct physical
or electrical contact. However, coupled may also mean that two or more elements
may not be in direct contact with each other, but yet may still cooperate or interact
with each other.
[0041] Reference in the specification to "one embodiment" or "some
embodiments" means that a particular feature, structure, or characteristic described
in connection with the embodiment is included in at least an implementation. The
appearances of the phrase "in one embodiment" in various places in the specification
may or may not be all referring to the same embodiment.
[0042] Although embodiments have been described in language specific to
structural features and/or methodological acts, it is to be understood that claimed
subject matter may not be limited to the specific features or acts described. Rather,
the specific features and acts are disclosed as sample forms of implementing the
claimed subject matter.

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CLAIMS
What is claimed is:
1. A system, comprising:
an integrated circuit;
a plurality of voltage regulators; and
a data bus coupled to the integrated circuit and the plurality of voltage
regulators;
wherein the integrated circuit comprises logic to embed a timing signal on
the data bus.
2. The system of claim 1, wherein the logic to embed a timing signal on the
data bus comprises logic to:
drive the data bus from a logic low to a logic high for a predetermined
time; and
drive the data bus back to a logic low for a predetermined time.
3. The system of claim 2, wherein the logic to embed a timing signal is to
drive the data bus to a logic high for a period of time corresponding to one-fourth
a clock cycle, then to a logic low for a period of time corresponding to threefourths
a clock cycle.
4. The system of claim 1, wherein the integrated circuit further comprises
logic to initiate a timing negotiation process with the plurality of voltage
regulators, wherein the timing negotiation process is to determine a
communication speed associated with one or more of the plurality of voltage
regulators.
5. The system of claim 4, wherein the timing negotiation process is to select
a communication speed which permits communication with a voltage regulator
that has the slowest data rate.
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6. The system of claim 1, comprising logic to initiate a data rate negotiation
process with at least one of the voltage regulators.
7. An apparatus, comprising:
an integrated circuit comprising logic to embed a timing signal on a data
bus that is to couple the integrated circuit to a plurality of voltage regulators.
8. The apparatus of claim 7, wherein the logic to embed a timing signal on
the data bus comprises logic to:
drive the data bus from a logic low to a logic high for a predetermined
time; and
drive the data bus back to a logic low for a predetermined time.
9. The apparatus of claim 8, wherein the logic to embed a timing signal is to
drive the data bus to a logic high for a period of time corresponding to one-fourth
a clock cycle, then to a logic low for a period of time corresponding to threefourths
a clock cycle.
10. The apparatus of claim 7, wherein the integrated circuit further comprises
logic to initiate a timing negotiation process with the plurality of voltage
regulators, wherein the timing negotiation process is to determine a
communication speed associated with one or more of the plurality of voltage
regulators.
11. The apparatus of claim 10, wherein the timing negotiation process is to
select a communication speed which permits communication with a voltage
regulator that has the slowest data rate.
12. The apparatus of claim 7, comprising logic to initiate a data rate
negotiation process with at least one of the voltage regulators.
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13. The apparatus of claim 1, wherein the data bus is to facilitate serial
communication between the integrated circuit and at least one of the plurality of
voltage regulators
14. An electronic device, comprising:
a display;
an integrated circuit;
a plurality of voltage regulators; and
a data bus coupled to the integrated circuit and the plurality of voltage
regulators;
wherein the integrated circuit comprises logic to embed a timing signal on
the data bus.
15. The electronic device of claim 14, wherein the logic to embed a timing
signal on the data bus comprises logic to:
drive the data bus from a logic low to a logic high for a predetermined
time; and
drive the data bus back to a logic low for a predetermined time.
16. The electronic device of claim 15, wherein the logic to embed a timing
signal is to drive the data bus to a logic high for a period of time corresponding to
one-fourth a clock cycle, then to a logic low for a period of time corresponding to
three-fourths a clock cycle.
17. The electronic device of claim 14, wherein the integrated circuit further
comprises logic to initiate a timing negotiation process with the plurality of
voltage regulators, wherein the timing negotiation process is to determine a
communication speed associated with one or more of the plurality of voltage
regulators.
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18. The electronic device of claim 17, wherein the timing negotiation process
is to select a communication speed which permits communication with a voltage
regulator that has the slowest data rate.
19. The electronic device of claim 14, comprising logic to initiate a data rate
negotiation process with at least one of the voltage regulators.
20. The electronic device of claim 14, wherein the data bus is to facilitate
serial communication between the integrated circuit and at least one of the
plurality of voltage regulators
Dated this the 13* day of January 2012.