BACKGROUND
Plrysidlogi'cal signal processing rSe^uirles l&fge' time cdnstattts to dbtsCifx working
designs at the very low frequencies required for biomedical signals like ECG,
EEG and/or EMG (typically in the.sub- 300 Hz range). As passive filters require
bulky capacitors and resistors to achieve such time constants, they are rarely used.
Transconductance-C (gm~C) structures are instead used to obtain the desired characteristics.
This technique becomes particularly effective when the transconductance
employed can be made to be ultra-small, thereby leading to the requirement of low
valued capacitors in the design [1-4].
As discussed above, the design of an ultra-low transconductance (gmJ Operational
Transconductance Amplifier (OTA) has therefore received significant research
attention over the recent past. Previous works have put forward various \ow-gin techniques
like current division, current cancellation, series parallel current division, etc.
to achieve transconductance gm values ranging from few nA/V to tens of pA/V [5]'.
OTAs using floating-gate MOS with input-voltage attenuation to achieve low gm
values has also been discussed. Additionally, an OTA based on current division
technique has been explored [6]. This technique has achieved gm of 0.1 ^A/V. Moreover;
by ctutienC cancellation technique, the tY^scoridfictailc'e obtained is' ardtfrid 10'
nA/V [6]. Thus, gm of few nA/V has been achieved by these techniques. In addition
to this, a series-parallel current division technique has been exploited [1]. It is based
on series-parallel current-mirror structure and reduces the gm to the range of tens
of pA/V. The minimum achieved gm by this technique was 15 pA/V [1).
§) All the above techniques use the hugely popular CMOS technology for the circuit
implementation. However, as has been demonstrated by the continued device scaling
in CMOS, if the transistor size is scaled to below 10 nm, then short channel effects
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ization of the MOS transistor [7-9]. The Carbon Nanotube Field Effect Transistor
(CNFET) is another technology which can be a possible alternative to mitigate the
limitations of CMOS technology scaling. The CNFET is similar to MOS transistor,
except the fact that the channel region contains carbon nandtubes (CNTs) to
£-©#-• £•&!• *carry the cttfrSfrt between the soured and the dfai'n. The Cafbofi nanot'ub'e-FET
are MOSFET-like transistors, with multiple CNTs making up the channel, and exhibit
various advantages over conventional MOSFETs, such as better control over
the channel, enhanced current density, higher carrier velocity, minimized leakage
currents, and reduction in carrier tuMeliiig and short-channel' effects [9^11].
The operational transconductance amplifier (OTA) has two input voltages and
generates an output current that is directly proportional to the difference between
the two input voltages. The expression for output current of transconductance
amplifier is given in (I), where gm is the trahscdnduct'ance gain of the amplifier [12].
lout = 9m (V! - V2) (1)
The proposed ultra^low transconductance amplifier is shown in Fig. 1. For the
sake of clarity, the circuit is divided in four parts labeled as Parts 1 through 4 in
Fig. 1. The functional stages of Carbon Nanotube Field Effect Transistor based
Ultra-low TVansconductance Amplifier, as divided into four sub-parts, can be described
a&:
1. The transistors M5 and Af6, work as a current mirror which is set to drive
two differential amplifiers consisting of transistors Mi h Af2 and M3 &, M4.
Further, since transistors M9 and Afi0 are biased with equal' gate voltages'
(and since their source voltages are also equal), they would have equal drain
currents. For matched M9 and M10, this would result in Vx = Vy\ — Vy2.
Additionally, transistors My andMn provide the necessary feedback action to
nlalce the voltage Vx independent of cttfriefit df&wn' from the te'rininal X.
2. The current in terminal X is conveyed to the Z\ terminal with the help of
transistors My, M8, M\\ and A/12.
3'. By using extra current mirror stage (A/13 - A/18), the current is conveyed in
an inverted manner to the Z% terminal.
4. The transistors M19 - A/26 form the transconductor structure to generate the
oiitput current which is proportional' to^ the differential' inputs.
Routine analysis of blocks 1, 2, and 3 gives the relations as given by (2) -(4).
Vx = VYi - VY2 (27
Izi = I.x) Iz2 = —Ix (3)
hx = IY% = 0 (4)
Further for the circuit of Fig. 1, the current Ix can be written as (5) and the
voltages Vzi.and Vz2 are given by (6) and (7) respectively with the following
assumptions': Ri = R2 and R$/Ri = R^/Ri — A.
V x { V y i _ V Y 2 )
lx = ~n~ = » ^ >
{ V y i - V Y 2 )
Vzi = -^ W
Va__w^w (7)
Now. considering the output stage, the expression for output current has been
written (8). Combining (6, 7) with (8), the output current may be given by
(9) where A is the voltage gain provided by the blocks 1 through 3 (in Fig. 1).
Comparing (9) with the standard OTA characteristics (1), it can be observed
that the obtained transconductance for the complete circuit of Fig. 1 is given
by (10) which is equal to the transconductance of the OTA block (4th sub-part
in Fig. I)' reduced by a factor of A/2. Choosing a higher value of the voltage
gain A (sub-parts 1 through 3) would therefore lead to a lower value of the
overall transconductance.
lout = 9mOTMA%h_ block) SVzi - VZ2) (8)
(Vyi - VY2)
A/2
7 - n K Y1 ~ Y2} (Q*OUt 9moTA(4th block) A /r» W
Table 1: Comparison of CNFET- and CMOS-based Tfaiisconductdf
Parameters
Power Supply
Power Dissipation
No. of Transistors
gin{rninimum)
Linear Range
CNFET
0.9 V
756.7 /*W
26
• 2,59 pA/V
766.8 mV
CMOS
0.9 V
7574.3 /JW
26
40pA/V
338.9 mV
Table 2: Comparison of Low-gm Techniques
Parameters
• grtftyninimum)
Lineai' Range
Power Supply
[6]
• 33 pA/V
300 mV
2V
[13]
30 pA/V
500 mV
2V
[14]
15 pA/V
2V
2V
This Work
2,59 pA/V
766.8 mV
±0.9 V
— ^tQTA(4tfe block)
jf^-ovGi-all A J1*}
The performance of the proposed CNFET-based transconductance amplifier
was verified by HSPICE simulations. Results of the computer simulations
sue jDiresiefited in Table 1. For the' sake of detnofistfating the superiority of
the proposed CNFET-based design over their CMOS counterparts, a CMOS
version of the circuit of Fig. 1 was also designed and simulated. Results of the
HSPICE simulations for the CMOS circuit are also included in Table 1, and are
observed to be inferior to the CNFET-based feisults on all the' three relevant
parameters tested: power dissipation, transconductance (gm) and linear range.
Additionally, the performance of proposed transconductor was compared with
similar existing works. Table 2 presents the comparison among various lowgm
techniques. It can be readily seen that the proposed circuit yields the
minimum value of transconductance with the lowest supply voltage amongst
all the circuits compared.

We claim:
1. A Carbon Nanotube Field Effect Tiansistor based Ultra-low Transconductance
Amplifier has two differential transistor pairs, with voltage inputs Vy\ and Vy^
producing a difference voltage at a low-impedance node (X) thereby generating
a current (Ix) in the resistor R3, which is then copied into the high-impedance
terminal (Z\) resulting in a voltage Vz\ being developed across the resistor Ru
and also copied with reverse polarity into the second high-impedance terminal
(Z2) resulting in a voltage Vz2 being developed across the resistor R%, which
along with Vz\ serve as the input voltages for the final transconductance amplifier
stage comprising of transistors M19 through M2Q-) thereby generating an
output current (lout) which is proportional to the difference of input voltages
Vyx and Vy2.
2. A Carbon Nanotube Field Effect Transistor based Ultra-low Transconductance
Amplifier as claimed in Claim-1 wherein the voltage of the low-impedance
output node (X) is the difference of the voltages at the two high-impedance
input nodes (Yj and Y2).
3. A Carbon Nanotube Field Effect Transistor based Ultra-low Transconductance
Amplifier as claimed in Claim-1 wherein the current flowing in R$ is conveyed
to the Z\ terminal & flows in resistors R\ and conveyed with reverse polarity
to Z2 terminal & flows in resistor R2.
4. A Carbon Nanotube Field Effect Transistor based Ultra-low Transconductance
Amplifier as claimed in Claim-1 wherein the voltages V%\ and Vz% are developed
at nodes Z\ and Z2, which are then fed as inputs to the transconductor
stage of the circuit.
5. A Carbon Nanotube Field Effect Transistor based Ultra-low Transconductance
Amplifier as claimed in Claim-1 wherein the output current (lout) is directly
proportional to the voltage difference of the two nodes Y\ and Y2.
.6. A Carbon Nanotube Field Effect Transistor based Ultra-low Transconductance
Amplifier as claimed in Claim-1 wherein the overall transconductance gm of
the amplifier can be scaled by the resistance ratio (A) depending upon the
values of Ru R2} and R3.
7. A Carbon Naiiotube Field Effect Transistor based Ultra-row Tfaiisconductance
Amplifier as claimed in Claim-1 wherein the circuit achieves a minimum
transconductance of 2.59 pA/V.