Claims:Claims:
I/We Claim:
1. An ultra-wideband quad digital receiver for receiving and measuring pulse parameters of radio detection and ranging signals for high speed transferring and monitoring of processed signals, wherein the hardware of the device comprises of:
at least two modules for receiving, sampling and processing the high frequency inputs of various ranges, wherein the modules include:
an Intermediate-Frequency (IF) module;
a clock synthesizer module; and
a quad digital receiver main board module;
the IF and clock synthesizer modules further categorized into two independent sections for receiving at least four IF input signals, wherein the sections consists of:
an IF section designed as a separate board to further integrate with the said quad digital receiver main board module, wherein the IF section accommodates a plurality of components for processing the received IF input signals;
the quad digital receiver main board module for acquiring high speed samples for processing of acquired digital data, wherein the module includes:
at least four high speed dual channel Analog to Digital Convertors (ADC’s) in the form of two sets;
at least three Field Programmable Gate Array (FPGA’s) interconnected with each other for receiving the sampled data from the said ADC’s;
VPX connectors for transferring and monitoring the processed data outputted;
at least one 51 pin ‘D’ connector for transferring and monitoring the processed data outputted;
a power supply system to power all the components of the said modules of the ultra-wideband digital receiver board; and
a means for cooling the quad digital receiver board for reducing the heat generated to improve the performance.

2. The IF section according to claim 1, characterized to comprise a plurality of components in all four IF input channels for processing of the input signals, wherein the components include:
a plurality of SMA connectors;
a Low Noise Amplifier (LNA);
at least two filters include but not limited to:
a low pass filter;
a band pass filter;
a 2-way power divider; and
a programmable attenuator at all input channels.

3. The IF section according to claim 2, characterized for receiving inputs signals of different frequency ranges and are allowed to pass through various components for further processing and sampling, wherein include:
a means for allowing the SMA connectors as IF input interfaces for the front end board;
a means for amplifying the input signals through the LNA by offering an extremely high dynamic range over a broad frequency range and with low noise figure;
a means for allowing the IF input signals to pass through the low pass and band pass filters to eliminate spurious signals to meet the input power level requirements of ADC;
a means for dividing or splitting a single IF input into two IF output signals to fed the corresponding ADC; and
a means for attenuating the IF input signals with frequencies which are out of range.

4. The clock synthesizer section according to claim 1, characterized to generate required clock frequency for ADC sampling using a phase locked loop method, wherein the clock synthesizer comprises of plurality of components include:
an ultra-low noise frequency synthesizer for generating the sampling clock;
a gain amplifier for amplifying the sampled clock signal; and
a 4-way power divider for dividing the output of the amplifier to clock the four ADC’s.

5. The analog to digital convertors according to claim 1, characterized to receive the IF input signals for digitizing the received analog inputs into digital inputs for transferring the high speed IF digital converted signals to FPGA’s.

6. The digital receiver device according to claim 1, characterized to support remote programming and up gradation of all FPGA’s configured with update bit stream provided with terminals on the board include:
a trimode Ethernet MAC; and
RIOs

7. The three FPGA’s according to claims 1, wherein at least two FPGA’s receive the sampled digitized data in real time from ADC’s for processing and transferring the processed data to the third FPGA, wherein the processed data is tested for dynamic range, gain matching and phase matching in all the IF input channels.

8. The three FPGA’s according to claim 1, characterized to be connected with plurality of other integrated circuits include but not limited to:
at least three crystal oscillators for providing system clock to each FPGA;
a memory subsystem comprising a PROM and an EEPROM for each FPGA;
an interface for connecting all the FPGA’s for communicating and data transferring with each other and in a daisy chain mode such as JTAG interface for configuration; and
a high speed rocket IO Multi Giga Bit Transceivers (MGT’s) assisting in communicating between all the FPGA’s to maintain serial connectivity.

9. The MGT according to claim 7, characterized for receiving a plurality of clock references for various interfaces include:
an inter FPGA RIO interfaces;
an RIOs routed to external connectors; and
an Ethernet connected to the third FPGA

10. The third FPGA of all the FPGA’s according to claim 7, characterized to additionally comprise a plurality of other integrated circuits include but not limited to:
an additional memory subsystem such as a Parallel flash PROM of 1GbB and DDR2 SDRAM of 2Gb B is connected to the third FPGA for storing the data;
an RS232 communication is used for transferring data between FPGA’s by sending the read or write commands and accordingly it gives the output to other modules; and
a temperature sensor controller for sensing the temperature of the board comprises plurality of registers for resetting to their default values after power ON include:
a serial bus interface register;
a address register;
a temperature register; and
a data register.

11. The VPX connectors according to claim 1, characterized to connect to the all the FPGA’s through RIO lines and the Gigabit Ethernet controller for outputting the processed data.

12. The digital receiver device according to claim 1, characterized to comprise level translators for asynchronous communication for transferring data between third FPGA and the VPX connector and also between the third FPGA and a 51 pin ‘D’ connector.

13. The digital receiver device according to claim 1, characterized to comprise a VPX conduction cooled chassis capable of holding at least two quad digital receivers, a power supply board and a controller board provided with features include:
a thermal layer for conduction cooling;
a metal plate for heat dissipation of components of the board;
a guide rail to ensure the correct alignment of the board; and
a means for terminating the side panel of the chassis for remote programmability.

14. The power supply system according to claim 1, characterized to fed the main supply from the VPX connector of about +12 V supply and is down converted to required voltage levels using switching and linear voltage regulators for supplying power to:
all the four ADC’s from linear regulator;
all the three FPGA’s through power rails and other modules; and
other components through quad digital receiver board digital interface.

15. A process of operating an ultra-wideband quad digital receiver device with an IF and a clock synthesizer module and a quad digital receiver main board module for receiving and measuring the pulse parameters of radio detection and ranging signals for high speed transferring and monitoring of processed signals, wherein the process comprises steps of:
receiving at least four IF input signals at IF module of different frequency ranges and are allowed to pass through various components for further processing;
amplifying the input signals through a plurality of Low Noise Amplifiers (LNA) by offering an extremely high dynamic range over a broad frequency range and with low noise figure;
passing the IF input signals through at least one of the two filters include a low pass filter and a band pass filter to eliminate spurious signals to meet the input power level requirements of ADC’s;
dividing or splitting a single IF input signal into two IF output signals to fed to corresponding ADC;
attenuating the IF input signals with frequencies which are out of range;
generating a clock frequency for ADC sampling using a phase locked loop method;
digitizing the received analog inputs into digital inputs for transferring the high speed IF digital converted signals to three FPGAs;
supporting remote programming and up gradation of all FPGA’s configured with updated bit stream provided with terminals on the board; and
outputting the processed data to a 51 pin micro ‘D’ connector and VPX connectors through RIO lines and a Gigabit Ethernet controller.

16. The process according to claim 15, wherein comprises of translators for asynchronous communication for transferring data between third FPGA the VPX connector and also between the third FPGA and a 51 pin micro ‘D’ connector.
, Description:Technical Field of the Invention

[0001] The present invention relates to an ultra-wideband quad digital receiver for receiving and measuring pulse parameters of radio detection and ranging systems in real time. More particularly, it relates to receiving and measuring pulse parameters for high speed transferring and monitoring of processed signals.

Background of the Invention

[0002] Radio detection and ranging devices are used for various purposes. The key for successful development of radio detection and ranging systems are for harnessing the basic technologies involved in the modern radio detection and ranging system designs. With the advent of microelectronics, Radio Frequency (RF) management and unprecedented growth in processing power and computation transformed radio detection and ranging systems into complex, advanced and intelligent sensors. The radio detection and ranging systems automatically detects and tracks heterogeneous air targets from a very low altitude (tree top level) to a medium altitude.

[0003] Systems are designed to measure all the basic parameters of the radio detection and ranging system like frequency, pulse width (PW), pulse amplitude (PA), time-of-arrival (TOA) and direction of arrival (DOA) of the emitter along with intra pulse modulation present in radio detection and ranging system signal. In a digital receiver, an analog-to-digital convertor (ADC)operates at low sampling rate and an Intermediate-Frequency (IF) amplifier commonly to improve image rejection, lower the desired selectivity and tends to lower frequency range.

[0004] In Quad Digital Receiver (QDR), field-programmable gate array (FPGA) technology plays a major role to satisfy almost any demand for high-speed data processing that is needed in digital signal processing (DSP) applications and fast data transfers. FPGA resources are used in DSP applications to perform down conversion, filtering, and data formatting. New trends in system architecture favor serial data rather than parallel data transfer by using FPGA’s internal resources, high-speed serial input/outputs (IO), and hard core processors.

[0005] Therefore, there is a need to develop a QDR for high speed transferring and monitoring of processed signals employing an IF section, a plurality of FPGA’s, VPX connectors etc. for measuring the pulse parameters of radio detection and ranging system in real time.

Brief Summary of the Invention

[0006] The present invention recognizes the limitations of the prior art and the need for systems and process that are able to provide assistance to users in a manner that overcomes these limitations.

[0007] A principle object of the present invention is to design a Quad Digital Receiver (QDR)capable of measuring and transferring pulse parameters of radio detection and ranging systems in real time.

[0008] Another object of the present invention is to build a Quad Digital Receiver (QDR) employing an IF section, a plurality of FPGA’s, VPX connectors along with high speed, low power, high performance 10 bit ADC’s etc.

[0009] Yet another object of the present invention is to manufacture the Quad Digital Receiver (QDR) hardware with plurality of modules include an IF section, a clock synthesizer module and a Quad Digital Receiver (QDR) main board module.

[0010] According to first aspect of the present invention, an ultra-wideband quad digital receiver for receiving and measuring pulse parameters of radio detection and ranging signals for high speed transferring and monitoring of processed signals is disclosed. The hardware of the device comprises of at least two modules for receiving, sampling and processing the high frequency inputs of various ranges and the two modules are an IF module, a clock synthesizer module and a quad digital receiver main board module.

[0011] In accordance with a first aspect of the present invention, the IF and clock synthesizer modules of the receiver is further are categorized into two independent sections for receiving at least four IF input signals include an IF section designed as a separate board to further integrate with the quad digital receiver main board module to accommodate a plurality of components for processing the received IF input signals.

[0012] In accordance with a first aspect of the present invention, further the quad digital receiver main board module for acquiring high speed samples for processing of acquired digital data of the receiver include at least four high speed dual channel Analog to Digital Convertors (ADC’s) in the form of two sets, at least three Field Programmable Gate Array (FPGA’s) interconnected with each other for receiving the sampled data from the said ADC’s, VPX connectors for transferring and monitoring the processed data outputted and at least one 51 pin ‘D’ connector for transferring and monitoring the processed data outputted.

[0013] In accordance with a first aspect of the present invention, wherein the device further comprises a power supply system to power all the components of the modules of the ultra-wideband digital receiver board and a means for cooling the quad digital receiver board for reducing the heat generated to improve performance.

[0014] In accordance with a first aspect of the present invention, the IF section of the receiver is further consists of a plurality of components in all the four IF input channels for processing of input signals. The components include a plurality of MCX connectors, a Low Noise Amplifier (LNA), at least two filters a low pass filter & a band pass filter, a 2-way power divider and a programmable attenuator at all input channels.

[0015] In accordance with a first aspect of the present invention, wherein the IF section of the receiver for receiving inputs signals of different frequency ranges and are allowed to pass through various components for further processing and sampling includes a means for allowing the SMA connectors as IF input interfaces for the front end board and a means for amplifying the input signals through the LNA by offering an extremely high dynamic range over a broad frequency range and with low noise figure.

[0016] In accordance with a first aspect of the present invention, further the IF section further includes a means for allowing the IF input signals to pass through the low pass and band pass filters to eliminate spurious signals to meet the input power level requirements of ADC, a means for dividing or splitting a single IF input into two IF output signals to fed all the four ADC’s anda means for attenuating the IF input signals with frequencies which are out of range.

[0017] In accordance with a first aspect of the present invention, wherein the clock synthesizer module generates the required clock frequency for ADC sampling using a phase locked loop method consisting of a plurality of components including an ultra-low noise frequency synthesizer for generating the sampling clock, a gain amplifier for amplifying the sampled clock signal and a 4-way power divider for dividing the output of the amplifier to clock the four ADC’s.

[0018] In accordance with a first aspect of the present invention, further the analog to digital convertors receives the IF input signals for digitizing the received analog inputs into digital inputs for transferring the high speed IF digital converted signals to FPGA’s.

[0019] In accordance with a first aspect of the present invention, wherein the digital receiver device supports the remote programming and up gradation of all FPGA’s configured with update bit stream provided with terminals on the board that includes a trimode Ethernet MAC and RIOs.

[0020] In accordance with a first aspect of the present invention, further the Quad Digital Receiver with at least two FPGA’s receive the sampled digitized data in real time from ADC’s for processing and transferring the processed data to the third FPGA, wherein the processed data is tested for dynamic range, gain matching and phase matching in all the IF input channels.

[0021] In accordance with a first aspect of the present invention, the three FPGA’s of the receiver connects with a plurality of other integrated circuits that includes at least three crystal oscillators for providing system clock to each FPGA, a memory subsystem comprising a PROM and an EEPROM for each FPGA, an interface for connecting all the FPGA’s for communicating and data transferring with each other and in a daisy chain mode such as JTAG interface for configuration and a high speed rocket IO Multi Giga Bit Transceivers (MGT’s) assisting in communicating between all the FPGA’s to maintain serial connectivity.

[0022] In accordance with a first aspect of the present invention, the MGT of the receiver receives a plurality of clock references for various interfaces that includes an inter FPGA RIO interfaces, and RIOs routed to external connectors and an Ethernet connected to the third FPGA.

[0023] In accordance with a first aspect of the present invention, further the third FPGA of the receiver is additionally comprised of a plurality of other integrated circuits that include an additional memory subsystem such as a flash PROM of 1Gb and DDR2 SDRAM of 2Gb is connected to the third FPGA for storing the data and an RS232 communication is used for transferring data between FPGA’s by sending the read or write commands and accordingly it gives the output to other modules.

[0024] In accordance with a first aspect of the present invention, wherein the third FPGA also includes a temperature sensor controller for sensing the temperature of the board comprises plurality of registers for resetting to their default values after power ON includes a serial bus interface register, an address register, a temperature register and a data register.

[0025] In accordance with a first aspect of the present invention, the receiver further comprises a VPX connector is connected to the all the FPGA’s through RIO lines and the Gigabit Ethernet controller for outputting the processed data.

[0026] In accordance with a first aspect of the present invention, wherein the receiver device comprises a level translator for asynchronous communication for transferring data between third FPGA and the VPX connector and also between the third FPGA and a 51 pin ‘D’ connector.

[0027] In accordance with a first aspect of the present invention, the digital receiver device is characterized to comprise a VPX conduction cooled chassis capable of holding at least two quad digital receivers, a power supply board and a controller board provided with features such as a thermal layer for conduction cooling, a metal plate for heat dissipation of components of the board, a guide rail to ensure the correct alignment of the board and a means for terminating the side panel of the chassis for remote programmability.

[0028] In accordance with a first aspect of the present invention, further the power supply system of the receiver device is characterized to fed the main supply from the VPX connector of about +12 V supply and is down converted to the required voltage levels using switching and voltage level regulators to supply power to all the four ADC’s from linear regulator, all the three FPGA’s through power rails and other modules and other components through quad digital receiver board digital interface.

[0029] According to second aspect of the present invention, a process of operating an ultra-wideband quad digital receiver device with an IF and a clock synthesizer module and a quad digital receiver main board module for receiving and measuring the pulse parameters of radio detection and ranging signals for high speed transferring and monitoring of processed signals. The process comprises steps of receiving at least four IF input signals at IF & clock synthesizer module of different frequency ranges and are allowed to pass through various components for further processing and amplifying the input signals through a plurality of Low Noise Amplifiers (LNA) by offering an extremely high dynamic range over a broad frequency range and with low noise figure.

[0030] In accordance with a second aspect of the present invention, further step of the receiver device passing the IF input signals through at least one of the two filters include a low pass filter and a band pass filter to eliminate spurious signals to meet the input power level requirements of ADC’s, dividing or splitting a single IF input signal into two IF output signals to fed to all the four ADC’s, attenuating the IF input signals with frequencies which are out of range and generating a clock frequency for ADC sampling using a phase locked loop method.

[0031] In accordance with a second aspect of the present invention, wherein the device also comprises steps of digitizing the received analog inputs into digital inputs for transferring the high speed IF digital converted signals to at least three FPGA’s and supporting the remote programming and up gradation of all FPGA’s configured with updated bit stream provided with terminals on the board.

[0032] In accordance with a second aspect of the present invention, further step of the device comprises of receiving at least the sampled digitized data in real time by at least to FPGA’s and transferring the processed data to third FPGA and outputting the processed data to a VPX connector and a 51 pin ‘D’ connector through RIO lines and a Gigabit Ethernet controller.

[0033] In accordance with a second aspect of the present invention, further the process of the device comprises a translator for asynchronous communication for transferring data between third FPGA the VPX convertor and also between the third FPGA and a 51 pin ‘D’ connector.

Brief Description of the Drawings

[0034] Other objects and advantages of the present invention will become apparent to those skilled in the art upon reading the following detailed description of the preferred embodiments, in conjunction with the accompanying drawings, wherein like reference numerals have been used to designate like elements, and wherein

FIG. 1 illustrates a functional block diagram depicting the modules and other integrated circuits of a quad digital receiver unit according to the present invention.

FIG. 2 illustrates a block diagram depicting the IF section & clock synthesizer modules of the receiver unit according to the present invention.

FIG.3 illustrates the block diagram depicting the internal components of the IF section for processing input signal according to the present invention.

FIG.4 illustrates a block diagram of a clock synthesizer section depicting the generation of clock frequency through different components according to the present invention.

FIG. 5 illustrates a block diagram depicting the inter FPGA communication interface according to the present invention.

FIG. 6illustratesa block diagram depicting the power supply sub system of the quad digital receiver main board according to the present invention.

FIG. 7 illustrates a block diagram depicting the temperature sensor of the receiver unit according to the present invention.

FIG.8 illustrates a block diagram depicting the remote programming setup of the receiver unit according to the present invention.

Detailed Description of the Invention

[0035] The present invention is directed towards an ultra-wideband quad digital receiver for receiving and measuring pulse parameters of radio detection and ranging signals for high speed transferring and monitoring of processed signals. Referring to the drawings, wherein like reference numerals designate identical or corresponding systems, preferred embodiments of the present invention are described.

[0036] The use of “including”, “comprising” or “having” and variations thereof herein is meant to encompass the items listed thereafter and equivalents thereof as well as additional items. The terms “a” and “an” herein do not denote a limitation of quantity, but rather denote the presence of at least one of the referenced item. Further, the use of terms “first”, “second”, and “third”, and the like, herein do not denote any order, quantity, or importance, but rather are used to distinguish one element from another.

[0037] In accordance with an exemplary embodiment of the present invention, an ultra-wideband quad digital receiver for receiving and measuring pulse parameters of radio detection and ranging signals for high speed transferring and monitoring of processed signals. The hardware of the device comprises of at least two modules for receiving, sampling and processing the high frequency inputs of various ranges and the two modules are an IF module, a clock synthesizer module anda quad digital receiver main board module.

[0038] In accordance with an exemplary embodiment of the present invention, the IF and clock synthesizer modules of the receiver is further are categorized into two independent sections for receiving at least four IF input signals include an IF section designed as a separate board to further integrate with the quad digital receiver main board module to accommodate a plurality of components for processing the received IF input signals.

[0039] In accordance with an exemplary embodiment of the present invention, further the quad digital receiver main board module for acquiring high speed samples for processing of acquired digital data of the receiver include at least four high speed dual channel Analog to Digital Convertors (ADC’s) in the form of two sets, at least three Field Programmable Gate Array (FPGA’s) interconnected with each other for receiving the sampled data from the said ADC’s, VPX connectors for transferring and monitoring the processed data outputted and at least one 51 pin ‘D’ connector for transferring and monitoring the processed data outputted.

[0040] In accordance with an exemplary embodiment of the present invention, wherein the device further comprises a power supply system to power all the components of the modules of the ultra-wideband digital receiver board and a means for cooling the quad digital receiver board for reducing the heat generated to improve performance.

[0041] In accordance with an exemplary embodiment of the present invention, the IF section of the receiver is further consists of a plurality of components in all the four IF input channels for processing of input signals. The components include a plurality of the SMA connectors, a Low Noise Amplifier (LNA), at least two filters a low pass filter & a band pass filter, a 2-way power divider and a programmable attenuator at all input channels.

[0042] In accordance with an exemplary embodiment of the present invention, wherein the IF section of the receiver for receiving inputs signals of different frequency ranges and are allowed to pass through various components for further processing and sampling includes a means for allowing the SMA connectors as IF input interfaces for the front end board and a means for amplifying the input signals through the LNA by offering an extremely high dynamic range over a broad frequency range and with low noise figure.

[0043] In accordance with an exemplary embodiment of the present invention, further the IF section further includes a means for allowing the IF input signals to pass through the low pass and band pass filters to eliminate spurious signals to meet the input power level requirements of ADC, a means for dividing or splitting a single IF input into two IF output signals to fed corresponding ADC and a means for attenuating the IF input signals with frequencies which are out of range.

[0044] In accordance with an exemplary embodiment of the present invention, wherein the clock synthesizer module generates the required clock frequency for ADC sampling using a phase locked loop method consisting of a plurality of components including an ultra-low noise frequency synthesizer for generating the sampling clock, a gain amplifier for amplifying the sampled clock signal and a 4-way power divider for dividing the output of the amplifier to clock the four ADC’s.

[0045] In accordance with an exemplary embodiment of the present invention, further the analog to digital convertors receives the IF input signals for digitizing the received analog inputs into digital inputs for transferring the high speed IF digital converted signals to FPGA’s.

[0046] In accordance with an exemplary embodiment of the present invention, wherein the digital receiver device supports the remote programming and up gradation of all FPGA’s configured with update bit stream provided with terminals on the board that includes a trimode Ethernet MAC and RIOs.

[0047] In accordance with an exemplary embodiment of the present invention, further the Quad Digital Receiver with at least two FPGA’s receive the sampled digitized data in real time from ADC’s for processing and transferring the processed data to the third FPGA, wherein the processed data is tested for dynamic range, gain matching and phase matching in all the IF input channels.

[0048] In accordance with an exemplary embodiment of the present invention, the three FPGA’s of the receiver connects with a plurality of other integrated circuits that includes at least three crystal oscillators for providing system clock to each FPGA, a memory subsystem comprising a PROM and an EEPROM for each FPGA, an interface for connecting all the FPGA’s for communicating and data transferring with each other and in a daisy chain mode such as JTAG for configuration interfaceanda high speed rocket IO Multi Giga Bit Transceivers (MGT’s) assisting in communicating between all the FPGA’s to maintain serial connectivity.

[0049] In accordance with an exemplary embodiment of the present invention, the MGT of the receiver receives a plurality of clock references for various interfaces that includes an inter FPGA RIO interfaces, an RIOs routed to external connectors and an Ethernet connected to the third FPGA.

[0050] In accordance with an exemplary embodiment of the present invention, further the third FPGA of the receiver is additionally comprised of a plurality of other integrated circuits that include an additional memory subsystem such as a flash PROM of 1Gb and DDR2 SDRAM of 2Gb B is connected to the third FPGA for storing the data and an RS232 communication is used for transferring data between FPGA’s by sending the read or write commands and accordingly it gives the output to other modules.

[0051] In accordance with an exemplary embodiment of the present invention, wherein the third FPGA also includes a temperature sensor controller for sensing the temperature of the board comprises plurality of registers for resetting to their default values after power ON includes a serial bus interface register, an address register, a temperature register and a data register.

[0052] In accordance with an exemplary embodiment of the present invention, the receiver further comprises a VPX connector is connected to the all the FPGA’s through RIO lines and the Gigabit Ethernet controller for outputting the processed data.

[0053] In accordance with an exemplary embodiment of the present invention, wherein the receiver device comprises a level translator for asynchronous communication for transferring data between third FPGA and the VPX connector and also between the third FPGA and a 51 pin ‘D’ connector.

[0054] In accordance with an exemplary embodiment of the present invention, the digital receiver device is characterized to comprise a VPX conduction cooled chassis capable of holding at least two quad digital receivers, a power supply board and a controller board provided with features such as a thermal layer for conduction cooling, a metal plate for heat dissipation of components of the board, a guide rail to ensure the correct alignment of the board and a means for terminating the side panel of the chassis for remote programmability.

[0055] In accordance with an exemplary embodiment of the present invention, further the power supply system of the receiver device is characterized to fed the main supply from the VPX connector of about +12 V supply and is down converted to the required voltage levels using switching and linear voltage regulators to supply power to all the four ADC’s from linear regulator, all the three FPGA’s through power rails and other modules and other components through quad digital receiver board digital interface.

[0056] In accordance with an exemplary embodiment of the present invention, a process of operating an ultra-wideband quad digital receiver device with an IF and a clock synthesizer module and a quad digital receiver main board module for receiving and measuring the pulse parameters of radio detection and ranging signals for high speed transferring and monitoring of processed signals. The process comprises steps of receiving at least four IF input signals at IF & clock synthesizer module of different frequency ranges and are allowed to pass through various components for further processing and amplifying the input signals through a plurality of Low Noise Amplifiers (LNA) by offering an extremely high dynamic range over a broad frequency range and with low noise figure.

[0057] In accordance with an exemplary embodiment of the present invention, further step of the receiver device passing the IF input signals through at least two filters include a low pass filter and a band pass filter to eliminate spurious signals to meet the input power level requirements of ADC’s, dividing or splitting a single IF input signal into two IF output signals to fed to all the four ADC’s, attenuating the IF input signals with frequencies which are out of range and generating a clock frequency for ADC sampling using a phase locked loop method.

[0058] In accordance with an exemplary embodiment of the present invention, wherein the device also comprises steps of digitizing the received analog inputs into digital inputs for transferring the high speed IF digital converted signals to at least three FPGA’s and supporting the remote programming and up gradation of all FPGA’s configured with updated bit stream provided with terminals on the board.

[0059] In accordance with an exemplary embodiment of the present invention, further step of the device comprises of receiving at least the sampled digitized data in real time by at least to FPGA’s and transferring the processed data to third FPGA and outputting the processed data to a VPX connector and a 51 pin ‘D’ connector through RIO lines and a Gigabit Ethernet controller.

[0060] In accordance with an exemplary embodiment of the present invention, further the process of the device comprises a translator for asynchronous communication for transferring data between third FPGA the VPX connectors and also between the third FPGA and a 51 pin ‘D’ connector.

[0061] Referring to drawings, illustrates various embodiments of an ultra-wideband quad digital receiver for receiving and measuring pulse parameters of radio detection and ranging system in real time depicting a plurality of module and its internal components for processing the received IF input signal.

[0062] FIG. 1 illustrates the block diagram (100) depicting the modules and other integrated circuits of a quad digital receiver unit according to the present invention. The Quad digital receiver (100)has two modules an IF module(102) and a clock synthesizer module (106) and quad digital receiver main board module for receiving, sampling and processing the high frequency inputs of various ranges. The 4 IF input signals (102a)are in the frequency range of 750-1250MHz (IBW: 500MHz)/980-1020 MHz (IBW: 40MHz)/140-180 MHz (IBW: 40MHz) of the IF section module (102)as shown in FIG. 2 are in various bandwidths. These IF input signals (102a) are allowed to pass through a plurality of filters, amplifiers as shown in FIG. 2in order to eliminate any spurious signals with a chain gain of 12dB to meet the input power level requirements of ADC’s(104)which are provided at the output section of IF section.

[0063] The clock synthesizer module (106) also generates a required clock frequency for ADC sampling (104) using a phase locked loop method as shown in FIG. 4. The output signals (102b) and (106a) generated from IF section module (102) and clock synthesizer module (106) are fed to four ADC’s 104 for digitizing the received analog input signals (102b) & (106a) into digital inputs (104a) to FPGA’s for transferring the high speed IF digital converted signals (104a)to two FPGA’s (108). The quad digital receiver unit employs three FPGA’s (108) FPGA-1, FPGA-2 and FPGA-3 at the output section of four ADC’s (104).

[0064] The three FPGA’s (108) are connected with other integrated circuits such as crystal oscillator (114) which provides the 100MHz system clock for each FPGA (108) and an integrated circuit ICS849S625I (not shown) and a memory subsystem EEPROM (110 of 1MB and SPI PROMs (not shown) of two 512 Mb and a 256 Mbfor configuration. The output signals from the FPGA-1 and FPGA-2 are provided to the third FPGA-3 as input signals for further processing. The third FPGA-3 (108) is further connected to a plurality of other integrated circuits through a 64 LVTTL I/O lines (136)is routed to the VPX connector (124) for transferring the processed data to the external world. In addition to this a high speed Gigabit Ethernet (138) is routed to VPX connector (136) for receiving commands from the external world and for other communication. The FPGA1 & FPGA2 (108) are connected to VPX connector (124) through 8 LVDS TX and8 LVDS RX (132) and a socket (130) is connected to all IF Channels (108) which are routed to VPX (124)via RIOs lines (134) for high speed communication link with the external world.

[0065] The third FPGA (108) consists of a plurality of integrated circuits such as a temperature sensor controller (118), RS 232 channel (140), an additional memory sub-system, a level translator (120) and DC converters (122). The temperature sensor controller (118) senses the temperature of the board comprising a plurality of registers as shown in FIG. 7 for resetting to their default values after power ON. A level translator (120), DC converters (122), one RS 232 channel(140)are connected from FPGA-3(108) to 51 pin ‘D’ connector (126) for transferring data between FPGA’s (108) by sending the read or write commands and accordingly giving the output to other modules. The additional memory subsystem such as a flash PROM (112) of 1GbBand DDR2 (128) SDRAM of 2Gb are connected to the third FPGA (108) for storing the data and a JTAG interface (116) for connecting all the FPGA’s (108)for communicating and data transferring with each other. Finally the data from ADC’s is fed to the two FPGA’s (108) for further processing. Later, the processed data is fed to the third FPGA (108) and outputted to a VPX connector (124) and a 51 pin ‘D’ connector (126), through RIO lines (134) and a Gigabit Ethernet controller (138).

[0066] FIG. 2 illustrates a block diagram (200) depicting the IF section & clock synthesizer modules of the quad digital receiver unit according to the present invention. The receiver unit with an IF section depicting the IF section module (202) with 4 IF input signals in the frequency range 750-1250MHz (IBW: 500MHz)/980-1020 MHz (IBW: 40MHz)/140-180 MHz (IBW: 40MHz) and 8 output signals and a CLK synthesizer section module (206).

[0067] FIG. 3illustratesblock diagram (300) depicting the internal components of the IF section for processing input signal according to the present invention. The IF input signals at the IF section are processed through a plurality of components include MCX connectors, amplifiers, filters etc. The IF input signals are allowed to pass through SMA connectors as IF input interfaces for the front end board through a channel CH1 (302a) and is allowed to pass through various components for processing and sampling.

[0068] The input signals is amplified through two low noise amplifiers i.e. LNA1 (342a), LNA2 (342b) and through two PADs (344a), (344b) by offering an extremely high dynamic range over a broad frequency range and with low noise figure. An attenuator (346) is used for attenuating the IF input signals within the channel frequencies for gain matching. An absorptive switch (348a) and (348b) is placed after the attenuator (346) for allowing the IF input signals (302a) to pass through a low pass filter (352) and a band pass filter (354) to eliminate spurious signals to meet the input power level requirements of ADC’s as shown in FIG. 1. A power divider (356)arranged at the end of the IF section divides or splits a single IF input signal into two IF output signals (302b) and (302c) to fed an ADC (104). Similarly, each IF input signal is processed and power divided into two individual IF output signals to fed to each ADC (104).

[0069] FIG.4 illustrates a block diagram (400) depicting the clock synthesizer section according to the present invention. The clock synthesizer section is used for generating the required clock frequency for ADC sampling using phase locked method. The clock synthesizer (406) generates a 100 MHZ reference clocks to allow passing through an ultra-low noise amplifier (442) for generating the sampling clock. Then the sampling clock is passed through the low pass filter (452) for filtering with the PAD(444)and the filtered sampled clock finally passes through the 4-way power divider (456) for dividing the output of the sampled clock pulses in to four clock pulses (402a, 402b, 402c, 402d)for ADC sampling.

[0070] FIG. 5illustratesa block diagram (500) the clock synthesizer section depicting the generation of clock frequency through different components according to the present invention. All the three FPGA’s are interconnected for communication through an interface through a plurality of IO lines to facilitate the inter FPGA communication. The three FPGA’s (508) are interconnected with many IO lines such as clock pulses, 84 lines, 120 lines and 128 lines. Along with this two clock pulses are connected to each other for synchronization and X2/X4 RIO’s (534) connected with each other for high speed communication between them.

[0071] FIG. 6 illustrates a block diagram depicting the power supply sub system of the quad digital receiver main board according to the present invention. The power supply system (600) is intended to supply power to all the internal components and modules. The main power supply is fed through VPX connector of about +12V supply and is down converted to a block diagram depicting the power supply sub system of the quad digital receiver main board according to the present invention required voltage levels using switching and linear voltage regulators. The VPX connector (624) supplies power to all the four ADC’s, three FPGA’s and other components through quad digital receiver board digital interface. The LTM 4637 is used to supply the required core and auxiliary voltages to FPGA’s and the maximum current consumed by the entire board at 12V is 7.58A (91W max).

[0072] FIG. 7 illustrates a block diagram (700) depicting the temperature sensor of the receiver unit according to the present invention. The temperature sensor controller senses the temperature of the board is an on-chip digital output temperature sensor with 8 bit resolution. The temperature sensor controller comprises of configuration registers include a serial bus interface register (758), address register (760), temperature register (762) and data register (764) for resetting to their default values after power ON. When the power is ON the internal configuration registers (758, 760, 762, and 764) defaults to their reset values, at first positive CLK edge ofFPGA_CLK a serial clock of 400 KHz shall be made available to initiate any serial transfer and monitoring.

[0073] FIG. 8 illustrates a block diagram (800) depicting the temperature sensor of the receiver unit according to the present invention. The quad digital receiver board supports remote programming and up gradation of all the three FPGA’s and also supports for fail-safe and fail back FPGA image in case of recognition failure. The remote programming is implemented to program new or enhanced bit streams into the update bit stream area. The FPGA preferably configures with the update bit stream. If the remote update procedure fails or is interrupted, the FPGA must be able to reliably fallback and configure from the golden bit stream. The SPI PROMs used in this case have twice the memory size to store the golden bit stream and the update bit stream. The multi-boot feature of FPGA enables to load the bit stream from particular location.

[0074] The remote programming set up comprises of connecting the two FPGA’s (808) FPGA-1 and FPGA-2 to the third FPGA-3. Further the third FPGA-3 is connected to Ethernet PHY (838) and in turn connected to VPX connector (824). The FPGA-1 and FPGA-2 are connected to SPI PROM for remote pupation. And a DDR2 and an SPI PROM are connected to the third FPGA-3 (808) for storing data.

[0075] The described embodiments are to be considered in all respects only as illustrative and not restrictive. The scope of the invention is, therefore, indicated by the appended claims rather than by the foregoing description. All changes which come within the meaning and range of equivalency of the claims are to be embraced within their scope.