The present invention relates to a printing device. More particularly, the
invention relates to the use of HMP (Heterogeneous Multi-core processing)
system architectures for large format digital inkjet printer control system.
5
Background of the Invention
Known present technologies in the industrial digital inkjet printing domain
are known to use physically separate microcontrollers, microprocessors, DSPs
or PLCs (Programmable logic controller) for the control system. So, the
10 performance of these systems is less optimized, they consume more power,
they are not cost effective, they are less reliable and secure.
Summary of the Invention
The following presents a simplified summary of one or more
15 embodiments in order to provide a basic understanding of such embodiments.
This summary is not an extensive overview of all contemplated embodiments,
and is intended to neither identify key or critical elements of all embodiments
nor delineate the scope of any or all embodiments. Its sole purpose is to
present some concepts of one or more embodiments in a simplified form as a
20 prelude to the more detailed description that is presented later.
In accordance with exemplary embodiments of the present invention,
use of HMP (Heterogeneous Multi-core processing) architecture of the MPU
(Micro Processor Unit) for large format digital inkjet printer control system
solves the above-mentioned problem.
3
In one aspect of the present invention relates to a digital inkjet printer
control system. The system including a Graphical User Interface (GUI) for an
operator and an embedded control system operable coupled with the GUI. The
control system is housed inside the printer body, the control system comprises
5 of multiple processing elements. The printer control system utilizes a HMP
(Heterogeneous Multi-core processor) System on Chip (SoC).The part of the
control system that requires capabilities of an underlying operating system runs
on a high MIPS application processor core (the first processor), whereas the
input/output control part that requires very quick response from the control
10 system resides on a smaller core (the second processor) thereby delivering
very low response latency, the entire control system is designed and
implemented using single SoC utilizing its resources in an optimized way.
Other aspects, advantages, and salient features of the invention will
become apparent to those skilled in the art from the following detailed
15 description, which, taken in conjunction with the annexed drawings, discloses
exemplary embodiments of the invention.
Brief description of the drawings
The above and other aspects, features, and advantages of certain
20 exemplary embodiments of the present invention will be more apparent from
the following description taken in conjunction with the accompanying drawings
in which:
FIG. 1 is a block diagram illustrating the structure of the printer 100
according to this embodiment.
4
FIG. 2 shows a system block diagram of a typical industrial digital inkjet
printer control system, according to one embodiment of the present invention.
FIG. 3 shows a flow chart of handling printer’s nominal latency tasks and
low latency tasks, as an example embodiment in conjunction with the invention.
5 FIG. 4 is a block diagram of an exemplary electronic system including
the SoC according to some embodiments.
Persons skilled in the art will appreciate that elements in the figures are
illustrated for simplicity and clarity and may have not been drawn to scale. For
example, the dimensions of some of the elements in the figure may be
10 exaggerated relative to other elements to help to improve understanding of
various exemplary embodiments of the present disclosure.
Throughout the drawings, it should be noted that like reference numbers
are used to depict the same or similar elements, features, and structures.
15 Detail description of the Invention
The inventive concept now will be described more fully hereinafter with
reference to the accompanying drawings, in which certain exemplary
embodiments are shown. The inventive concept may, however, be embodied in
many different forms and should not be construed as limited to the exemplary
20 embodiments set forth herein. Rather, these exemplary embodiments are
provided so that this disclosure will be thorough and complete, and will, fully
convey the scope of the inventive concept to those skilled in the art. In the
drawings, the size and relative sizes of layers and regions may be exaggerated
for clarity. Like numbers refer to like elements throughout.
5
It will be understood that when an element is referred to as being
“connected” or “coupled” to another element, it can be directly connected or
coupled to the other element or intervening elements may be present. In
contrast, when an element is referred to as being “directly connected” or
5 “directly coupled” to another element, there are no intervening elements
present. As used herein, the term “and/or” includes any and all combinations of
one or more of the associated listed items and may be abbreviated as “/”.
It will be understood that, although the terms first, second, etc. may be
used herein to describe various elements, these elements should not be limited
10 by these terms. These terms are only used to distinguish one element from
another. For example, a first signal could be termed a second signal, and,
similarly, a second signal could be termed a first signal without departing from
the teachings of the disclosure.
The terminology used herein is for the purpose of describing particular
15 embodiments only and is not intended to be limiting of the inventive concept. As
used herein, the singular forms “a”, “an” and “the” are intended to include the
plural forms as well, unless the context clearly indicates otherwise. It will be
further understood that the terms “comprises” and/or “comprising,” or “includes”
and/or “including” when used in this specification, specify the presence of
20 stated features, regions, integers, steps, operations, elements, and/or
components, but do not preclude the presence or addition of one or more other
features, regions, integers, steps, operations, elements, components, and/or
groups thereof.
6
Unless otherwise defined, all terms (including technical and scientific
terms) used herein have the same meaning as commonly understood by one of
ordinary skill in the art to which the inventive concept belongs. It will be further
understood that terms, such as those defined in commonly used dictionaries,
5 should be interpreted as having a meaning that is consistent with their meaning
in the context of the relevant art and/or the present application, and will not be
interpreted in an idealized or overly formal sense unless expressly so defined
herein.
Hereinafter, the term “module” may indicate a hardware component
10 which performs a function and an operation corresponding to its name, a
computer program code for executing particular function and operation, or an
electronic recording medium, e.g., a processor, equipped with the computer
program code. In other words, the module may be a functional and/or structural
combination of hardware for realizing the inventive concept and/or software for
15 running the hardware.
FIG. 1 is a block diagram illustrating the structure of the printer 100
according to this embodiment. If print data including character or image data to
be printed sent from the host computer 180 is received by the printer 100, the
received data is input to and held in a receive buffer 110. Further, model20 specific data that has been stored in the ROM 130b of printer 100, data for
confirming whether data has been transferred correctly from the host computer
180 to the printer 100, and data for reporting the operating status of the printer
100 is transmitted from the printer 100 to the host computer 180.
7
Data that has been stored in the receive buffer 110 is transferred to a
RAM 130a under the control of a CPU 120 and is stored in the RAM 130a
temporarily. The ROM 130b stores a control program executed by the CPU
120, various initial-setting parameters, as well as model-specific parameters
5 and control commands of the printer 100. In response to a command from the
CPU 120, an engine controller 140 drives and controls a printer engine 145
having mechanical portions such as a carriage motor and paper-feed motor.
A sensor/switch controller 150 sends the CPU 120 signals from various
sensors and from a sensor/switch unit 155 that includes the switches of the
10 control panel. In response to a command from the CPU 120, a display-element
controller 165 drives LEDs on the control panel and a display unit 165 having
liquid crystal display elements. A printhead controller 170 drives and controls
the printhead 175 in accordance with a command from the CPU 120. The
printhead controller 170 senses, e.g., the temperature of the printhead 175,
15 which is indicative of the status of the printhead 175, and sends this signal to
the CPU 120. In response, the CPU 120drives and controls the printhead 175
based upon the temperature information.
FIG. 2 shows a system block diagram of a typical industrial digital inkjet
printer control system, according to one embodiment of the present invention.
20 The digital industrial inkjet printer consists of a Graphical User Interface (GUI)
210 for an operator (not shown in figure) and an embedded control system 220
housed inside the printer body 200. The GUI 210 and the printer 200 are
coupled via a high speed communication 215 (e.g. Ethernet or USB).The print
control system 220 includes an application processor 240 and a real time core
8
250, in which both are on the same wafer i.e. system on chip (SoC) 230. The
print control system further includes a data management 270, motion system
280, ink management 290 and a print head interface 260.
With respect to a heterogeneous multi-core system, it has cores that are
5 not identical. In an example embodiment, the heterogeneous multi-core system
includes at least one first core and at least one second core, where each first
core has first processor architecture, and each second core has second
processor architecture that is different from the first processor architecture.
Hence, if the same task is running on the first core and the second core,
10 instructions executed by the first core would be different from that executed by
the second core.In general, the first core and the second core implemented in
the heterogeneous multi-core system would have different computing power
due to different processor architecture. For example, the first core is a
performance-oriented processor core, while the second core is a power-saving
15 oriented processor core. Hence, the computing power/capability of the first core
is greater than that of the second core.
In an example embodiment, the printer control system design utilizes the
HMP (Heterogeneous Multi-core processing) based SoC architecture. The part
of the control system that requires capabilities of an underlying operating
20 system runs on a high MIPS application processor core, whereas the
input/output control part that requires very quick response from the control
system like the encoder sensor, limit switches or high speed motion control
reside on a smaller core that can guarantee very low response latency. This
9
way entire control system is designed and implemented using single SoC
utilizing its resources in an optimized way.
Four key reasons why the use of a heterogeneous multi-core processing
configuration is beneficial and solves problems of existing known techniques:
5 (1) Performance optimization: Prior known inventions make use of
embedded firmware running on application processor with an OS such as
Windows or Linux, and a physically separate microcontroller, DSP or even PLC
running firmware that address hard real time requirements. The two physically
separate entities are connected to each other using low bandwidth and high
10 latency interfaces. In the present invention by the means of using HMP based
SoC, addresses both low latency and high latency system requirements by
using the multiple asymmetric cores within the same physical SoC connected
over high speed very low latency buses thereby delivering better overall
performance.
15 (2) Reduction of power consumption: Many processes providing the
monitoring of sensors and controlling of various motors or actuators require
determinism and are efficiently run using an RTOS on top of the smaller
dedicated core. If the use case also calls for a rich OS running on higher MIPS
application core, the rich OS may spend much of its time waiting on user
20 interaction or communication from the various sensors being monitored by the
RTOS running on the dedicated smaller core. In this situation the system can
take advantage of this situation and power gate the large application core until
either a predetermined wake-up time or through an interrupt generated from the
dedicated smaller core. By shutting down the large core and associated silicon,
10
the amount of power that is needed to run the system can be optimized. Also
existing designs are using separate MCU or PLC for time critical tasks. Cutting
down these modules further reduce overall power consumption.
(3) Improved system reliability and security: A natural benefit of
5 distributing processes between the two cores is the ability to create separation
between the two asymmetric processing environments. A system can now
control or forbid access between the two processing environments and in turn
provide greater stability and security, preventing processes that goes awry from
affecting the real time processing domain. By separating access to the
10 peripherals/memory between the two processing environments, a secure
firewall is created that improves both system reliability and security.
(4) Cost optimization: Cutting down the separate hardware and software
modules (MCU or PLC) will optimize the design cost. It simplifies the
manufacturing process and speed up manufacturing too. And hence the overall
15 product cost reduces.
The present invention provides a way of using Heterogeneous multiprocessor (HMP) architecture for large format digital inkjet printer control
systems. A large format digital inkjet printer control system has to meet a wide
spectrum of response latency requirements. The innovative design approach of
20 the present invention incorporates a HMP based “system on chip” (SoC) to
successfully meet these wide spectrums of response latency requirements.
Different real time operating systems running separate embedded applications
on different processor cores within a single System on Chip (SoC) address the
complex latency response requirements. A higher MIPS application processor
11
core runs firmware that needs a full-fledged operating system with layered
software stack-based network interfaces, whereas a smaller processor core
running dedicated and purpose-built embedded firmware to meet very low
latency (hard real time) requirements of the control system functionality.
5 FIG. 3 shows a flow chart of handling printer’s nominal latency tasks and low
latency tasks. In one embodiment, the flow chart 300 having two section.
Section 340, shows soft real-time domain, handling printer’s nominal latency
tasks, and section 380 which shows hard real-time, handling printer’s low
latency tasks.
10 FIG. 4 is a block diagram of an exemplary electronic system including
the SoC according to some embodiments. The electronic system may be
implemented, for example, as a personal computer (PC), a data server or a
portable electronic device.
The portable electronic device may be a laptop computer, a cellular
15 phone, a smart phone, a tablet personal computer (PC), a personal digital
assistant (PDA), an enterprise digital assistant (EDA), a digital still camera, a
digital video camera, a portable multimedia player (PMP), portable navigation
device (PDN), a handheld game console, or an e(electronic)-book device.
The electronic system includes the SoC 400, a power source 410, a
20 storage device 420, a memory 430, I/O ports 440, an expansion card 450, a
network device 460, and a display 470. The electronic system may further
include a camera module 480.The SoC 400 may include the CPU 120
illustrated in FIG. 1. The CPU 120 may be a multi-core processor.
12
The SoC 400 may control the operation of at least one of the elements
410 through 480. The power source 410 may supply an operating voltage to at
least one of the elements 120, and 420 through 480. The storage device 420
may be implemented, for example, by a hard disk drive (HDD) or a solid-state
5 drive (SSD).
The memory 430 may be implemented by a volatile or non-volatile
memory. The memory 430 may correspond to the external memory 130 (a,b)
illustrated in FIG. 1. A memory controller (not shown) that controls a data
access operation, e.g., a read operation, a write operation (or a program
10 operation), or an erase operation, on the memory 430 may be integrated into or
embedded in the SoC 400. Alternatively, the memory controller may be
provided between the SoC 400 and the memory 430.
The I/O ports 440 are ports that receive data transmitted to the electronic
system or transmit data from the electronic system to an external device. For
15 instance, the I/O ports 440 may include a port connecting with a pointing device
such as a computer mouse, a port connecting with a printer, and a port
connecting with a USB drive.
The expansion card 450 may be implemented as a secure digital (SD)
card or a multimedia card (MMC). The expansion card 450 may be a subscriber
20 identity module (SIM) card or a universal SIM (USIM) card.
The network device 460 enables the electronic system to be connected
with a wired or wireless network. The display 470 displays data output from the
storage device 420, the memory 430, the I/O ports 440, the expansion card
450, or the network device460.
13
The camera module 480 converts optical images into electrical images.
Accordingly, the electrical images output from the camera module 480 may be
stored in the storage module 420, the memory 430, or the expansion card 450.
Also, the electrical images output from the camera module 480 may be
5 displayed through a display 470.
As described above, according to some embodiments, the cores may
include different types of cores (e.g., having different architectures, sizes,
and/or processing speeds) that form a heterogeneous multi-core processor.
Moreover, first-type cores and second-type cores may be asymmetrically
10 switched with each other, so that the number of first-type cores and the number
of second-type cores being used are flexibly adjusted, which is advantageous in
designing multi-core processors.
Further, in the foregoing detailed description of embodiments of the
invention, various features are grouped together in a single embodiment for the
15 purpose of streamlining the disclosure. This method of disclosure is not to be
interpreted as reflecting an intention that the claimed embodiments of the
invention require more features than are expressly recited in each claim.
Rather, as the following claims reflect, inventive subject matter lies in less than
all features of a single disclosed embodiment. Thus, the following claims are
20 hereby incorporated into the detailed description of embodiments of the
invention, with each claim standing on its own as a separate embodiment.
It is understood that the above description is intended to be illustrative,
and not restrictive. It is intended to cover all alternatives, modifications and
equivalents as may be included within the spirit and scope of the invention as
14
defined in the appended claims. Many other embodiments will be apparent to
those of skill in the art upon reviewing the above description. The scope of the
invention should, therefore, be determined with reference to the appended
claims, along with the full scope of equivalents to which such claims are
5 entitled. In the appended claims, the terms “including” and “in which” are used
as the plain-English equivalents of the respective terms “comprising” and
“wherein,” respectively.

We Claim:
1. A digital inkjet printer control system, comprising:
a Graphical User Interface (GUI) for an operator; and
an embedded control system operable coupled with the GUI, the control
5 system housed inside the printer body, the control system comprises a first
processor and a second processor, the first processor and the second
processor are heterogeneous multiprocessors, the printer control system
utilizes the HMP (Heterogeneous Multi-core processor)System on Chip (SoC)
architecture in which the part of the control system that requires capabilities of
10 an underlying operating system runs on a high MIPS application processor core
(the first processor), whereas the input/output control part that requires very
quick response from the control system reside on a smaller core (the second
processor) thereby deliveringvery low response latency, the entire control
system is designed and implemented using single SoC utilizing its resources in
15 an optimized way.
2. The system as claimed in claim 1 is an efficient and technological
advance printer control system utilizing the utmost capability of a MPU (Micro
Processor Unit) by utilizing the HMP (Heterogeneous Multi-core processing).
20
3. The system as claimed in claim 1, wherein the first processor and the
second processor which process the data running in real time for separate
embedded applications on different processor cores within a single System on
Chip (SoC) address the complex latency response requirements.
16
4. The system as claimed in claim 1, wherein the first processor which is a
higher MIPS application processor core runs firmware which has a full-fledged
operating system with layered software stack-based network interfaces.
5 5. The system as claimed in claim 1, wherein the second processor which
is a smaller processor core running dedicated and purpose-built embedded
firmware to meet very low latency (hard real time) requirements of the control
system functionality.
10 6. The system as claimed in claim 1, wherein, using Heterogeneous multiprocessor (HMP) architecture for large format digital inkjet printer control
systems has to meet a wide spectrum of response latency requirements.
7. The system as claimed in claim 1, wherein using of HMP based SoC,
15 addresses both low latency and high latency requirements by using the multiple
asymmetric cores within the same physical SoC connected over high speed
very low latency buses thereby delivering better overall performance.
8. The system as claimed in claim 1, wherein by distributing processes
20 between the two cores which creates separation between the two asymmetric
processing environments which provides greater stability and security,
preventing processes that goes awry from affecting the real time processing
domain, wherein by separating access to the peripherals/memory between the
two processing environments, a secure firewall is created that improves both
25 system reliability and security.
17
9. The system as claimed in claim 1 by utilizing the HMP (Heterogeneous
Multi-core processing) based in System on Chip (SoC) architecture cut down
the separate hardware and software modules (MCU or PLC) which eventually
optimize the design cost, simplifies the manufacturing process and speed up
5 manufacturing.
10. The system as claimed in claim 1, the first processor which is an
application processor, and the second processor is a real-time core processor
which are integrated as a system-on-chip device all sharing a common wafer.