FORM 2
THE PATENTS ACT 1970
(39 of 1970)
&
THE PATENTS RULES, 2003
COMPLETE SPECIFICATION
(See Section 10; rule 13)
TITLE OF THE INVENTION
Variable Frequency Pulse Signal Generation System and method of signal generation thereof based on serial communication


APPLICANTS
TATA MOTORS LIMITED, an Indian company
having its registered office at Bombay House,
24 Homi Mody Street, Hutatma Chowk,
Mumbai 400 001 Maharashtra, India
INVENTORS
Mr. Vishwas Vaidya and Ms. Kshitija Desai
both are Indian nationals
of TATA MOTORS LIMITED,
an Indian company having its registered office
at Bombay House, 24 Homi Mody Street, Hutatma Chowk,
Mumbai 400 001 Maharashtra, India

PREAMBLE TO THE DESCRIPTION
The following specification particularly describes the invention and the manner in which it is to be performed.

16 SEP 2008

FIELD OF INVENTION
This invention relates to Variable Frequency Pulse Signal Generation System and more particularly it relates to Variable Frequency Pulse Signal Generation System which is based on serial communication.
BACKGROUND OF INVENTION
Variable frequency pulse generators are required in various industrial applications such as motor control applications, where they are required to govern the motor speed. They also can be used as a reference signal source to calibrate frequency driven inputs of electronic systems. They can also provide base signal to derive other wave shapes like sine, triangular or saw-tooth required for various signal processing applications. Micro-controller based solutions for pulse generation are generally preferred for pulse generation because of the flexibility and programmability they offer. The chip-manufacturers recommend use of on-chip timer based resources for this purpose. Although this technique is widely used, it suffers from following draw-backs:
- It ties-up a timer resource only for pulse generation purpose, thereby making it unavailable for other tasks in the application.
- Use of timer based pulse generation is mutually exclusive with on chip event counting hardware.
Hence applications requiring event counting cannot use pulse generation using timers.
US 6,995,592 B2 describes use of on-chip Pulse Width Modulator block for generation of the variable frequency waveform. This approach eats-up PWM (Pulse
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i Modulator) resources on the chip and hence cannot be used in applications 'ing use of PWM outputs, timers, event counters where these resources need to located. Also this approach depends on a look-up table to output amplitude s to be modulated in the PWM signal. This consumes a fair amount of )ry.
,145,371 describes a Phase Lock Loop based methodology which intends to the overall pulse count over a period constant but suffers from pulse to pulse ^jitters. This approach though suitable for video signal processing application acceptable for other applications such as motor control where no timing jitter eptable.
IP2001/011020 uses discrete digital chips like adders, comparators and pulse ator for implementing the concept. This approach lacks programmability of icro-controller based approach, apart from leading to high component count.
SCTS OF INVENTION
The main object of this invention is to provide a Variable Frequency Pulse Signal Generation system based on serial communication.
Another object of this invention is to provide Variable Frequency Pulse Signal Generation System based on on-chip serial transmission resources.
Yet another object of this invention is to provide Variable Frequency Pulse Signal Generation System based on serial communication which is simple in construction and cost-effective.
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STATEMENT OF INVENTION
According to present invention A Method of generating Variable frequency Puis signals comprising the steps of
a) Receiving frequency value from frequency table;
b) Converting frequency value into ON and OFF period intervals;
c) Generating Bit pattern for a byte for issuing said ON or OFF period intervals;
d) Generating Bit pattern for a byte by based on bit pattern in previous byte during transition between said ON and OFF period intervals.
Another object of the present invention is to provide a Variable Frequency Pulse Signal (VFPS) Generation System based on serial communication comprises of a micro-controller, at least one input and output interfaces, said micro-controller is connected with said input and output interfaces and said micro-controller is embedded with an algorithm to generate a VFPS bit pattern on on-chip serial synchronous transmitter channel.
BRIEF SUMMARY OF INVENTION
Variable frequency pulse signal (VFPS) generation system based on serial communication in accordance with this invention basically comprises of embedded micro-controller with input and output interfaces, a VFPS generator based on an on-chip serial synchronous transmitter and a buffer circuit. Wherein said micro¬controller is connected with said input and output interfaces. The said micro¬controller is further interfaced with VFPS generator using its on-chip serial transmitter hardware means. The serial transmitter output means of said microcontroller is connected to buffer circuit based on low out-put impedance
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operational amplifier. The micro-controller apart from interacting with the said input/output interfaces runs an algorithm to generate a VPPS bit pattern on serial transmitter channel. The maximum possible frequency generated by the system corresponds to half the baud-rate frequency at which the on-chip serial communication is programmed.
Another objective of the present invention is a Variable Frequency Pulse Signal Generation technique which makes use of on-chip resources comprising of serial synchronous transmitter circuits. This technique basically uses an on-chip embedded algorithm to generate Variable Frequency Pulse Signal (VFPS) at the output of the "Transmitter Pin" which is connected to a buffer circuit. Output of the buffer circuit is connected to systems requiring VFPS input signals such as motor controllers, simulated sensor signals for Hardware In the Loop (HIL) applications etc.
Method of generating VFPS consists of following steps:
a. Program the on-chip synchronous serial communication resource to a
baud-rate frequency which is at least twenty times in value compared
to the maximum required frequency of the pulse signal, as dictated by
the application.
b. Compute number of "on state bits" followed by number of "off state
bits". (These will be same for a square wave pulse-train but differ for
a rectangular wave pulse train).
c. Form and generate at the output, a byte pattern corresponding to "on
state period"
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d. Form and generate at the output, a byte pattern corresponding to "off
state period"
e. Go back to step "b" so as to continue this cycle, so that frequency of
the output pulse signal is varied every instant, in accordance with the
application requirement.
BRIEF DESCRIPTION OF DRAWINGS
Fig 1 shows block diagram of Variable Frequency Pulse Generation System based
on serial communication
Fig 2 Shows Flow-chart of overall software used in Variable Frequency Pulse
Generation system based on serial communication
Fig 3 shows Flow-chart of VFPS bit pattern generation used in the said system
based on serial communication
DESCRIPTION OF THE PREFERRED EMBODIMENTS OF THE INVENTION
Referring now to the drawings wherein the illustrations are for the purpose of demonstrating a preferred embodiment of the invention only, and not for the purpose of limiting the same
Referring to fig.l, VFPS generation system based on serial communication comprises of embedded micro-controller (1) with input and output interfaces (2), a VFPS generator based on an on-chip serial synchronous transmitter (3) and a low-impedance buffer (4) , Wherein said micro-controller is connected with said input and output interfaces. The serial transmitter output means (3) of said
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microcontroller is connected to low-impedance buffer network (4) based on an operational amplifier. The micro-controller apart from interacting with the said input/output interfaces (2) runs an algorithm to generate a WPS bit pattern on serial transmitter channel (3). The on-chip baud-rate generator is programmed for twenty times the maximum desired frequency for the application.
The end application uses this concept for generating variable frequency pulse signal to suit its functional needs. Generally, such an application needs to generate pulse signals of different frequencies at different time instants. It needs to maintain a frequency table in the form of a circular buffer so as to feed variable frequency values to the core algorithm which implements variable frequency pulse signal generation. The core algorithm periodically reads the contents of the frequency table so as to implement required values of on period and off periods of dictated by application specific frequency generation needs.
Referring to Fig 2
Overall software strategy used in said VFPS generator system basically comprises of four steps.
- Step 1, Program the on-chip baud-rate generator for the synchronous serial communication to a frequency twenty times the value compared to the maximum one required for the application . (Say lOOKhz baud-rate for maximum application frequency of 5 KHz. This corresponds to individual bit interval of 10 micro-seconds and worst case resolution/accuracy of 5% at the maximum frequency)
- Step2, Convert the required pulse frequency signal at any given instant into "On Bit counter" and Off Bit counter. (For generating a lKhz square wave pulse, On Period being 500 micro-second and so also the off period.
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This gives counter values for both the periods = Pulse Period/ Bit interval = 500micro-secs/10micro-secs = 50 bit duration.
Step 3, Generate a bit pattern for issuing the desired on and off period intervals of the pulse. - Step 4, When the application requires a different pulse frequency , go back to steps 2 and 3 so as to generate the pulse signal with the required value of the changed frequency.
Fig 3 explains the core-algorithm which converts an on period counter value into a series of "l"s and off period counter value into a series of "0"s. The algorithm follows three steps to generate three portions of a typical period counter:
Step 1 transmits appropriate number of 'On-state bytes' each with a value 'OxFF'. Number of On State Bits required to be issued at the output are obtained by subtracting on bits in the preceding transition byte (if any), from the total on-state bit count. The result is divided by 8. E.g. for an On bit count, of 50 and a preceding transition byte of 00001111b (notice four on state bits), Total On-state Bytes generated are (50-4)/8 = 5 (considering integer division). However for the very first Pulse cycle, there will not be any preceding transition byte and hence we need to carry our an integer division of (50-0)/8 = 6 (Fig. 3)
Step 2 transmits an 'On to Off Transition Byte' which marks end of 'On-Period' and start of'Off-period' Transition byte is based on the remainder of above division (i.e. remainder of 50 Mod 8 = 2 in our case.) This byte consists of a number of consecutive Ts starting from LSB backwards. Value of remainder determines the number of Ts. For remainder = 4, the number T s to be packed are 4, giving
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transition byte as '0000 0011b' in binary or 0x03 in hexadecimal. All other bits in the transition byte are '0.
Table 2 lists all possible values of the remainder and associated values for the transition bytes.
Step 3 transmits off bits conesponding to the off portion of the pulse. Number of "Off-state bits" each with a value of 0x00 are computed by subtracting number of off bits in the transition byte (6 in our case) from the off period count (50 in our case) giving 50-6 = 44. This is generated by transmitting 5 off bytes (40 off bits) followed by an "off to on transition byte" of Ox OF.
Step 1 is again repeated now, except we need to subtract for on state bits already Transmitted by "off to on transition byte" (4 in this case). Hence we need to transmit 50-4 = 46 more "on bits". This is achieved by 5 bytes with value Oxff and 6 more "on bits" by using an "on to off transition byte" of Ox 3f.
Steps 2, 3 and 4 are repeated over an over again. Transition bits need to be accurately inserted to preserve the accuracy of on and off periods.
The foregoing description is a specific embodiment of the present invention. It should be appreciated that this embodiment is described for purpose of illustration only, and that numerous alterations and modifications may be practiced by those skilled in the art without departing from the spirit and scope of the invention. It is intended that all such modifications and alterations be included in so far as they come within the scope of the invention as claimed or the equivalents thereof.
As an application example consider variable frequency pulse signal generation required for simulating Vehicle RPM sensor signal for testing an automotive ECU.
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Assume that the vehicle speed signal is to be updated every second. The application uses a frequency table for entering different RPM values in accordance with a test-driving pattern. (Thereby meeting the functional needs of the application). The core algorithm samples the table every second to obtain the frequency value corresponding to the RPM value desired as per the driving pattern at a given second. This frequency value is transformed into a pulse pattern conforming to the specified frequency by the core algorithm. For the next second next entry inside the table is read and processed by the core algorithm and so on. This in effect generates a pulse pattern conforming to the stipulated driving cycle.
Example Pulse Cycle for 1KHz Wave
1 Total Bits for 1msec period with lOOKhz baud-rate=100 Bits = 50 On Bits+ 50 Off Bits
2 Number of On state Bytes =50 /8 = 6 (Integer division)
3 Remainder=50 -(8*6) = 2
Transition byte = 0000 001 lb = 0x03H (Notice two 'l's from lsb side)
4 Number of Off State Bytes =Total (50 bytes - 6 Off bits in the preceding
Transition Byte) /8 = 44 div 8 = 5 Off state bytes.
5 Off to On Transition byte should contain 44 Mod 8 = four off bits. Hence
transition byte now has value of 0000 111 lb = OxF H.
The foregoing description is a specific embodiment of the present invention. It should be appreciated that this embodiment is described for purpose of illustration only, and that numerous alterations and modifications may be practiced by those skilled in the art without departing from the spirit and scope of the invention. It is intended that all such modifications and alterations be included insofar as they come within the scope of the invention as claimed or the equivalents thereof.
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WE CLAIM
1. A Method of generating Variable frequency Pulse signals comprising the steps of
receiving frequency value, from frequency table;
converting frequency value into ON and OFF period intervals;
generating Bit pattern for a byte for issuing said ON or OFF period intervals;
generating Bit pattern for a byte by based on bit pattern in previous byte during
transition between said ON and OFF period intervals.
2. A method as claimed in claim 1 wherein said bit pattern is generated by the
steps of
a. dividing the difference between ON bit count for said ON period and ON
bits included in any preceding transition Byte by 8 to obtain appropriate number of
ON state Bytes and forming a transition byte having remainder of ON bits;
b. transmitting appropriate number of On-state bytes each with a value 'OxFF'
followed by the transition byte as computed in step (a);
c. dividing the difference between OFF bit count for said OFF period and
OFF bits included in any preceding transition byte by 8 to obtain appropriate
number of Off-state bytes and forming a transition byte having remainder of OFF
bits;
d. transmitting appropriate number of Off-state bytes each with a value
'0x00' followed by the transition byte as computed in step (c).
3. A Variable Frequency Pulse Signal (VFPS) Generation System based on serial
communication comprising
a micro-controller;
at least one input and output interface;
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said micro-controller being connected with said input and output interfaces and embedded with a program configured to perform the method as claimed in claim 1 to generate a VFPS bit pattern on on-chip serial synchronous transmitter channel.
4. The system as claimed in claim 3 wherein said serial synchronous transmitter of said microcontroller is connected to a low impedance buffer network to interface with output loads.
5. The system as claimed in claim 3 wherein said VFPS generator system has a serial bit pattern to provide required On state Period and Off State Period as per the
application requirement.
6. The system as claimed in claim 4 wherein said buffer is based on low impedance operational amplifier network.
7. The system substantially as herein described with reference to accompanying drawings.
8. A method of generating Variable frequency Pulse signals substantially as herein described with reference to accompanying drawings.
Dated this 16th day of September 2008
TATA MOTORS LIMITED By their Agent & Attorney

(Karuna Goleria)
of DePENNING & DePENNING
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