[CLAIMS] [Claim 1]
A variable resistance nonvolatile memory device including memory cells each having a variable resistance element, a resistance state of which reversibly changes based on an electrical signal, said device comprising:
a substrate;
bit lines in a plurality of layers which are stacked in a Z direction, and in which said bit lines extending in an X direction are aligned in a Y direction, the X and Y directions being directions orthogonal to each other on a plane parallel to a main surface of said substrate, and the Z direction being a direction in which the layers are stacked above the main surface of said substrate;
word lines in a plurality of layers which are stacked in the Z direction and formed at respective intervals between the layers of said bit lines, and in which said word lines extending in the Y direction are aligned in the X direction;
a memory cell array having said memory cells which ara formed at respective crosspoints of said bit lines in the layers and said word lines in the layers, and each of which is interposed between a corresponding one of said bit lines and a corresponding one of said word lines, said memory cell array including a plurality of basic array planes aligned in the Y direction, and each of said basic array planes having memory cells included in said memory cells and interposed between, among said bit lines in the layers, bit lines in the layers at the same position in the Y direction and said word lines crossing said bit lines at the same position;
global bit lines provided in one-to-one correspondence with said basic array planes; and
sets of a first selection switch element and a second selection switch element, said sets being provided in one-to-one correspondence with said basic array planes,
wherein each of said basic array planes further includes a first via group interconnecting only even-layer bit lines among said bit lines in said basic array plane, and a second via group interconnecting

only odd-layer bit lines among said bit lines in said basic array plane, and
for each of said basic array planes, said first via group in said basic array plane is connected to said global bit line corresponding to said basic array plane via one of said first selection switch element and said second selection switch element that are included in said set corresponding to said basic array plane, and said second via group in said basic array plane is connected to said corresponding global bit line via the other of said first selection switch element and said second selection switch element that are included in said corresponding set, and
when one of said basic array planes is a first basic array plane, and a different one of said basic array planes is a second basic array plane, said different one being adjacent to said first basic array plane an the Y direction,
said first via group in said first basic array plane and said second via group in said second basic array plane are adjacent to each other in the Y direction, and said second via group in said first basic array plane and said first via group in said second basic array plane are adjacent to each other in the Y direction,
said first via group in said first basic array plane is connected to said global bit line corresponding to said first basic array plane via said first selection switch element corresponding to said first basic array plane, and said second via group in said first basic array plane is connected to said corresponding global bit line via said second selection switch element corresponding to said first basic array plane,
said second via group in said second basic array plane is connected to said global bit line corresponding to said second basic array plane via said first selection switch element corresponding to said second basic array plane, and said first via group in said second basic array plane is connected to said corresponding global bit line via said second selection switch element corresponding to said second basic array plane, and
in said sets which correspond to said basic array planes, and each of which includes said first selection switch element and said

second selection switch element, electrical connection, and disconnection of said first selection switch elements are controlled by a first common bit line selection signal, and electrical connection and disconnection of said second selection switch elements are controlled by a second common bit line selection signal. [Claim 2]
The variable resistance nonvolatile memory device according to Claim 1,
wherein for each of said basic array planes, said first via group in said basic array plane connects all said even-layer bit lines in said basic array plane using a single via, and said second via group in said basic array plane connects all said odd-layer bit lines in said basic array plane using a single via, said even-layer bit lines being adjacent to each other in the Z direction with said odd-layer bit lines in said basic array plane interposed, and said odd-layer bit lines being adjacent to each other in the Z direction with said even-layer bit lines in said basic array plane interposed. [Claim 3]
The variable resistance nonvolatile memory device according to one of Claims 1 and 2, further comprising, for each of said basic array planes,
a current limiting circuit between said global bit line corresponding to said basic array plane and terminals, one of the terminals being a terminal of said first selection switch element corresponding to said basic array plane and the other of the terminals being a terminal of said second selection switch element corresponding to said basic array plane. [Claim 4]
The variable resistance nonvolatile memory device according to any one of Claims 1 to 3, further comprising:
a global bit line decoder/driver that selects at least one of said global bit lines, and applies a read voltage to said at least one selected global bit line;
a read circuit that reads the resistance state of a memory cell in said basic array piane corresponding to said at least one global bit line

selected by said global bit line decoder/driver; and
a control circuit that controls said global bit line decoder/driver,
wherein when an operation of reading from a memory cell in said first basic array plane is performed, said control circuit controls said global bit line decoder/driver such that an operation of reading from a memory cell in said second basic array plane is prevented from being simultaneously performed. [Claim 5]
The variable resistance nonvolatile memory device according to Claim 4,
wherein when the operation of reading from a memory cell in said first basic array plane is performed, said control circuit further controls said global bit line decoder/driver such that an operation of reading from a memory cell in a third basic array plane is simultaneously performed, said third basic array plane not being adjacent to said first basic array plane in the Y direction.