Description:RELATED APPLICATION
[0001] This patent application is related to and claims priority from India Patent Application No. 202044026971, filed 25 June 2020, entitled “VARIED BALL BALL-GRID-ARRAY (BGA) PACKAGES”.
[0002] The present application claims priority to U.S. Non-Provisional Patent Application No. 16/575,307, filed September 18, 2019 and titled “VARIED BALL BALL-GRID-ARRAY (BGA) PACKAGES,” the entire disclosure of which is hereby incorporated by reference.

TECHNICAL FIELD
[0003] Embodiments of the present disclosure relate to semiconductor devices, and more particularly to interconnect architectures that include first solder balls and second solder balls to provide improved yield in assembly processes.

BACKGROUND
[0004] The dynamic warpage of flip chip ball-grid-array (BGA) packages induces a variety of defects during surface mount technology (SMT) processes. Figure 1 is a cross-sectional illustration of a BGA package 100 that illustrates examples of some of the typical defects. The BGA package 100 may include a board 105 with a package substrate 115 attached to the board 105 by interconnects 125 between pads 107 and 117. A die 120 may be attached to the package substrate 115. As shown, warpage of the package substrate 115 may result in several of the defects. Defect 126 illustrates solder ball bridging (SBB). SBB defects occur when the solder balls are compressed, resulting in the interconnect width extending beyond tolerances and coalesce with a neighboring interconnect. Compression may be the result of increased warpage due to thinner substrate layer count, package shape variation due to the presence of large and thick stiffeners, and/or increased weight per bump due to the increased die size and package form factor. Warpage may also lead to other defects. For example, defect 127 is a head on pillow (HoP) defect that results from the solder ball not coalescing with the solder paste. Defect 128 is a non-contact open (NCO), and defect 129 is a non-wet open (NWO).
[0005] Warpage may be addressed by adding stiffeners onto the package substrate. However, stiffeners (and their necessary keep out zones) occupy valuable real estate on the top side of the package. In order to account for the warpage, stencil design optimization to tailor paste volumes to control solder volumes at different locations has been proposed. However, stencil designs are approaching the printing process limits to further reduce paste volume to prevent SBBs. Another proposed option is to use land side components (LSCs) on the backside of the package as a stand-off during SMT to prevent SBBs. However, the choice of LSC height is limited and are often too short to function as a stand-off, or are too tall and induce NCO defects. Also, height variations of LSCs between suppliers is large and not easily controllable. Another option is to use copper bumps or pillars on the motherboard to serve as a stand-off during SMT. However, this requires SMT process changes to attach the pillars using pick and place equipment, as well as occupying the constrained package and mother board real estate.

BRIEF DESCRIPTION OF THE DRAWINGS
[0006] Figure 1 is a cross-sectional illustration of an electronic package with a plurality of defects arising from the warpage of the package substrate.
[0007] Figure 2A is a cross-sectional illustration of a package substrate with first solder balls and second solder balls, in accordance with an embodiment.
[0008] Figure 2B is a cross-sectional illustration of the package substrate being attached to a board, in accordance with an embodiment.
[0009] Figure 2C is a cross-sectional illustration of an electronic package with interconnects formed from the first solder balls and the second solder balls, in accordance with an embodiment.
[0010] Figure 3A is a cross-sectional illustration of a first solder ball and a second solder ball after ball attach (BA) reflow, in accordance with an embodiment.
[0011] Figure 3B is a cross-sectional illustration of a first interconnect and a second interconnect after SMT, in accordance with an embodiment.
[0012] Figure 4A is a plan view illustration of a package substrate that illustrates the pin map with second solder balls at the corners of the package substrate, in accordance with an embodiment.
[0013] Figure 4B is a plan view illustration of a package substrate that illustrates the pin map with second solder balls at the corners and the center of the package substrate, in accordance with an embodiment.
[0014] Figure 4C is a plan view illustration of a package substrate that illustrates the pin map with second solder balls at the corners, the interior, and the center of the package substrate, in accordance with an embodiment.
[0015] Figure 4D is a plan view illustration of the package substrate that illustrates the pin map with the second solder balls along a perimeter and in the center of the package substrate, in accordance with an embodiment.
[0016] Figure 5A is a cross-sectional illustration of a first solder ball and a second solder ball, where the first solder ball and the second solder ball have different material compositions, in accordance with an embodiment.
[0017] Figure 5B is a cross-sectional illustration of a first solder ball and a second solder ball, where the first solder ball and the second solder ball have different volumes, in accordance with an embodiment.
[0018] Figure 5C is a cross-sectional illustration of a first solder ball and a second solder ball, where the second solder ball comprises a core, in accordance with an embodiment.
[0019] Figure 5D is a cross-sectional illustration of a first solder ball and a second solder ball, where the second solder ball comprises a core and a solder composition different than the solder composition of the first solder ball, in accordance with an embodiment.
[0020] Figure 6 is a cross-sectional illustration of an electronic system that comprises first level interconnects and second level interconnects, where the first level interconnects and the second level interconnects both comprise first solder balls and second solder balls, in accordance with an embodiment.
[0021] Figure 7 is a schematic of a computing device built in accordance with an embodiment.

EMBODIMENTS OF THE PRESENT DISCLOSURE
[0022] Described herein are electronic packages with interconnect architectures that include first solder balls and second solder balls to provide improved yield in assembly processes, in accordance with various embodiments. In the following description, various aspects of the illustrative implementations will be described using terms commonly employed by those skilled in the art to convey the substance of their work to others skilled in the art. However, it will be apparent to those skilled in the art that the present invention may be practiced with only some of the described aspects. For purposes of explanation, specific numbers, materials and configurations are set forth in order to provide a thorough understanding of the illustrative implementations. However, it will be apparent to one skilled in the art that the present invention may be practiced without the specific details. In other instances, well-known features are omitted or simplified in order not to obscure the illustrative implementations.
, Claims:1. A package comprising:
a first substrate;
a second substrate;
an array of interconnects between the first substrate and the second substrate, the array of interconnects including a plurality of first interconnects and a plurality of second interconnects, each of the first interconnects including a first solder comprising tin, and
each of the second interconnects comprising a copper core and a second solder surrounding the copper core, the second solder comprising tin;
wherein the array of interconnects includes corner regions and a middle, at least one of the second interconnects located in one of the corner regions and at least one of the first interconnects located in the middle.