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'Voltage Controlled Offset Amplifier'

Abstract: The present invention discloses an amplifier for controlling an offset voltage between its input nodes. The amplifier includes a current generator, a current mirror, and a differential amplifier. The current generator generates a reference current (Iref) by receiving a reference voltage (Vref). The current mirror includes a reference transistor and a tail transistor. The reference transistor receives the reference current (Iref) from the current generator, The tail transistor generates a tail current (Itail) through the reference transistor. The tail current has a value in a ratio of the reference current (Iref). The differential amplifier creates an offset voltage across the differential amplifier through the tail current by creating a potenţial drop across a resistance.

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Notices, Deadlines & Correspondence

Patent Information

Application #
Filing Date
30 March 2007
Publication Number
52/2008
Publication Type
INA
Invention Field
ELECTRICAL
Status
Email
Parent Application

Applicants

STMICROELECTRONICS PVT. LTD.
PLOT NO. 1, KNOWLEDGE PARK III, GREATER NOIDA-201308, UP, INDIA.

Inventors

1. NITIN BANSAL
6/115, SHIVAJI NAGAR, GURGAON-122001, HARYANA.

Specification

VOLTAGE CONTROLLED OFFSET AMPLIFIER Field of the Invention
The present invention relates to amplifier circuits and more specifically to amplifiers with controlled offset voltage between its two inputs,
Background of the Invention
Amplifiers are used in nearly every integrated circuit, The amplifiers can be used to accurately control the amplification of an input signal to a predetermined level, either in an inverting or non-inverting mann.er. The amplifier can also be used to amplify the difference of two input signals. As another example, the amplifiers may be used to differentiate or integrate an input signal. In still other applications, the amplifiers may merely be used as a buffer or driver wherein the output signal is the same as, or offset by a predetermined amount from, the input voltage. Normally the input offset voltage which originates from random mismatches in the devices fabrication is not desirable, as it is difficult to control. Some applications require a controlled input offset voltage between the two inputs of an amplifier,
FIGURE l illustrates an U.S. Patent Application No. 2005/0052233 by Moyer describing a controlled offset amplifier. The amplifier includes input transistors 103a and 103b, a current source 105, load resistors 107a and 107b, and an amplifier stage 109. The gates of the input transistors 103a and 103b are connected to two inputs, V.sub.il and V.sub.il. In one embodiment, the transistors are enhancement mode p-channel MOŞ transistors. The input transistors 103a and 103b are matched physically to have the same dimensions and to be as nearly identical as possible (with an exception detailed below). This ensures that the random offset of the input voltage due to variations in the process and due to străin in the silicon when the die is assembled into the package is less than about 5 millivolts. The offset is introduced by using the transistors 103a and 103b at the

input stage with different threshold voltage (Vt) implants. The amplifier further includes an amplification stage that receives a signal from the input stage and provides an output signal related to the signal.
The prior art as described above suffers from various problems. Firstly, this approach consumes extra process steps and large threshold voltage (Vt) variations over process and temperature. Secondly, the range of offset is limited by the difference in the threshold voltages (Vts) of the two devices.
Therefore, there is a need for a novei amplifier circuit that can effectively and efficiently control offset voltages between its inputs,
Summary of the Invention
It is an object of the present invention to provide an amplifier which can control offset voltage across its inputs.
To achieve the aforementioned objective, the present invention provides an amplifier module for controlling an offset voltage comprising:
a current generator for generating a reference current (Iref) by receiving a reference voltage (Vref);
a current mirror receiving a supply voltage (Vdd) and being operatively coupled to said current generator, said current mirror comprises:
a reference transistor receiving the reference current (Iref) from said current generator; and

a tail transistor generating a tail current (Itail) through said reference transistor, said tail current comprises current in a ratio of said reference current (Iref);
a differential amplifier operatively coupled to said current mirror for creating the offset voltage across said differential amplifier through said tail current by creating a potenţial drop.
Further the present invention provides a method for controlling an offset in an amplifier comprising:
generating a reference current (Iref) from a reference voltage (Vref) through an operaţional amplifier;
passing the reference current (Iref) as a tail current (Itail) through one of a branch of a current mirror circuit, said tail current comprises current in a ratio ofsaid reference current (Iref); and
generating said offset at an input of said amplifier through said tail current (Itail) by creating a potenţial drop.
Brief Description of the Drawings
The aforementioned aspects and other features of the present invention will be explained in the following description, taken in conjunction with the accompanying drawings, wherein:
FIGURE l illustrates a convenţional amplifier for controlling offset voltage.
FIGURE 2 illustrates a voltage controlled offset amplifier according to the present invention.

FIGURE 3 illustrates a flow diagram of a method for controlling offsets in an amplifier according to the present invention.
Detailed Description of the Invention
The preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, the present invention is not limited to the preferred embodiments, The present invention can be modified in various forms. The preferred embodiments of the present invention are only provided to explain more clearly the present invention to the ordinarily skilled in the art of the present invention. In the accompanying drawings, Hke reference numerals are used to indicate like components.
FIGURE 2 illustrates a voltage controlled offset amplifier according to the present invention. The amplifier includes a current generator 202, a current mirror 204, and a differential amplifier 206. The current generator 202 generates a reference current (Iref=Vref / Rl) by receiving a reference voltage (Vref) on its positive terminal. The current generator 202 includes an operaţional amplifier 208 coupled to an NMOS transistor M5 which is grounded through a resistance Rl. The current mirror 204 receives a supply voltage (Vdd) and is operatively coupled to the current generator 202. The current mirror 204 includes a reference transistor Mref and a tail transistor Mtail. The reference transistor Mref receives the reference current (Iref) from the current generator 202. The tail transistor Mtail generates a tail current (Itail) through the reference transistor Mref because of current mirror property. The tail current has a value in a ratio of said reference current (Iref). The reference current (Iref) and the tail current (Itail) are equal, The differential amplifier 206 operatively coupled to the current mirror 204 through the tail transistor Mtail for creating a desired offset voltage across the inputs of the differential amplifier 206, A resistance R2 is inserted between a drain terminal of a PMOS Ml and a source terminal of Mtail. The offset is generated through the tail current Itail by creating a potenţial drop across the resistance R2.

The input offset voltage is given by the relation as below: Voffset = Vref/2 * Itail / Iref * R2/R1
In an embodiment for a reference voltage of 1.2V, R1=10K, Mref size of lOOu/lu and Mtail size 20u/lu, R2=2k, the offset voltage is 24mv,
Thus depending upon the circuit requirement, the offset voltage can be controlled by the folio wing factors:
• changing reference voltage (Vref),
• the current ratio Iref/ Itail, and/or
• resistance ratio R2/R1
The factor R2/R1 is a ratio, thus even if R2 and Rl vary a lot with Process and temperature the ratio will remain the same.
The current ratio Iref / Itail is again independent of process and temperature and operation voltage effects.
The factor Vref is a bând gap reference voltage which is an accurate and fixed voltage level.
FIGURE 3 illustrates a flow diagram of a method for controlling imbalances according to the present invention. At step 302, a reference current (Iref) is generated from a reference voltage (Vref) through an operaţional amplifier. At step 304, the reference current (Iref) is passed as a tail current (Itail) through one of a branch of a current mirror circuit, the tail current comprises current in a ratio of said reference current (Iref). At step

J06, an offset is generated at an input of the amplifier through the tail current (Itail) by creating a potenţial drop across a resistor.
The present invention provides an amplifier for controlling offset voltage across its two inputs offers various advantages, First, the present amplifier provides flexibility for controlling an offset voltage based on circuit parameters (such as current ratio, resistance ratio, reference voltage, etc). Second, the amplifier is very cost effective as it utilizes simple circuits (such as transistors, resistors, operaţional amplifiers) for its construction and operation.
Although the disclosure of circuit and method has been described in connection with the embodiment of the present invention illustrated in the accompanying drawings, it is not limited thereto. It will be apparent to those skilled in the art that various substitutions, modifications and changes may be made thereto without departing from the scope and spirit of the disclosure.

We Claim:
1. An amplifier module for controlling an offset voltage comprising:
a current generator for generating a reference current (Iref) by receiving a
reference voltage (Vref);
a current mirror receiving a supply voltage (Vdd) and being operatively
coupled to said current generator, said current mirror comprises:
a reference transistor receiving the reference current (Iref) from said
current generator; and
a tail transistor generating a tail current (Itail) through said reference
transistor, said tail current comprises current in a ratio of said reference
current (Iref);
a differential amplifier operatively coupled to said current mirror for
creating the offset voltage across said differential amplifier through said
tail current by creating a potenţial drop.
2. The amplifier as claimed in claim l, wherein said current generator comprises an
operaţional amplifier and a transistor.
3. The amplifier as claimed in claim l, wherein said reference transistor comprises a
PMOS transistor.
4. The amplifier as claimed in claim l, wherein said tail transistor comprises a
PMOS transistor.
5. The amplifier as claimed in claim l, wherein said ratio equals to unity.
6. A method for controlling an offset in an amplifier comprising:
generating a reference current (Iref) from a reference voltage (Vref) through an operaţional amplifier;

passing the reference current (Iref) as a tail current (Itail) through one of a branch of a current mirror circuit, said tail current comprises current in a ratio of said reference current (Iref); and
generating said offset at an input of said amplifier through said tail current (Itail) by creating a potenţial drop across a resistor.
7. An amplifier module for controlling an offset voltage substantially as herein
described with reference to and as illustrated in the accompanying drawings.
8. A method for controlling an offset in an amplifier substantially as herein
described with reference to and as illustrated in the accompanying drawings.

Documents

Application Documents

# Name Date
1 724-del-2007-abstract.pdf 2011-08-21
1 724-del-2007-form-3.pdf 2011-08-21
2 724-del-2007-claims.pdf 2011-08-21
2 724-del-2007-form-2.pdf 2011-08-21
3 724-del-2007-correspondence-others.pdf 2011-08-21
3 724-del-2007-form-1.pdf 2011-08-21
4 724-del-2007-description (complete).pdf 2011-08-21
4 724-del-2007-drawings.pdf 2011-08-21
5 724-del-2007-description (complete).pdf 2011-08-21
5 724-del-2007-drawings.pdf 2011-08-21
6 724-del-2007-correspondence-others.pdf 2011-08-21
6 724-del-2007-form-1.pdf 2011-08-21
7 724-del-2007-claims.pdf 2011-08-21
7 724-del-2007-form-2.pdf 2011-08-21
8 724-del-2007-abstract.pdf 2011-08-21
8 724-del-2007-form-3.pdf 2011-08-21