DESC:TECHNICAL FIELD
[0001] The present disclosure relates generally to a technique of an efficient way of pulsing gate terminal voltage of radio frequency (RF) power amplifiers to realize pulsed mode of operation.

BACKGROUND
[0002] Background description includes information that may be useful in understanding the present invention. It is not an admission that any of the information provided herein is prior art or relevant to the presently claimed invention, or that any publication specifically or implicitly referenced is prior art.
[0003] A radio frequency (hereinafter interchangeably referred to as “RF”) power amplifier is a type of electronic amplifier that converts a low-power radio-frequency signal into a higher power signal.
[0004] Transmitters play an important integral part in the amplification of RF signals which are then emitted as electromagnetic waves into free space for target detection. Among few components used in the transmitters, RF power amplifiers consume a significant share of the system power. Hence, it is essential to efficiently pulse the RF power amplifier in order to curtail the power consumption.
[0005] Therefore, there is need in the art to provide a simple and efficient solution which can obviate the above mentioned problem.

OBJECTS OF THE PRESENT DISCLOSURE
[0006] Some of the objects of the present disclosure, which at least one embodiment herein satisfies are as listed herein below.
[0007] It is an object of the present disclosure to provide a gate pulsing electrical circuitry for use with an RF power amplifier.
[0008] It is an object of the present disclosure to provide a simple and effective gate pulsing electrical circuitry for use with an RF power amplifier.
[0009] It is an object of the present disclosure to provide a reliable and efficient gate pulsing electrical circuitry for use with an RF power amplifier.
[0010] It is an object of the present disclosure to provide a robust gate pulsing electrical circuitry for use with an RF power amplifier.

SUMMARY
[0011] The present disclosure relates generally to a technique of an efficient way of pulsing gate terminal voltage of radio frequency (RF) power amplifiers to realize pulsed mode of operation.
[0012] An aspect of the present disclosure pertains to an electrical circuitry. The electrical circuitry includes a first voltage regulation circuit, a second voltage regulation circuit, a first charge storage capacitor, a second charge storage capacitor, a third capacitor, a voltage switch, and a power amplifier. The first voltage regulation circuit is configured to regulate pinch-off voltage with respect to a gate terminal of a power amplifier. The second voltage regulation circuit is configured to regulate gate bias voltage with respect to the gate terminal of the RF power amplifier. The first charge storage capacitor is connected at an output terminal of the first voltage regulation circuit. The second charge storage capacitor is connected at an output of the second voltage regulation circuit. The voltage switch is configured to provide a pulsed voltage to the gate terminal associated with the RF power amplifier. The third capacitor is connected at an input terminal of the RF power amplifier.
[0013] In an aspect, capacitance associated with the third capacitor is lower than the capacitance associated with the first charge storage capacitor and the second charge storage capacitor.
[0014] In an aspect, the RF power amplifier is configured to be in an on state and off state with the two states being based on the regulated pinch-off voltage from the first voltage regulation circuit and the regulated gate bias voltage from the second voltage regulation circuit.
[0015] In an aspect, the power amplifier is a radio frequency (RF) power amplifier.
[0016] In an aspect, the circuitry further comprising a fourth charge storage capacitor disposed proximate a drain terminal of the power amplifier.
[0017] In an aspect, the first and the second voltage regulation circuits are based on a linear type voltage regulation circuit.
[0018] In an aspect, the voltage switch is an analog voltage switch.
[0019] In an aspect, the RF power amplifier is a high power amplifier based on depletion-mode amplifying devices.
[0020] In an aspect, the depletion-mode amplifying devices is a Gallium Arsenide (GaAs), or a Gallium Nitride (GaN) based depletion-mode amplifying devices.
[0021] In an aspect, the present disclosure disclosed a device technique of gate pulsing of RF solid state high power amplifier (PA), that are based on a voltage regulation circuit to provide gate voltages, an analog switch/analog voltage switch to switch between bias and pinch-off voltages, and charge storage capacitors to source gate current during switching.
[0022] In an embodiment, the voltage regulation circuit can include a linear voltage regulation circuit to provide gate bias voltage.
[0023] In an embodiment, the voltage regulation circuit can include a linear voltage regulation circuit to provide gate pinch-off voltage.
[0024] In an embodiment, the analog voltage switch may have low series impedance and switching time.
[0025] In an embodiment, the analog voltage switch can be placed between the voltage regulation circuits and the gate of the power amplifier.
[0026] In an embodiment, the high power amplifier can be depletion-mode amplifying device based on Gallium Arsenide (GaAs) and Gallium Nitride (GaN) technology.
[0027] In an embodiment, the charge storage capacitors can includes combination of high and low value of capacitors.
[0028] In an embodiment, a high value of shunt capacitors to ground can be placed between voltage regulation circuits and analog voltage switch.
[0029] In an embodiment, a low value of shunt capacitors to ground can be placed between analog voltage switch and gate of the power amplifier.
[0030] Various objects, features, aspects and advantages of the inventive subject matter will become more apparent from the following detailed description of preferred embodiments, along with the accompanying drawing figures in which like numerals represent like components.

BRIEF DESCRIPTION OF THE DRAWINGS
[0031] The accompanying drawings are included to provide a further understanding of the present disclosure, and are incorporated in and constitute a part of this specification. The drawings illustrate exemplary embodiments of the present disclosure and, together with the description, serve to explain the principles of the present disclosure. The diagrams are for illustration only, which thus is not a limitation of the present disclosure.
[0032] FIG. 1 shows an exemplary block diagram of an electrical circuit that can perform the gate pulsing technique, in accordance with an embodiment of the present disclosure.
[0033] FIG. 2 illustrates an exemplary block diagram of regulation circuit portion, in accordance with an embodiment of the present disclosure.
[0034] FIG. 3 illustrates an exemplary block diagram of a voltage switch and power amplifier connection, in accordance with an embodiment of the present disclosure.
[0035] FIG. 4 illustrates an exemplary block diagram of Gate and Drain terminals of power amplifier connection, in accordance with an embodiment of the present disclosure.
[0036] FIG. 5 illustrates an exemplary multiple power amplifier pulsing approach, in accordance with an embodiment of the present disclosure.
[0037] FIG. 6 illustrates an exemplary rising edge waveform, in accordance with an embodiment of the present disclosure.
[0038] FIG. 7 illustrates an exemplary rise time measurement in waveform, in accordance with an embodiment of the present disclosure.
[0039] FIG. 8 illustrates an exemplary falling edge waveform, in accordance with an embodiment of the present disclosure.
[0040] FIG. 9 illustrates an exemplary fall time measurement in waveform, in accordance with an embodiment of the present disclosure.
[0041] Persons skilled in the art will appreciate that elements in the figures are illustrated for simplicity and clarity and may have not been drawn to scale. For example, the dimensions of some of the elements in the figure may be exaggerated relative to other elements to help to improve understanding of various exemplary embodiments of the present disclosure. Throughout the drawings, it should be noted that like reference numbers are used to depict the same or similar elements, features, and structures.

DETAILED DESCRIPTION
[0042] In the following description, numerous specific details are set forth in order to provide a thorough understanding of embodiments of the present invention. It will be apparent to one skilled in the art that embodiments of the present invention may be practiced without some of these specific details.
[0043] If the specification states a component or feature “may”, “can”, “could”, or “might” be included or have a characteristic, that particular component or feature is not required to be included or have the characteristic.
[0044] As used in the description herein and throughout the claims that follow, the meaning of “a,” “an,” and “the” includes plural reference unless the context clearly dictates otherwise. Also, as used in the description herein, the meaning of “in” includes “in” and “on” unless the context clearly dictates otherwise.
[0045] The recitation of ranges of values herein is merely intended to serve as a shorthand method of referring individually to each separate value falling within the range. Unless otherwise indicated herein, each individual value is incorporated into the specification as if it were individually recited herein. All methods described herein can be performed in any suitable order unless otherwise indicated herein or otherwise clearly contradicted by context. The use of any and all examples, or exemplary language (e.g. “such as”) provided with respect to certain embodiments herein is intended merely to better illuminate the invention and does not pose a limitation on the scope of the invention otherwise claimed. No language in the specification should be construed as indicating any non-claimed element essential to the practice of the invention.
[0046] Groupings of alternative elements or embodiments of the invention disclosed herein are not to be construed as limitations. Each group member can be referred to and claimed individually or in any combination with other members of the group or other elements found herein. One or more members of a group can be included in, or deleted from, a group for reasons of convenience and/or patentability. When any such inclusion or deletion occurs, the specification is herein deemed to contain the group as modified thus fulfilling the written description of all groups used in the appended claims.
[0047] Exemplary embodiments will now be described more fully hereinafter with reference to the accompanying drawings, in which exemplary embodiments are shown. This invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. These embodiments are provided so that this disclosure will be thorough and complete and will fully convey the scope of the invention to those of ordinary skill in the art. Moreover, all statements herein reciting embodiments of the invention, as well as specific examples thereof, are intended to encompass both structural and functional equivalents thereof. Additionally, it is intended that such equivalents include both currently known equivalents as well as equivalents developed in the future (i.e., any elements developed that perform the same function, regardless of structure).
[0048] Embodiments explained herein relate to a device and technique for pulsing the gate terminal voltage of RF power amplifiers to realize pulsed mode of operation. The proposed device and technique can be realized in one of the transmitter modules that include multiple power amplifiers which need to be efficiently pulsed.
[0049] An aspect of the present disclosure pertains to an electrical circuitry. The electrical circuitry includes a first voltage regulation circuit, a second voltage regulation circuit, a first charge storage capacitor, a second charge storage capacitor, a third capacitor, a voltage switch, and a power amplifier. The first voltage regulation circuit is configured to regulate pinch-off voltage with respect to a gate terminal of the power amplifier. The second voltage regulation circuit is configured to regulate gate bias voltage with respect to the gate terminal of the RF power amplifier. The first charge storage capacitor is connected at an output terminal of the first voltage regulation circuit. The second charge storage capacitor is connected at an output of the second voltage regulation circuit. The voltage switch is configured to provide a pulsed voltage to the gate terminal associated with the RF power amplifier. The third capacitor is connected at an input terminal of the RF power amplifier.
[0050] In an aspect, capacitance associated with the third capacitor is lower than the capacitance associated with the first charge storage capacitor and the second charge storage capacitor.
[0051] In an aspect, the RF power amplifier is configured to be in an on state and off state with the two states being based on the regulated pinch-off voltage from the first voltage regulation circuit and the regulated gate bias voltage from the second voltage regulation circuit.
[0052] In an aspect, the power amplifier is a radio frequency (RF) power amplifier.
[0053] In an aspect, the circuitry further comprising a fourth charge storage capacitor disposed proximate a drain terminal of the power amplifier.
[0054] In an aspect, the first and the second voltage regulation circuits are based on a linear type voltage regulation circuit.
[0055] In an aspect, the voltage switch is an analog voltage switch.
[0056] In an aspect, the RF power amplifier is a high power amplifier based on depletion-mode amplifying devices.
[0057] In an aspect, the depletion-mode amplifying devices is a Gallium Arsenide (GaAs), or a Gallium Nitride (GaN) based depletion-mode amplifying devices.
[0058] In an aspect, the present disclosure disclosed a device technique of gate pulsing of RF solid state high power amplifier (PA), that are based on a voltage regulation circuit to provide gate voltages, an analog switch/analog voltage switch to switch between bias and pinch-off voltages, and charge storage capacitors to source gate current during switching.
[0059] In an embodiment, the voltage regulation circuit can include a linear voltage regulation circuit to provide gate bias voltage.
[0060] In an embodiment, the voltage regulation circuit can include a linear voltage regulation circuit to provide gate pinch-off voltage.
[0061] In an embodiment, the analog voltage switch may have low series impedance and switching time.
[0062] In an embodiment, the analog voltage switch can be placed between the voltage regulation circuits and the gate of the power amplifier.
[0063] In an embodiment, the high power amplifier can be depletion-mode amplifying device based on Gallium Arsenide (GaAs) and Gallium Nitride (GaN) technology.
[0064] In an embodiment, the charge storage capacitors can includes combination of high and low value of capacitors.
[0065] In an embodiment, a high value of shunt capacitors to ground can be placed between voltage regulation circuits and analog voltage switch.
[0066] In an embodiment, a low value of shunt capacitors to ground can be placed between analog voltage switch and gate of the power amplifier.
[0067] FIG. 1 shows an exemplary block diagram of an electrical circuit that can perform the gate pulsing technique, in accordance with an embodiment of the present disclosure. The electrical circuit (not shown, but can be appreciated by those skilled in the art) can include a first voltage regulation circuit 101, a second voltage regulation circuit 102, a voltage switch 103, and a power amplifier 104. The power amplifier 104 is a radio frequency (RF) power amplifier and can be a high power amplifier known in the art. The RF power amplifier 104 can include respective components known in the art such as gate terminal, source terminal, and drain terminal (not shown, but can be appreciated by those skilled in the art), while also including known components such as input terminal and output terminal. It is also envisioned that those skilled in the art can appreciate that these components can further include their respective sub-components and aspects such as respective voltages, electric potential, properties, further sub-aspects, and the like with regards to their respective conditions and states.
[0068] In some embodiments, the power amplifier 104 can include amplifiers other than those associated with RF as can be appreciated by those skilled in the art, without deviating from the spirit and scope of the current disclosure.
[0069] As shown in FIG. 1, an RF power amplifier 104 can be turned to an on state and an off state fast by pulsing its gate terminal (of the power amplifier 104) with both the gate pinch-off and the gate bias voltages being regulated using voltage regulation circuits (first voltage regulation circuit 101 and second voltage regulation circuit 102 respectively). This can allow the supply applied to the gate terminal to be free of voltage ripples capable of causing damage to the gate terminal of the power amplifier 104. These regulated voltages ensure that the fluctuations in the output of power amplifier 104 are minimized as the amplifier output is highly sensitive to minuscule changes in gate voltage of power amplifier 104. Voltage output of 101 and 102 are connected to 103 which gives the pulsed voltage waveform required at the gate terminal of the power amplifier 104.
[0070] FIG. 2 illustrates an exemplary block diagram of a regulation circuit (can include both the first regulation circuit 101 and the second regulation circuit 102; shown as 201 and 202 respectively) portion while FIG. 3 illustrates an exemplary block diagram of a voltage switch and power amplifier connection, in accordance with embodiments of the present disclosure. As shown in FIG. 2, the proposed electrical circuitry can include the placement of charge storage capacitors (first charge storage capacitor 204 and second charge storage capacitor 205) at respective output terminals of 201 and 202. High capacitors are recommended at regulation circuit output for its operation. But this high value of capacitances increases the rise and fall time if offered directly at the gate terminal of power amplifier 104. In some embodiments, the charge storage capacitors can be a high charge storage capacitor (while the term “high” is relative, it is to be appreciated that the term “high” should be read in conjunction with other capacitors known in the art; in particular, it is to be understood with regards to a charge storage capacitor herein mentioned) while in other embodiments, the charge storage capacitor can be based on other similar functional capacitors known in the art.
[0071] Referring now to FIG. 3, the proposed circuitry incorporates the voltage switch 301 (see 103 in FIG. 1, and herein used interchangeably) which is controlled by a digital logic signal to switch between outputs of 201 and 202. The digital logic signal can include an LVTTL signal as can be appreciated. High values of recommended capacitance (204 and 205) are provided to the input terminals of voltage switch 301 which in turn are connected to outputs of 201 and 202. Whereas low value of recommended capacitance (i.e. a third capacitor 303) to power amplifier 302 (see 104 in FIG. 1, and herein used interchangeably) is connected to the output terminal of voltage switch 301 which is further connected to the gate terminal of power amplifier 302. 303 ensures that the rise and fall time of the gate pulse is lower. It also ensures that the voltage across gate terminal of power amplifier 302 is maintained during the transition of voltage switch 301 from pinch-off to operating bias voltages as it first breaks the contact between 201 and 202 output and the gate terminal. power amplifier 302 gets damaged if the gate terminal is left open while the drain terminal supply is powered ON. The proposed technique eliminates the issue of switching high voltages and currents switching involved in drain pulsing circuits. Switching high voltages requires high breakdown Vds (Drain to Source) MOSFETs and with high Ids current handling capability.
[0072] In conventional gate pulsing circuits, resistor potential dividers are used to derive pinch-off and bias gate voltages. In order to reduce the current drawn from supply, resistor values can be higher which may degrade the rise and fall time of the gate pulse. On the other hand, lower values of resistors draw higher current degrading the efficiency of the module. In the proposed technique, rise and fall time are limited only by voltage switch 301 impedance which is of the order of few ohms which is quite low. Moreover in potential divider approach, I²R losses on the resistors are dissipated as heat and it accounts for heavier metal housings for better thermal management resulting in increased cost and size.
[0073] FIG. 4 illustrates an exemplary block diagram of Gate and Drain terminals of power amplifier connection, in accordance with an embodiment of the present disclosure. Referring to FIG. 4, charge storage capacitors shown therein can be kept as close as possible to the drain terminal of the power amplifier 401 (see amplifiers 104, 302 in other FIGs. 1, 3 provided herein) as the parasitic inductance offered by the long traces is minimal. These parasitic trace inductances restrict the rate of change in current. This manifests as overshoots in the drain pulses which can distort the RF output waveform and potentially damage the power amplifier if the overshoot levels exceed the operating margins. In the proposed electrical circuitry, by virtue of gate pulsing, a fourth charge storage capacitor 403 can be kept closer to the drain terminal of power amplifier 401. Absence of the drain pulsing circuit components enables to have larger copper area for the drain supply trace, further reducing the trace inductance. Moreover in the proposed technique, by virtue of low current, overshoots on the gate pulses are minimal. voltage switch 301 impedance ensures damped response resulting in curbing voltage overshoots.
[0074] The proposed circuitry facilitates the use of gate pulsing rather than drain pulsing in device or systems which contain higher number of amplifiers. FIG. 5 illustrates an exemplary multiple power amplifier pulsing approach, in accordance with an embodiment of the present disclosure. FIG. 5 depicts 502(1) through 502(N) that can be gate pulsed simultaneously. 501 incorporates two voltage regulation circuit which provides pinch-off and bias voltage for the power amplifier. N in FIG. 5 denotes the number of amplifier chains in the module which dictates the choice of voltage regulation circuit required depending on the collective gate currents while 502 consists of voltage switch and power amplifier. This allows a lower cost and size of the module.
[0075] In some embodiments, the proposed circuitry as shown in FIG. 5 can be implemented in a module which consists of multiple channels or “n” number of channels as can be appreciated. Every channel can accommodate one or more power amplifier each. In some embodiments, the proposed circuitry can be implemented in multiple channels based on the scale of a given associated project. In some embodiments, the number of channels can be four.
[0076] FIG. 6 illustrates an exemplary rising edge waveform while FIG. 7 illustrates an exemplary rise time measurement in waveform, in accordance with an embodiment of the present disclosure. FIG. 8 illustrates an exemplary falling edge waveform while FIG. 9 illustrates an exemplary fall time measurement in waveform, in accordance with an embodiment of the present disclosure. In FIGs. 7 to 9, trace 1 depicts the gate control TTL logic provided at the voltage switch control terminal and trace 2 indicates the voltage levels at the gate terminal of the power amplifier. It can be inferred from the FIGs. 6 to 9 that the overall switching ON and switching OFF of the power amplifier through its gate voltage terminal is better than 100ns which includes switching time delay of the voltage switch and rise/fall time of the gate voltage.
[0077] For the purposes of the present disclosure, it is to be appreciated that even though the capacitors 204, 205, and 403 are charge storage capacitors, in some embodiments, the capacitors 204, 205, and 403 can be decoupling capacitors. Therefore, aspects and functionalities of decoupling capacitors are intended to covered by the present disclosure without deviating from the spirit and the scope of the present disclosure. Thus, in some embodiments, the third capacitor 303 can also be a charge storage capacitor, or a decoupling capacitor.
[0078] In an embodiment, the proposed circuitry facilitates gate pulsing using voltage regulated DC supplies, appropriate placement of charge storage capacitors, fast rise and fall time of the gate pulse, low risk of power amplifier failure in using break before make switches, eliminates high voltages and currents switching in drain pulsing, simpler solution as compared to drain pulsing circuits, minimal RF overshoot in Power Amplifier output as compared to drain pulsing, and reduce the distance from charge storage device to the drain of power amplifier.
[0079] The present disclosure provides an efficient device and method for pulsing gate terminal voltage of RF high power solid state amplifier (PA) to realize pulsed mode of operation of the RF power amplifiers. The method includes switching between two regulation circuits using an analog switch and careful placement of charge storage capacitors on supplies and gate terminals of the RF power amplifiers.
[0080] Thus, it will be appreciated by those of ordinary skill in the art that the diagrams, schematics, illustrations, and the like represent conceptual views or processes illustrating systems and methods embodying this invention. The functions of the various elements shown in the figures may be provided through the use of dedicated hardware as well as hardware capable of executing associated software. Similarly, any switches shown in the figures are conceptual only. Their function may be carried out through the operation of program logic, through dedicated logic, through the interaction of program control and dedicated logic, or even manually, the particular technique being selectable by the entity implementing this invention. Those of ordinary skill in the art further understand that the exemplary hardware, software, processes, methods, and/or operating systems described herein are for illustrative purposes and, thus, are not intended to be limited to any particular named.
[0081] While embodiments of the present invention have been illustrated and described, it will be clear that the invention is not limited to these embodiments only. Numerous modifications, changes, variations, substitutions, and equivalents will be apparent to those skilled in the art, without departing from the spirit and scope of the invention, as described in the claim.
[0082] In the foregoing description, numerous details are set forth. It will be apparent, however, to one of ordinary skill in the art having the benefit of this disclosure, that the present invention may be practiced without these specific details. In some instances, well-known structures and devices are shown in block diagram form, rather than in detail, to avoid obscuring the present invention.
[0083] It should be apparent to those skilled in the art that many more modifications besides those already described are possible without departing from the inventive concepts herein. The inventive subject matter, therefore, is not to be restricted except in the spirit of the appended claims. Moreover, in interpreting both the specification and the claims, all terms should be interpreted in the broadest possible manner consistent with the context. In particular, the terms “comprises” and “comprising” should be interpreted as referring to elements, components, or steps in a non-exclusive manner, indicating that the referenced elements, components, or steps may be present, or utilized, or combined with other elements, components, or steps that are not expressly referenced. Where the specification claims refers to at least one of something selected from the group consisting of A, B, C …. N, the text should be interpreted as requiring only one element from the group, not A plus N, or B plus N, etc.
[0084] While the foregoing describes various embodiments of the invention, other and further embodiments of the invention may be devised without departing from the basic scope thereof. The scope of the invention is determined by the claims that follow. The invention is not limited to the described embodiments, versions or examples, which are included to enable a person having ordinary skill in the art to make and use the invention when combined with information and knowledge available to the person having ordinary skill in the art.

ADVANTAGES OF THE PRESENT DISCLOSURE
[0085] The present disclosure provides a gate pulsing electrical circuitry for use with an RF power amplifier.
[0086] The present disclosure provides a simple and effective gate pulsing electrical circuitry for use with an RF power amplifier.
[0087] The present disclosure provides a reliable and efficient gate pulsing electrical circuitry for use with an RF power amplifier.
[0088] The present disclosure provides a robust gate pulsing electrical circuitry for use with an RF power amplifier.
,CLAIMS:1. An electrical circuitry comprising:
a first voltage regulation circuit configured to regulate pinch-off voltage with respect to a gate terminal of a power amplifier;
a second voltage regulation circuit configured to regulate gate bias voltage with respect to the gate terminal of the RF power amplifier;
a first charge storage capacitor connected at an output terminal of the first voltage regulation circuit;
a second charge storage capacitor connected at an output of the second voltage regulation circuit;
a voltage switch configured to provide a pulsed voltage to the gate terminal associated with the RF power amplifier; and
a third capacitor connected at an input terminal of the RF power amplifier;
wherein capacitance associated with the third capacitor is lower than the capacitance associated with the first charge storage capacitor and the second charge storage capacitor; and
wherein the RF power amplifier is configured to be in an on state and off state with the two states being based on the regulated pinch-off voltage from the first voltage regulation circuit and the regulated gate bias voltage from the second voltage regulation circuit.
2. The electrical circuitry as claimed in claim 1, wherein the power amplifier is a radio frequency (RF) power amplifier.
3. The electrical circuitry as claimed in claim 1, wherein the circuitry further comprising a fourth charge storage capacitor disposed proximate a drain terminal of the power amplifier.
4. The electrical circuitry as claimed in claim 1, wherein the first and the second voltage regulation circuits are based on a linear type voltage regulation circuit.
5. The electrical circuitry as claimed in claim 1, wherein the voltage switch is an analog voltage switch.
6. The electrical circuitry as claimed in claim 2, wherein the RF power amplifier is a high power amplifier based on depletion-mode amplifying devices.
7. The electrical circuitry as claimed in claim 6, wherein the depletion-mode amplifying devices is a Gallium Arsenide (GaAs), or a Gallium Nitride (GaN) based depletion-mode amplifying devices.