NOIXN3ANI 3HX JO HHflXVN
aHx saanosaa A-ravinDixavd NoixvDMoads OML&OTICM HHX

WATCHDOG TIMER WITH AUTO INITIALIZER AND POWER-ON RESET
A) Technical field
[0001] The embodiments herein generally relate to hardware reset system for computer processors or for an embedded system and more particularly it relates to a watchdog timer used to reset the system in the event of an anomaly.
B) Background
[0002] Embedded systems often reside in machines that are expected to run continuously for years without errors. In case if any error occurs the recovery from errors may be achieved with techniques such as a watchdog timer that resets the computer. Most embedded systems need to be self-reliant. It is usually not possible to wait for someone to reboot them if the software hangs. Some embedded designs are simply not accessible to human operators. If their software ever hangs, such systems are permanendy disabled. The speed with which human operators reset the system would be too slow to meet the requirements. For those embedded systems that cannot be constantly monitored by human, watchdog timers are used.
[0003] A watchdog timer (WDT) is a device that is used to restart a computer or an embedded system after certain time during which a software program or application fails or

stops responding. The working principle of the watchdog timer is based on a counter, which counts down from some initial value to zero at a constant speed. If the counter reaches zero before the computer recovers, a signal is sent to the designated circuits to perform the reset action. A watchdog mechanism requires careful consideration of both software and hardware. It also requires careful consideration of what action to take when the failure is detected.
[0004] Normally the WDT continuously receives tick-signals from a processor to find out weather the computer or an embedded system is working properly. The function of the watchdog timer is to reset the system in the event of an anomaly. The causes for the anomaly could range from software problems to clock related problems in hardware. Some of them are: a logical fallacy resulting in the execution of an infinite loop; another possibility is that an unusual number of interrupts arrives during one pass of the loop. Any extra time spent in ISRs is time not spent executing the main loop; When multitasking kernels are used, deadlocks can occur. For example, a group of tasks might get stuck waiting on each other and some external signal that one of them needs, leaving the whole set of tasks hung indefinitely.
[0005] The watchdog (WD) timer is implemented using monostable multivibrator circuit. The processor keeps triggering the watchdog timer after every major cycle under normal operating conditions. However in the event of an anomaly the processor stops triggering the watchdog timer. The watchdog timer waits for certain duration for the processor trigger,

after which it resets the processor for certain duration. The processor resets and starts triggering the watchdog. Most of the embedded systems have shorter major cycle times (of the order of 20ms). However post-reset, the software initialization takes a longer duration than the normal cycle operation. This can be anywhere from a few hundreds of milli-seconds to a few seconds. If the WD function is not disabled during this period, then the watchdog keeps resetting the processor during initialization and does not allow the processor to execute the major cycle software.
[0006] The known prior art uses watchdog timer to reset the system in the event of anomaly. It includes method of monitoring the functionality of the processor. It comprises a set of timer, receiving at least one acknowledge signal from processor or software module. It includes resetting processor and restarting timer based on acknowledgement from the timer. It generates a reset signal upon the different conditions met by the timers. Some other available options includes a watchdog timer circuit which performs both the power-up initialization and program resetting function to an associated microprocessor utilizing a single astable multivibrator circuit with a single pair of complementary transistors and a single capacitor to affect timing and regenerative feedback between the transistors.
[0007] The currently available options do not provide individual setting of watchdog trigger duration and processor reset pulse duration, which is a must in critical processor based systems. In addition most of the available designs do not work over a wide temperature and voltage range.

[0008] Hence there is a need to develop a system for independent setting of watchdog trigger duration and processor reset pulse duration. There is a further need to a watchdog timer circuit that can be used over a wide range of temperature and wide supply range.
C) Object of the invention
[0009] An object of the embodiment is to provide a watchdog timer with auto initializer.
[0010] Another object of the embodiment is to provide a watchdog timer that is automatically disabled until the software initialization is complete due to unavailability of trigger pulse by software.
[0011] Another object of the embodiment is to provide a watchdog timer with power-on reset to the processor.
[0012] Yet another objective of the embodiment is to provide a watchdog timer in which watchdog trigger duration and processor reset pulse duration can be set independently.
[0013] Yet another objective of the embodiment is to provide a watchdog timer that can be used over a wide temperature range of -550C to +1250C

[0014] Yet another objective of the embodiment is to provide a watchdog timer that can be used over a wide supply range of +3V to + 15V.
D) Summary
[0015] The watchdog timer is implemented using monostable multivibrator circuit. The processor keeps triggering the watchdog timer after every major cycle under normal operating conditions. However in the event of an anomaly the processor stops triggering the watchdog timer. The watchdog timer waits for certain duration (20 ms) for the processor trigger, after which it resets the processor for certain duration (200ms). The processor resets and starts triggering the watchdog. Most of the embedded systems have shorter major cycle times (of the order of 20ms). However post-reset, the software initialization takes a longer duration than the normal cycle operation. This can be anywhere from a few hundreds of milli-seconds to a few seconds. If the WD function is not disabled during this period, then the watchdog keeps resetting the processor during initialization. The present invention has this feature is inbuilt in the design under consideration as the watchdog is automatically disabled until the software initialization is complete due to unavailability of trigger pulse. In addition to auto initialization, the circuit supports and provides power-on reset pulse to the processor. This circuit can be used over a wide temperature of -550C to +1250C, and wide supply range of +3V to +15V. Different watchdog pulse times and power-on time can be set by changing resistor and capacitor.

[0016] In accordance with the current invention, watchdog tinier circuit consists of two monostable multivibrators. First monostable multivibrator is triggered by software on the rising edge and second monostable multivibrator is triggered by the falling edge of first multivibrator. First multivibrator decides the duration of the watchdog pulse, and second multivibrator decides the duration of the processor reset pulse. Both active high and active low reset signals are available to be connected to the processor. The circuit gets automatically disabled during software initialization, and also provides processor reset on power-on with the help of power-on circuit.
[0017] The watchdog timer circuit uses two D-flip-flop's (DFF) configured as monostable multivibrators (monoshot) within the single chip. First monoshot is configured in the retriggerable mode, the trigger being provided by the processor pin 'from uC (provided by software). The time period of the monoshot pulse is approximately set at particular value (TV) by selecting resistor and capacitor (Rl and CI) values. The software triggers first monoshot once within every predefined period of time (Ts). The output of first monoshot is connected to the input of second monoshot. Second monoshot is triggered by the falling edge of output of first monoshot and has a pulse width of particular value (T2) set by respective resistor and capacitor (R2 and C2). The output of second monoshot is connected to the processor reset pin.
[0018] The preset pin of second monoshot is connected to a RC powered by VCC . During the power-on stage, the capacitor C3 acts as a short circuit for a short duration depending on

the value of C3 and R3, thereby presetting second monoshot. The output of second monoshot goes high, and causes the output to be held HIGH for duration of T2 ms, after which the output goes LOW. This can be used as a power-on reset to the processor, thereby resetting the processor very first time.
[0019] These and other aspects of the embodiments herein will be better appreciated and understood when considered in conjunction with the following description and the accompanying drawings. It should be understood, however, that the following descriptions, while indicating preferred embodiments and numerous specific details thereof, are given by way of illustration and not of limitation. Many changes and modifications may be made within the scope of the embodiments herein without departing from the spirit thereof, and the embodiments herein include all such modifications.
E) Brief description of the drawings
[0020] The embodiments herein will be better understood from the following detailed description with reference to the drawings, in which:
[0021] FIG. 1 illustrates block diagram of watchdog timer.
[0022] FIG. 2 illustrates functional flowchart of watchdog timer.

[0023] FIG. 3 illustrates a single chip watchdog timer circuit.
[0024] FIG. 4 illustrates watchdog timer waveforms.
[0025] FIG. 5 illustrates waveforms corresponding to the power-on reset operation.
F) Detailed description
[0026] The embodiments herein and the various features and advantageous details thereof are explained more fully with reference to the non-limiting embodiments that are illustrated in the accompanying drawings and detailed in the following description. Descriptions of well-known components and processing techniques are omitted so as to not unnecessarily obscure the embodiments herein. The examples used herein are intended merely to facilitate an understanding of ways in which the embodiments herein may be practiced and to further enable those of skill in the art to practice the embodiments herein. Accordingly, the examples should not be construed as limiting the scope of the embodiments herein.
[0027] FIG. 1 illustrates block diagram of watchdog timer. The watchdog timer circuit consists of two monostable multivibrators 102, 104. Monostable multivibrator 102 is triggered by software on the rising edge and monostable multivibrator 104 is triggered by the falling edge of first multivibrator 102. Multivibrator 102 decides the duration of the watchdog pulse, and multivibrator 104 decides the duration of the processor reset pulse.

Both active high and active low reset signals are available to be connected to the processor. The circuit gets automatically disabled during software initialization, and also provides processor reset on power-on with the help of power-on circuit 106.
[0028] FIG. 2 illustrates functional flowchart of watchdog timer. The watchdog timer circuit (202) gets automatically disabled during software initialization (206), and also provides processor reset on power-on with the help of power-on circuit (204). The processor keeps triggering (210) the watchdog timer after every major cycle (208) under normal operating conditions. However in the event of an anomaly the processor stops triggering the watchdog timer. The watchdog timer waits for certain duration (20 ms) for the processor trigger, after which it resets the processor for certain duration (200ms). The processor resets and starts triggering the watchdog.
[0029] FIG. 3 illustrates a single chip watchdog timer circuit. The circuit uses two D-flip-flop's (DFF) configured as monostable multivibrators (monoshot) within the single chip. On the rising edge of the clock CLK (CLK, D, Q, Qn, SET, RESET are the signals corresponding to each DFF; the K in CLK is masked by RESET), the output Q goes HIGH. Whenever the output of the DFF goes HIGH the capacitor starts charging toward the HIGH voltage. After a predetermined duration set by Rl and CI values, the capacitor voltage is sufficient to reset the DFF, thereby making its output LOW.
[0030] First monoshot 102 is configured in the retriggerable mode, the trigger being

piovided by the processor pin 'from uC (software). The time period of the monoshot pulse is approximately set at particular value (Tl) by selecting Rl and CI values. According to present embodiment value of Tl has been taken as 22ms. The software triggers monoshot 102 once within every predefined period of time (Ts). According to present embodiment value of Ts has been taken as 15ms. The active LOW output of monoshot 102 Ql is connected to the 'CLIC input of monoshot 104. Monoshot 104 is triggered by the rising edge of Qln and has a pulse width of particular value (T2) set by R2 and C2. According to present embodiment value of Tl has been taken as 22ms. The output of monoshot 104 named RESET (Active HIGH) or RESETn (Active LOW) are connected to the processor reset pin (Some processors need "Active HIGH" and some need "Active LOW" reset signals). The time T2 ms can be set to around 200ms as most processors require a minimum reset pulse width of 200ms. According to present embodiment value of T2 has been taken as 220ms.
[0031] The preset pin of monoshot 104 (pin-10) is connected to a RC (R3 and C3) powered by VCC (range 3V to 15V). During the power-on stage, the capacitor C3 acts as a short circuit for a short duration depending on the value of C3 and R3, thereby presetting monoshot 104. The output of monoshot 104 goes high, and causes the output to be held HIGH for duration of T2 ms, after which the output goes LOW. This can be used as a power-on reset to the processor, thereby resetting the processor very first time. Subsequent to power-on condition, this circuit does not produce any reset pulse. This circuit (R3 and C3) works only when power to the circuit is switch OFF and ON, and for very first time

during power-up.
[0032] Most of the embedded systems have shorter major cycle times (of the order of 20ms). However post-reset, the software initialization takes a longer duration than the normal cycle operation. This can be anywhere from a few hundreds of milliseconds to a few seconds. If the watchdog function is not disabled during this period, then the watchdog keeps resetting the processor during initialization. This feature is inbuilt in the design under consideration as the watchdog is automatically disabled until the software initialization is complete due to unavailability of monoshot 102 trigger pulse. The watchdog circuit operation starts after receiving the first software trigger pulse, and hence does not generate any reset pulse during software initialization. This is one of the novel features of the design. The watchdog timer is automatically disabled during software initialization.
[0033] FIG. 4 illustrates watchdog timer waveforms. The software keeps triggering the monoshot 102 (shown in FIG. 1 & 3) input with a narrow pulse of around lus (during lus the pulse level is HIGH, and LOW at other times) every Ts ms. The output of monoshot 102 (shown in FIG. 1 & 3) is held high as long as the retriggering takes place. During this period, the output of monoshot 104 (shown in FIG. 1 & 3) is held low. The watchdog operation begins when the processor fails to trigger monoshot (shown in FIG. 1 & 3). During this period monoshot (shown in FIG. 1 & 3) waits for a period of Tl ms, and asserts its output LOW. The falling edge of monoshot1 s 102 (shown in FIG. 1 & 3) output Ql (or rising edge of Qln) triggers monoshot 104 (shown in FIG. 1 & 3). Monoshot 104 (shown in

FIG. 1 & 3) output goes HIGH, waits for a period of T2 ms, and goes low, thereby resetting the processor. Once the processor resets, it keeps triggering monoshot (shown in FIG. 1 & 3) and the cycle continues till the next anomaly.
[0034] Some processors need (Active HIGH) and some need (Active LOW) reset signals. Hence the circuit under consideration provides both Active HIGH and Active LOW signals, one of which can be connected to the processor.
[0035] FIG. 5 illustrates waveforms corresponding to the power-on reset operation. The preset pin of monoshot 104 (pin-10) is connected to a RC powered by VCC (range 3V to 15V). During the power-on stage, the capacitor C3 (shown in FIG. 3) acts as a short circuit for a short duration depending on the value of C3 and R3 (shown in FIG. 3), thereby presetting monoshot 104 (shown in FIG. 1 & 3). The output of monoshot 104 goes high, and causes the output to be held HIGH for duration of T2 ms, after which the output goes LOW. This can be used as a power-on reset to the processor, thereby resetting the processor very first time. The presetting occurs only during power-on and during normal operation the watchdog Timer provides the reset only in case of an anomaly.
[0036] The circuit can be used over a wide temperature of -550C to +1250C, and wide supply range of +3V to +15V.
[0037] The foregoing description of the specific embodiments will so fully reveal the general

nature of the embodiments herein that others can, by applying current knowledge, readily modify and/or adapt for various applications such specific embodiments without departing from the generic concept, and, therefore, such adaptations and modifications should and are intended to be comprehended within the meaning and range of equivalents of the disclosed embodiments. It is to be understood that the phraseology or terminology employed herein is for the purpose of description and not of limitation. Therefore, while the embodiments herein have been described in terms of preferred embodiments, those skilled in the art will recognize that the embodiments herein can be practiced with modification within the spirit and scope of the appended claims.
G) ADVANTAGES OF THE PRESENT INVENTION
[0038] Processor independent watchdog timer circuit with independent duration setting can be fine tuned for any embedded system applications requiring different watchdog duration.
[0039] Wide working voltage range from +3V to +15V and wide temperature range from -550C to +1250C enables the circuit to be used in a variety of applications ranging from aerospace to industrial designs.
[0040] The circuit consists of a few components, thus leading to lower cost, and compact packaging.

CLAIMS
What is claimed is:
1. A watchdog timer system for individual setting of watchdog trigger duration and for
resetting micro processor to an initialization point with power-on reset to the said
microprocessor, said system comprising:
two D-flip-flop's configured as monostable multivibrators within the single chip, wherein first monostable multivibrator is triggered by software on the rising edge and second monostable multivibrator is triggered by the falling edge of first multivibrator; and
a power-on circuit,
2. The system of claim 1, wherein said microprocessor keeps triggering said watchdog timer after every major cycle under normal operating conditions.
3. The system of claim 1, wherein in case of an anomaly said microprocessor stops
triggering said watchdog timer and after certain predefined duration said watchdog resets said microprocessor.

4. The system of claim 1, wherein after resetting said microprocessor said watchdog is automatically disabled until the software initialization is complete due to unavailability of software trigger pulse.
5. The system of claim 1, wherein said first multivibrator decides the duration of the watchdog pulse and is configured in the retriggerable mode.
6. The system of claim 1, wherein the time period of said multivibrator pulse is set at particular value by selecting resistor and capacitor values.
7. The system of claim 1, wherein said second multivibrator decides the duration of the processor reset pulse by selecting resistor and capacitor values.
8. The system of claim 1, wherein output of said first multivibrator is connected to the input of said second multivibrator.
9. The system of claim 1, wherein output of said second multivibrator is connected to said microprocessor reset pin.
10. The system of claim 1, wherein said power-on circuit is operatively connected to said second multivibrator.

11. The system of claim 1, wherein during the power-on stage, the capacitor of said
power-on circuit acts as a short circuit for a short duration depending on the value of
capacitor and resistor of said power-on circuit and presets said second multivibrator.
12. The system of claim 1, wherein said watchdog circuit provides both active HIGH
and active LOW reset signals to the processor.
13. The system of claim 1, wherein said watchdog circuit works over a wide range of
power supply from +3V to +15V.
14. The system of claim 1, wherein said watchdog circuit works over a wide range of
temperature from -550C to +1250C.