Description:RELATED APPLICATION This patent application is related to India Patent Application No. 201947029134, filed on 19 July 2019, entitled “WIRELESS COMMUNICATION TECHNOLOGY APPARATUSES AND METHODS”. TECHNICAL FIELD Some aspects of the present disclosure pertain to antennas and antenna structures. Some aspects of the present disclosure pertain to antennas and antenna structures for millimeter-wave communications. Some aspects of the present disclosure pertain to wireless communication devices (e.g., mobile devices and base stations) that use antennas and antenna structures for communication of wireless signals. Some aspects of the present disclosure relate to devices that operate in accordance with 5th Generation (5G) wireless systems. Some aspects of the present disclosure relate to devices that operate in accordance with the Wireless Gigabit Alliance (WiGig) (e.g., IEEE 802.11ad) protocols. BACKGROUND Physical space in mobile devices for wireless communication is usually at a premium because of the amount of functionality that is included within the form factor of such devices. Challenging issues arise, among other reasons, because of need for spatial coverage of radiated radio waves, and of maintaining signal strength as the mobile device is moved to different places, or because a user may orient the mobile device differently from time to time. This can lead to the need, in some aspects, for a large number of antennas, varying polarities, directions of radiation, varying spatial diversity of the radiated radio waves at varying time, and related needs. When designing packages that include antennas operating at millimeter wave (mmWave or mmW) frequencies, efficient use of space can help resolve such issues. The ubiquity of wireless communication has continued to raise a host of challenging issues. In particular, challenges have evolved with the advent of mobile communication systems, such as 5G communications systems due to both the wide variety of devices with different needs and the spectrum to be used. In particular, the ranges of frequency bands used in communications has increased, most recently due to the incorporation of carrier aggregation of licensed and unlicensed bands and the upcoming use of the mmWave bands. A challenge in mmWave radio front end modules (RFEMs) is providing for complete or near-complete directional coverage. Millimeter Wave systems require high antenna gain to close link budgets, and phased array antennas can be used to provide beam steering. However, the use of phased array antennas (such as an array of planar patch antennas) by themselves provide limited angular coverage. Although beam steering can help to direct energy towards the intended receiver (and reciprocally increase gain at the receiver in the direction of the intended transmitter), a simple array limits the coverage of steering angles. In addition, polarization of radio frequency (RF) signals is a major issue for mmWave. There are significant propagation differences between vertical and horizontal polarization, and in addition, use of both polarizations can be used to provide spatial diversity. Given the expected applications of this technology to mobile devices, it will become important to provide for selectable polarization in the antennas. Another issue of increasing concern is atmospheric attenuation loss. Due to the high path loss caused by atmospheric absorption and high attenuation through solid materials, massive multiple input, multiple output (MIMO) systems may be used for communication in the mmWave bands. The use of beamforming to search for unblocked directed spatial channels, and the disparity between line of sight (LOS) and non-line of sight (NLOS) communications, may complicate mmWave architecture compared to the architecture used for communication through a wireless personal area network (WPAN) or a wireless local area network (WLAN). BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 illustrates an exemplary user device according to some aspects. FIG. 1A illustrates a mmWave system, which can be used in connection with the device of FIG. 1 according to some aspects. FIG. 2 illustrates an exemplary base station radio head according to some aspects. FIG. 3A illustrates exemplary millimeter wave communication circuitry according to some aspects. FIG. 3B illustrates aspects of exemplary transmit circuitry illustrated in FIG. 3A according to some aspects. FIG. 3C illustrates aspects of exemplary transmit circuitry illustrated in FIG. 3A according to some aspects. FIG. 3D illustrates aspects of exemplary radio frequency circuitry illustrated in FIG. 3A according to some aspects. FIG. 3E illustrates aspects of exemplary receive circuitry in FIG. 3A according to some aspects. FIG. 4 illustrates exemplary useable RF circuitry in FIG. 3A according to some aspects. FIG. 5A illustrates an aspect of an exemplary radio front end module (RFEM) according to some aspects. FIG. 5B illustrates an alternate aspect of an exemplary radio front end module, according to some aspects. FIG. 6 illustrates an exemplary multi-protocol baseband processor useable in FIG. 1 or FIG. 2, according to some aspects. FIG. 7 illustrates an exemplary mixed signal baseband subsystem, according to some aspects. FIG. 8A illustrates an exemplary digital baseband subsystem, according to some aspects. FIG. 8B illustrates an alternate aspect of an exemplary baseband processing subsystem, according to some aspects. FIG. 9 illustrates an exemplary digital signal processor subsystem, according to some aspects. FIG. 10A illustrates an example of an accelerator subsystem, according to some aspects. FIG. 10B illustrates an alternate exemplary accelerator subsystem, according to some aspects. FIGS. 11A to 11E illustrate exemplary periodic radio frame structures, according to some aspects. FIGS. 12A to 12C illustrate examples of constellation designs of a single carrier modulation scheme that may be transmitted or received, according to some aspects. FIGS. 13A and 13B illustrate alternate exemplary constellation designs of a single carrier modulation scheme that may be transmitted and received, according to some aspects. FIG. 14 illustrates an exemplary system for generating multicarrier baseband signals for transmission, according to some aspects. FIG. 15 illustrates exemplary resource elements depicted in a grid form, according to some aspects. FIG. 16A, FIG. 16B, FIG. 16C, and FIG. 16D illustrate example of coding, according to some aspects. FIG. 17 illustrates a digital-to-time converter (DTC) structure in accordance with some aspects. FIG. 18 illustrates an open loop calibrated DTC architecture in accordance with some aspects. FIG. 19A illustrates time interleaving of DTCs to increase the clock frequency in accordance with some aspects; FIG. 19B illustrates clock signals of FIG. 19A in accordance with some aspects. FIG. 20 illustrates a series injection locking oscillator with pulse shaping in accordance with some aspects. FIG. 21 illustrates a method of providing a mmWave frequency signal in accordance with some aspects. FIG. 22 illustrates a receiver in accordance with some aspects. FIG. 23 illustrates a basic implementation of a feedforward equalizer (FFE) in accordance with some aspects. FIG. 24A and FIG. 24B illustrates a FFE in accordance with some aspects. FIG. 25 illustrates a method of providing analog signal equalization according to some aspects. FIGS. 26Aand 26B illustrate configurations of a reconfigurable decision feedback equalizer (DFE) in accordance with some aspects. FIGS. 27A and 27B illustrate selector/D Flipflop (DFF) combination configurations of a reconfigurable DFE in accordance with some aspects. FIG. 28 is a method of configuring a DFE in accordance with some aspects. FIG. 29 illustrates a mmWave architecture in accordance with some aspects. FIG. 30 illustrates a transmitter hybrid beamforming architecture in accordance with some aspects. FIG. 31 illustrates a simulation of communication rate in accordance with some aspects. FIG. 32 illustrates a simulation of a signal-to-noise ratio (SNR) in accordance with some aspects. FIG. 33 illustrates a method of communicating beamformed mmWave signals in accordance with some aspects. FIGS. 34A and 34B illustrate a transceiver structure in accordance with some aspects. FIGS. 35A and 35B illustrate a transceiver structure in accordance with some aspects. FIG. 36 illustrates an adaptive resolution analog-to-digital converter (ADC) power consumption in accordance with some aspects. FIG. 37 illustrates bit error rate (BER) performance in accordance with some aspects. FIG. 38 illustrates a method of communicating beamformed mmWave signals in accordance with some aspects. FIGS. 39A and 39B illustrate a transceiver structure in accordance with some aspects. FIG. 40 illustrates an array structure in accordance with some aspects. FIG. 41 illustrates a simulation of grating lobes in accordance with some aspects. FIG. 42 illustrates a simulation of optimal phase values in accordance with some aspects. FIG. 43 illustrates another simulation of optimal phase values in accordance with some aspects. FIG. 44 illustrates a process for a phase shifter in accordance with some aspects. FIG. 45 illustrates a phase value determination in accordance with some aspects. FIG. 46 illustrates a performance comparison in accordance with some aspects. FIG. 47 illustrates another performance comparison in accordance with some aspects. FIG. 48 illustrates a method of providing beam steering in a communication device in accordance with some aspects. FIGS. 49A and 49B illustrate an aspect of a charge pump in accordance with some aspects. FIG. 50 illustrates an aspect of a charge pump in accordance with some aspects. FIG. 51A illustrates a simplified scheme of an output portion of the charge pump in accordance with some aspects. FIG. 51Billustrates a timing diagram of signals of the charge pump in accordance with some aspects. FIGS. 52A to 52C illustrate the operation of the charge pump according to some aspects. FIGS. 53Ato 53Cillustrate summarization of operation of the charge pump according to some aspects. FIG. 54 illustrates a method of injecting charge in a charge pump in accordance with some aspects. FIG. 55 illustrates a receiver architecture in accordance with some aspects. FIG. 56 illustrates the filter characteristic of a receiver according to some aspects. FIG. 57 illustrates the BER performance of a receiver according to some aspects. FIG. 58 illustrates different receiver architecturesaccording to some aspects. FIG. 59 illustrates a method of compensating for interferers in a receiver in accordance with some aspects. FIGS. 60A and 60B illustrate interference in accordance with some aspects. FIG. 61 illustrates a receiver architecture in accordance with some aspects. FIG. 62 illustrates an oversampled signal in accordance with some aspects. FIGS. 63A and 63B illustrate filter characteristics of the receiver in accordance with some aspects. FIG. 64 illustrates a beamforming pattern according to some aspects. FIG. 65 illustrates a BER performance according to some aspects. FIG. 66 illustrates a method of reducing quantizer dynamic range in a receiver in accordance with some aspects. FIG. 67 illustrates an ADC system (ADCS) according to some aspects. FIGS. 68A and 68B illustrate different operation modes of an ADCS according to some aspects. FIG.69 illustrates core ADC averaging according to some aspects. FIG. 70 illustrates resolution improvement of an averaging system in accordance with some aspects. FIG. 71 illustrates a method of providing a flexible ADC architecture in accordance with some aspects. FIG. 72 illustrates a receiver architecture in accordance with some aspects. FIG. 73 illustrates a simulation of a spatial response in accordance with some aspects. FIG. 74 illustrates a simulation of BER in accordance with some aspects. FIG. 75 illustrates a simulation of interference rejection in accordance with some aspects. FIG. 76 illustrates a method of reducing quantizer dynamic range in a receiver in accordance with some aspects. FIG. 77 is a block diagram of an example of a Time-Interleaved Analog to Digital Converter (TI-ADC) architecture in accordance with some aspects that may be utilized herein and that achieves a high-speed conversion using M parallel low speed ADC channels in some aspects. FIG. 78 is a timing diagram 29100 that illustrates how all the channels operate with a same sampling frequency FS (or its inverse TS, illustrated in FIG. 78) with M uniformly spaced phases according to an example TI-ADC. FIG. 79 is a block diagram illustrating an example of a transceiver 29200 having a loopback design according to an example disclosed herein. FIG. 80 is a flowchart illustrating a process according to an example disclosed herein. FIG. 81 is a block diagram of an example TI-ADC, according to some aspects. FIG. 82 is a block diagram of an example of a TI-ADC architecture that achieves a high-speed conversion, according to some aspects. FIG. 83 is a timing diagram that illustrates how all the channels operate with a same sampling frequency FS (or its inverse TS, illustrated in FIG. 83) with M uniformly spaced phases, according to some aspects. FIG. 84 is a flowchart illustrating an example implementation of a process for applying the gain correction, according to some aspects. FIG. 85 is a graph illustrating an example of a PA characteristic curve of AM/AM (input amplitude VS. output amplitude), according to some aspects. FIG. 86 is a graph illustrating an example of a PA characteristic curve of AM/PM (input amplitude VS. output phase variation), according to some aspects. FIG. 87 is a block diagram of an example of a gain model for a portion of a phased array transmitter, according to an exemplary aspect of the present disclosure. FIG. 88 is a block diagram of an example of a switchable transceiver portion that the transmitter model described above may represent, according to an exemplary aspect of the present disclosure. FIG. 89 is essentially a replica transceiver portion of the transceiver portion illustrated in FIG. 88, but with the switches thrown in a receive configuration, according to an exemplary aspect of the present disclosure. FIGS. 90A and 90B are parts of a block diagram of an overall transceiver example that may contain a transceiver portion, according to an exemplary aspect of the present disclosure. FIG. 91 is a block diagram illustrating the phased array transceiver that is in communication with an external phased array transceiver (EPAT), according to an exemplary aspect of the present disclosure. FIG. 92 is a flowchart illustrating an example of a process that may be used by the transceiver, according to an exemplary aspect of the present disclosure. FIG. 93 is a flowchart illustrating another example of a process that may be used by the transceiver, according to an exemplary aspect of the present disclosure. FIGS. 94A and 94B are parts of a block diagram of an example of an overall distributed phased array transceiver system, according to some aspects. FIG. 95 is a block diagram of a receiver power amplifier according to some aspects. FIG. 96 is a graph that plots, for a given automatic gain control (AGC) gain setting, an EVM versus the received power according to some aspects. FIG. 97 is a graph that includes the EVM vs. receive power curve for a number of the AGC gain settings, where the AGC gain settings have degree of overlap with each other according to some aspects. FIG. 98 is a graph illustrating optimal threshold values for activating a particular AGC gain setting according to some aspects. FIG. 99 is a flowchart illustrating an example process that may be utilized to determine the optimal threshold values according to some aspects. FIG. 100 is a block schematic diagram of a radio frequency (RF) phased array system according to some aspects. FIG. 101 is a block schematic diagram illustrating another topology of a phased array radio transceiver that is referred to as a local oscillator (LO) phased array system according to some aspects. FIG. 102 is a block schematic diagram illustrating a third alternative to phased array radio transceiver design according to some aspects and is referred to as a digital phased array system. FIG. 103 is a block diagram of an example cell element of a scalable phased array radio transceiver architecture (SPARTA) array, according to some aspects. FIG. 104 is a block diagram illustrating tiled SPARTA cells according to some aspects. FIGS. 105 and 106 are pictorial diagrams of wafer dicing according to some aspects. FIG. 107 is a pictorial illustration of a combined SPARTA array that may be wafer processed and combined with an antenna array according to some aspects. FIG. 108 is a block diagram illustrating an implementation of aSPARTA cell that may be used for digital phase array tiling according to some aspects. FIG. 109 is a block diagram that illustrates LO phased array pipelining between adjacent cells in the LO phase combining mode according to some aspects. FIG. 110 is a block diagram illustrating the SPARTA cell tiling using an LO phase array and illustrating active data converter ADC according to some aspects. FIG. 111 is a block diagram that illustrates a SPARTA array in hybrid mode, where each row is tiled in an LO phase shifting and sharing a single ADC according to some aspects. FIG. 112 is a block diagram illustrating pipelining of the analog phased array combining between adjacent cells for the analog phased array combining operation mode according to some aspects. FIG. 113 is a schematic diagram illustrating components for Injection-locked (IL)-based phase modulation circuit, according to some aspects, which exploits phase shift characteristics of a conventional locked oscillator. FIG. 114 is a graph that illustrates how, as a center frequency of the oscillator is changed with respect to the locking frequency, the output phase and amplitude change, while still being locked to the injection frequency, according to some aspects. FIG. 115 is a timing graph illustrating two symbols with phases φ1 and φ2 being generated by controlling the cap-DAC with baseband modulation bits as the data input, according to some aspects. FIG. 116 is a block diagram for an IL-based phase modulation circuit with a full 360° phase modulation using a cascaded sub-harmonic injection-locked architecture with respect to the carrier frequency, according to some aspects. FIG. 117 is a combination graph that illustrates a true time delay-based beam forming in which elements one and two are being fed the same baseband data signals (“11”, “00”) at two different offsets, according to some aspects. FIG. 118 is a schematic block diagram illustrating an example architecture of a four-element phased array transmitter that implements combining harmonic IL based phase modulation with true time delay beam-forming, according to some aspects. FIG. 119 is a block diagram for an IL-based phase modulation circuit illustrating an example of an injection-locked oscillator at operating at 1/3 of the carrier frequency, according to some aspects. FIG. 120 is a block diagram for an IL-based phase modulation circuit illustrating an example of an injection-locked oscillator at operating at 1/2 of the carrier frequency, according to some aspects. FIG. 121 is a pictorial diagram that illustrates quadrature phase-shift keying (QPSK) (PAM2-wireline-based) modulation (two bits per symbol) with a graph that is a constellation map illustrating the I/Q values that are possible, according to some aspects. FIG.122 is a pictorial diagram that illustrates a 16-QAM (PAM4-wireline-based) modulation (four bits per symbol) with a graph that is a constellation map illustrating the I/Q values that are possible, according to some aspects. FIG. 123 is a pictorial diagram of a design for PAM2 (QPSK) modulation, according to some aspects. FIG. 124 is a table of data and error values provided according to some aspects. FIG. 125 is a graph illustrating use of the equation for Z and the first table, according to some aspects. FIG. 126 is a table illustrating a second idea, in which the error values are all minus one, except above the plus three values and below the minus three value, according to some aspects. FIG. 127 is a graph of the Z function using the second table, according to some aspects. FIG. 128 is a block schematic diagram of a typical baud rate CDR loop for wireline, according to some aspects. FIG. 129 is a block schematic diagram of a novel wireless CDR loop, having both an in-phase (I) and quadrature (Q) inputs, according to some aspects. FIG. 130 is a table containing various mode values that may be used for the mode in the design of FIG. 129, according to some aspects. FIG. 131A is a block schematic diagram of an example AGC circuit that may be implemented at a receiver where an amplitude of the received signal varies during the operation of the receiver, according to some aspects. FIG. 131B is a flowchart of an example AGC process that may be implemented at a receiver where an amplitude of the received signal varies during the operation of the receiver, according to some aspects. FIG. 132 is a constellation graph for quadrature encoding that illustrates quantization bins for low-resolution ADCs with b=〖log〗_2⁡(2n)bits in each of the I/Q components of a receiver signal in a single antenna receiver system, according to some aspects. FIG. 133 is a constellation graph for quadrature encoding illustrating quantization regions for a 3-bit ADC, according to some aspects. FIG. 134 is a graph illustrating conditional probability distributions, where only r_1 and r_5 are monotonically increasing and decreasing, according to some aspects. FIG. 135 is a graph illustrating the derivative of conditional probability distributions, according to some aspects. FIG. 136 is a graph illustrating an example of the estimation performance of the proposed power estimation algorithm compared to the classical average power determination, according to some aspects. FIG. 137 is a graph illustrating the latency of the novel algorithm, according to some aspects. FIG. 138 is a graph that compares the normalized mean square error (MSE), according to some aspects. FIG. 139 is a graph illustrating a mean square error (MSE) with a uniform 45° phase noise, according to some aspects. FIG. 140 is a block schematic diagram illustrating an example of a MIMO receiver with a digital processor, according to some aspects. FIG. 141 is a block diagram that illustrates an example of a beam forming circuit with N identical transceiver slices and N antenna elements, according to some aspects. FIG. 142 is a graph that plots SNDR vs. input power at the antenna in the case when the antenna array gain is held constant, according to some aspects. FIG. 143 is a graph that plots SNDR vs. input power at the antenna in the case when the antenna array gain is varied to enable gain control, according to some aspects. FIG. 144 is a graph that illustrates the radiated power and the relative current drain versus the number of active elements in the antenna array, according to some aspects. FIG. 145 is a graph that illustrates operating condition tradeoffs for Rx, according to some aspects. FIG. 146 is a graph that illustrates operating condition tradeoffs for Tx, according to some aspects. FIG. 147 is a flowchart that illustrates an example of a receive process that may be used, according to some aspects. FIG. 148 is a flowchart that illustrates an example of a transmit process that may be used, according to some aspects. FIG. 149 is a schematic diagram of a DAC architecture, according to some aspects. FIG. 150 is a schematic diagram of a hierarchically structured, according to one implementation of a device described herein. FIG. 151 is a combined pictorial chart diagram, including a pair of graphs illustrating co-polarization and cross-polarization when a transmit antenna and a receive antenna are aligned (i.e., parallel), according to some aspects. FIG. 152 is a combined pictorial chart diagram, including a pair of graphs illustrating co-polarization and cross-polarization when a transmit antenna and a receive antenna are misaligned (i.e., not parallel), according to some aspects. FIG. 153 is an example of a receiver using the MSFFPE design, according to some aspects. FIG. 154 is a circuit diagram illustrating a conventional summer. FIG. 155 is a circuit diagram illustrating an integrating a DFE summer, with the relevant differences highlighted, according to some aspects. FIG. 156 is a schematic diagram that provides more details about the DFE summer design, according to some aspects. FIG. 157 is a graph related to the DFE summer design illustrating the clock signal with respect to the summing amplifier out signal and the strong-arm-1 signal, according to some aspects. FIG. 158 is a schematic illustration of a block diagram of an RF device, in accordance with some demonstrative aspects. FIG. 159 is a schematic illustration of a block diagram of an RF device, in accordance with some demonstrative aspects. FIG. 160 is a schematic illustration of a bi-directional amplifier circuit, in accordance with some demonstrative aspects. FIG. 161 is a schematic illustration of a bi-directional amplifier circuit, in accordance with some demonstrative aspects. FIG. 162 is a schematic illustration of a bi-directional amplifier circuit, in accordance with some demonstrative aspects. FIG. 163 is schematic illustration of a block diagram of a transceiver including a cascode topology of an active bidirectional splitter and combiner (ABDSC), in accordance with some demonstrative aspects. FIG. 164 is a schematic illustration of a circuit diagram of a common source topology of an ABDSC, in accordance with some demonstrative aspects. FIG. 165 is a schematic illustration of a common gate topology of an ABDSC, in accordance with some demonstrative aspects. FIG. 166 is a schematic illustration of a common gate/common source (CS/CG) topology of an ABDSC, in accordance with some demonstrative aspects. FIG. 167 is a schematic illustration of a block diagram of an architecture of a transmitter, in accordance with some demonstrative aspects. FIG. 168A is a schematic illustration of an electronic circuit of a stacked-gate control amplifier, in accordance with some demonstrative aspects. FIG. 168B is a schematic illustration of an electronic circuit of a stacked-gate control amplifier, in accordance with some demonstrative aspects. FIG. 169 is a schematic illustration of a block diagram of a transmitter including a stacked-gate modulated digital Power Amplifier (PA), in accordance with some demonstrative aspects. FIGS. 170A and 170B are schematic illustrations of a dynamic realization of a multi-level high speed eye diagram, in accordance with some demonstrative aspects. FIGS. 171A and 171B depict a performance improvement graph (FIG. 171A) and a power reduction graph (FIG. 171B) corresponding to an input series switch amplifier, in accordance with some demonstrative aspects. FIG. 172A and FIG. 172B depict an amplitude resolution graph (FIG. 172A) and a power efficiency graph (FIG. 172B), corresponding to an N bit digital PA, in accordance with some demonstrative aspects. FIG. 173 depicts a drain efficiency versus power saturation of a stacked gate-controlled amplifier with a driver amplifier before it, in accordance with some demonstrative aspects. FIG. 174 is a schematic illustration of a block diagram of a transmitter, in accordance with some demonstrative aspects. FIG. 175 is a schematic illustration of a block diagram of a two-stage Doherty amplifier, which may employ a Sub-Quarter Wavelength (SQWL) balun, in accordance with some demonstrative aspects. FIG. 176 is a schematic illustration of a block diagram of a transceiver, in accordance with some demonstrative aspects. FIG. 177 is a schematic illustration of a block diagram of a transmitter, in accordance with some demonstrative aspects. FIG. 178 is a schematic illustration of a block diagram of an outphasing amplifier employing an SQWL balun as a load, in accordance with some demonstrative aspects. FIG. 179 is a schematic illustration of a block diagram of a transceiver, in accordance with some demonstrative aspects. FIG. 180 is a schematic illustration of an electronic circuit plan of phase shifting circuitry, in accordance with some demonstrative aspects. FIG. 181 is a schematic illustration of a first quadrant of a constellation-point map, in accordance with some demonstrative aspects. FIG. 182 is a schematic illustration of a graph depicting a gain variation of constellation points verses ideal phase shifted constellation points, in accordance with some demonstrative aspects. FIG. 183 is a schematic illustration of a block diagram of a transceiver, in accordance with some demonstrative aspects. FIG. 184 is a schematic illustration of a block diagram of a transceiver, in accordance with some demonstrative aspects. FIG. 185 is a schematic illustration of a quadrature Local Oscillator (LO) generator, in accordance with some demonstrative aspects. FIG. 186 is a schematic illustration of a passive quadrature LO generator, in accordance with some demonstrative aspects. FIG. 187 is a schematic illustration of a block diagram of a transmitter, in accordance with to some demonstrative aspects. FIG. 188 is a schematic illustration of a band plan of a plurality of channels corresponding to a plurality of channel bandwidths, which may be implemented in accordance with some demonstrative aspects. FIG. 189 is a schematic illustration of a graph depicting a gain response of a low band amplifier and a high band amplifier, in accordance with some demonstrative aspects. FIG. 190 is a schematic illustration of a transformer, in accordance with some demonstrative aspects. FIG. 191 is a schematic illustration of a block diagram of a wireless communication apparatus, in accordance with some demonstrative aspects. FIG. 192 is a schematic illustration of an impedance matching switch, in accordance to some demonstrative aspects. FIG. 193 is a schematic illustration of a block diagram of a transceiver, in accordance with some demonstrative aspects. FIG. 194 is a schematic illustration of a block diagram of a half-duplex transceiver, in accordance with some demonstrative aspects. FIG. 195 is a schematic illustration of a bi-directional mixer, in accordance to some demonstrative aspects. FIG. 196 Aillustrates a phased-array transceiver, according to some aspects of the present disclosure. FIG. 196B illustrates an antenna array with an original reduced angle of coverage, according to some aspects of the present disclosure. Fig. 196C illustrates a lens used in conjunction with a phased-array antenna to deflect the radiated beams and extend the angle of coverage, according to some aspects of the present disclosure. FIG. 196D illustrates a concave reflector used in conjunction with a phased-array to deflect the radiated beams and extend the angle of coverage, according to some aspects of the present disclosure. FIG. 197 illustrates a plurality of phased arrays used in conjunction with a printed reflector in a first configuration, according to some aspects of the present disclosure. FIG. 198 illustrates a plurality of phased arrays used in conjunction with a Cassegrain antenna in the first configuration, according to some aspects of the present disclosure. FIG. 199 illustrates a plurality of phased arrays used in conjunction with a printed reflector in a second configuration, according to some aspects of the present disclosure. FIG. 200 illustrates a plurality of phased arrays used in conjunction with a Cassegrain antenna in the second configuration, according to some aspects of the present disclosure. FIG. 201 illustrates a plurality of phased arrays used in conjunction with a printed reflector in a third configuration, according to some aspects of the present disclosure. FIG. 202 illustrates a plurality of phased arrays used in conjunction with a Cassegrain antenna in the third configuration, according to some aspects of the present disclosure. FIG. 203 illustrates a top view of sectorization resulting from a plurality of phased arrays used in conjunction with a reflecting antenna, according to some aspects of the present disclosure. Fig. 204 illustrates scanning in each sector of the sectorized scan regions, according to some aspects of the present disclosure. FIG. 205 illustrates a package within which antennas may be embodied within a user device, according to some aspects of the present disclosure. FIG. 206 illustrates a graph of realized gain of a 1x4 dipole array embodied in the package of FIG. 205, according to some aspects of the present disclosure. FIG. 207 illustrates radiation patterns associated with the graph of FIG. 206, according to some aspects of the present disclosure. FIG. 208 illustrates the use of an integrated circuit (IC) shield as an antenna ground plane and a reflector for a stacked patch antenna, according to some aspects of the present disclosure. FIG. 209 illustrates a side view of the monopole antenna illustrated in FIG. 208showing an unsymmetrical via feeding mechanism, according to some aspects of the present disclosure. FIGS. 210A-210C illustrate certain dimensions of the monopole antenna illustrated in FIG. 208, according to some aspects of the present disclosure. FIG. 211 illustrates patch elements of the monopole antenna of FIGS. 208and 109in an antenna array configuration with a mobile platform, according to some aspects of the present disclosure. Fig. 212A illustrates a dipole antenna with a surface mounted device (SMD) antenna that transitions the dipole antenna to a dipole with a monopole, according to some aspects of the present disclosure. FIG. 212B is a perspective view of the dipole portion of the antenna of FIG. 212A, according to some aspects of the present disclosure. FIG. 212Cillustrates a combined dipole and monopole antenna, according to some aspects of the present disclosure. FIG. 212D illustrates a perspective view of the monopole part of the antenna of FIG. 424A, according to some aspects of the present disclosure. FIG. 212E is a side view of the antenna of FIGS. 212Aand 212D, according to some aspects of the present disclosure. FIG. 213 illustrates a radiation pattern of the antenna of FIG. 212A, according to some aspects of the present disclosure. FIG. 214A illustrates an elevation cut of the radiation pattern of the antenna of FIG. 212A. FIG. 214B illustrates a radiation pattern of the antenna of FIG. 212B, according to some aspects of the present disclosure. FIG. 215A illustrates a side view of an SMD L-shaped dipole with an IC shield used as a reflector, according to some aspects of the present disclosure. FIG. 215B illustrates a perspective view of the SMD L-shaped dipole with an IC shield used as a reflector that is illustrated in FIG. 215A, according to some aspects of the present disclosure. FIG. 216 illustrates a perspective view of an array of four SMD L-shaped dipoles, according to an aspect. FIG. 217A illustrates the array of FIG. 216for vertical polarization, with the fields cancelling out, according to some aspects of the present disclosure. FIG. 217B illustrates the array of FIG. 216for vertical polarization, with the fields adding up, according to some aspects of the present disclosure. FIG. 218A illustrates the array of FIG. 216for horizontal polarization, with the fields adding up, according to some aspects of the present disclosure. FIG. 218B illustrates the array of FIG. 216for horizontal polarization, with the fields cancelling out, according to some aspects of the present disclosure. Fig. 219 illustrates a three-dimensional radiation pattern for vertical (theta) polarization, according to some aspects of the present disclosure. Fig. 220 illustrates a three-dimensional radiation pattern for horizontal (phi) polarization, according to some aspects of the present disclosure. FIG. 221 illustrates a single SMD monopole antenna, according to some aspects of the present disclosure. FIG. 222 illustrates a three-dimensional radiation pattern, according to some aspects of the present disclosure. FIG. 223 illustrates an impedance plot of a single monopole, according to some aspects of the present disclosure. FIG. 224 illustrates the return loss of a single monopole over frequency, according to some aspects of the present disclosure. FIG. 225 illustrates realized vertical polarization (θ) gain in the X-Z plane from a single monopole, according to some aspects of the present disclosure. FIG. 226 illustrates realized vertical polarization (θ) gain over frequency, at 15o above endfire, from a single monopole, according to some aspects of the present disclosure. FIG. 227 illustrates a two-element monopole and a two-element dipole array, according to some aspects of the present disclosure. FIG. 228 illustrates a three-dimensional radiation pattern of the two-dipole array of FIG. 227 at 60 GHz, according to some aspects of the present disclosure. FIG. 229 illustrates realized horizontal polarity (Ø) gain over frequency in the endfire direction from the two-dipole array of FIG. 227, according to some aspects of the present disclosure. FIG. 230 illustrates a three-dimensional radiation pattern of the two-monopole array of FIG. 227at 60 GHz, according to some aspects of the present disclosure. FIG. 231 illustrates the realized vertical polarity (θ), according to some aspects of the present disclosure. FIG. 232 illustrates a single patch, dual feed, dual polarization vertical SMD patch antenna, according to some aspects of the present disclosure. FIG. 233 illustrates a stacked patch, single feed, single polarization vertical SMD patch antenna, according to some aspects of the present disclosure. FIG. 234 illustrates a horizontal SMD patch antenna, according to some aspects of the present disclosure. FIG. 235 illustrates a vertical SMD patch antenna using a cross-hatch pattern, according to some aspects of the present disclosure. FIG. 236 illustrates an SMD spiral antenna with circular polarization, according to some aspects of the present disclosure. FIG. 237 illustrates the implementation of a spiral antenna within an SMD, according to some aspects of the present disclosure. FIG. 238 illustrates coupling radiation to directors on a chassis, according to some aspects of the present disclosure. FIG. 239A is a perspective view of an IC shield wall cut-out that forms an antenna, according to some aspects of the present disclosure. FIG. 239B is a side view of the wall cut-out that comprises the antenna illustrated in FIG. 239A, according to some aspects of the present disclosure. FIG. 239C is a perspective view of an IC shield with a wall cut-out and a top cut-out that comprise antenna elements of an antenna array, according to some aspects of the present disclosure. FIG. 239D is a perspective view of an IC shield with a first wall cut-out and a second wall cut-out that comprise antenna elements of an antenna array, according to some aspects of the present disclosure. FIG. 240A illustrates a patch antenna and RF feed line connection including a transmit/receive (TR) switch for a single polarization design, according to some aspects of the present disclosure. FIG. 240B illustrates a patch antenna and RF feed line connection including a TR switch for a dual polarization design, according to some aspects of the present disclosure. FIG. 240C illustrates a patch antenna in a single polarization design, with the antenna feed line for the RX feed line matching point slightly offset to one side as compared to the TX feed line matching point, according to some aspects of the present disclosure. FIG. 240D illustrates a patch antenna in a dual polarization design, with the antenna feed lines for the RX feed line matching point slightly offset to one side as compared to the TX feed line matching point, for both polarizations, according to some aspects of the present disclosure. FIG. 241A illustrates a single polarization implementation of a TX feed line and an RX feed line connected directly to antenna feed line matching points, according to some aspects of the present disclosure. FIG. 241B illustrates a dual polarization implementation of a horizontal polarization TX feed line and RX feed line, and a vertical polarization TX feed line and RX feed line, connected directly to antenna feed line matching points, according to some aspects of the present disclosure. FIG. 242A illustrates an IC shield, according to some aspects of the present disclosure. FIG. 242B illustrates an IC shield with a bulge, or extension, to enhance antenna gain and directivity, according to some aspects of the present disclosure. FIG. 242C illustrates the use of a folded extension with an IC shield to improve the gain of an array of dipole antenna elements, according to some aspects of the present disclosure. FIG. 242D illustrates a hole that occurs in the shield structure because of the bulge, according to some aspects of the present disclosure. FIG. 242E is a close-up perspective view of the bulge and the hole of FIG. 54D, according to some aspects of the present disclosure. FIG. 243 is top view of a combined patch antenna and dipole antenna array with a shield reflector, according to some aspects of the present disclosure. FIG. 244 is a side view of the antenna array of FIG. 455, according to some aspects of the present disclosure. FIG. 245 is a perspective view of an interposer used with a patch array to bypass large obstacles in a user device, according to some aspects of the present disclosure. FIG. 246A is a perspective view of the interposer of FIG. 457 illustrating an IC shield lid, according to some aspects of the present disclosure. FIG. 246B is a vertical view of the radiation pattern for the dipole antenna array of FIG. 458A, with the endfire direction illustrated at minus ninety (-90) degrees, according to some aspects of the present disclosure. FIG. 247 illustrates realized gain of the patch antenna array of FIGS. 245 and 246A as a function of the height of the interposer, in various directions, according to some aspects of the present disclosure. FIG. 248A is a perspective view of a combined patch and slot antenna for dual band, dual polarization operation, according to some aspects of the present disclosure. FIG. 248B is a side view of the combined patch and slot antenna of FIG. 248A, according to some aspects of the present disclosure. FIG. 249A is an exploded view of an antenna-on-a-chip (AOC), according to some aspects of the present disclosure. FIG. 249B is a bottom view of the antennas that comprise the AOC of FIG. 249A, according to some aspects of the present disclosure. FIG. 249C is a side view of the AOC of FIG. 249A, according to some aspects of the present disclosure. FIG. 250is another bottom view of the AOC of FIG. 249A, including dimensions for some aspects of the present disclosure. FIG. 251 is a radiation pattern for the antenna on a chip of FIGS. 249A-249Cand 250, according to some aspects of the present disclosure. FIG. 252A illustrates another view of an AOC for an embedded die in a package on package implementation, according to some aspects of the present disclosure. FIG. 252B is an illustration of radiation efficiency as a function of height of the silicon divided by height of the patches, according to some aspects of the present disclosure. FIG. 252C is an illustration of realized gain in dBi as a function of height of the silicon divided by height of the patches, according to some aspects of the present disclosure. FIG. 253 is another illustration of an AOC symbolically showing a chip overview and including the relationship of the antennas and the circuitry on the chip, according to some aspects of the present disclosure. FIG. 254 illustrates a block diagram of an example machine upon which any one or more of the techniques or methodologies discussed herein may be performed, according to some aspects of the present disclosure. FIG. 255 illustrates protocol functions that may be implemented in a wireless communication device, according to some aspects of the present disclosure. FIG. 256 illustrates various protocol entities that may be implemented in connection with a wireless communication device or a wireless communication system, according to some aspects of the present disclosure. FIG. 257 illustrates a medium access control (MAC) entity that may be used to implement medium access control layer functions according to some aspects of the present disclosure. FIG. 258A and FIG. 258B illustrate formats of PDUs that may be encoded and decoded by the MAC entity of FIG. 257according to some aspects of the present disclosure. FIG. 258C, FIG. 258D, and FIG. 258E illustrate various sub-headers that may be used in connection with the MAC entity of FIG. 257according to some aspects of the present disclosure. FIG. 259 illustrates functions contained within a radio link control (RLC) layer entity according to some aspects of the present disclosure. FIG. 260A illustrates a TMD PDU according to some aspects of the present disclosure. FIG.260B and FIG. 260C illustrate UMD PDUs according to some aspects of the present disclosure. FIG. 260D and FIG. 260E illustrate AMD PDUs according to some aspects of the present disclosure. FIG. 260F illustrates a STATUS PDU according to some aspects of the present disclosure. FIG. 261 illustrates aspects of functions, which may be contained within a packet data convergence protocol (PDCP) layer entity according to some aspects of the present disclosure. FIG. 262 illustrates a PDCP PDU that may be transmitted and received by a PDCP entity according to some aspects of the present disclosure. FIG. 263 illustrates aspects of communication between instances of radio resource control (RRC) layer according to some aspects of the present disclosure. FIG. 264 illustrates states of an RRC that may be implemented in a user equipment (UE) according to some aspects of the present disclosure. DETAILEDDESCRIPTION With the advancement of 5G mmWave-based communications, several challenges have evolved, such as limited communications range, directionality of the antenna systems, achieving desired directionality and beamforming with large scale antenna arrays, signal attenuation due to atmospheric attenuation loss and high attenuation through solid materials. Techniques described herein can be used in connection with digital baseband circuitry, transmit circuitry, receive circuitry, radio frequency circuitry, protocol processing circuitry and antenna arrays to address the challenges associated with the 5G mmWave-based communications. Discussions herein utilizing terms such as, for example, "processing", "computing", "calculating", "determining", "establishing", "analyzing", "checking", or the like, may refer to operation(s) and/or process(es) of a computer, a computing platform, a computing system, or other electronic computing device, that manipulate and/or transform data represented as physical (e.g., electronic) quantities within the computer's registers and/or memories into other data similarly represented as physical quantities within the computer's registers and/or memories or other information storage medium that may store instructions to perform operations and/or processes. The terms "plurality" and "a plurality", as used herein, include, for example, "multiple" or "two or more". For example, "a plurality of items" includes two or more items. References to "one aspect", "an aspect", “an example aspect”, “some aspects”, "demonstrative aspect", "various aspects" etc., indicate that the aspect(s) so described may include a particular feature, structure, or characteristic, but not every aspect necessarily includes the particular feature, structure, or characteristic. Further, repeated use of the phrase "in one aspect" does not necessarily refer to the same aspect, although it may. As used herein, unless otherwise specified the use of the ordinal adjectives "first", "second", "third" etc., to describe a common object, merely indicate that different instances of like objects are being referred to, and are not intended to imply that the objects so described must be in a given sequence, either temporally, spatially, in ranking, or in any other manner. Some aspects may be used in conjunction with various devices and systems, for example, a User Equipment (UE), a Mobile Device (MD), a wireless station (STA), a Personal Computer (PC), a desktop computer, a mobile computer, a laptop computer, a notebook computer, a tablet computer, a server computer, a handheld computer, a sensor device, an Internet of Things (IoT) device, a wearable device, a handheld device, a Personal Digital Assistant (PDA) device, a handheld PDA device, an on-board device, an off-board device, a hybrid device, a vehicular device, a non-vehicular device, a mobile or portable device, a consumer device, a non-mobile or non-portable device, a wireless communication station, a wireless communication device, a wireless Access Point (AP), a wired or wireless router, a wired or wireless modem, a video device, an audio device, an audio-video (A/V) device, a wired or wireless network, a wireless area network, a Wireless Video Area Network (WVAN), a Local Area Network (LAN), a Wireless LAN (WLAN), a Personal Area Network (PAN), a Wireless PAN (WPAN), and the like. Some aspects may, for example, be used in conjunction with devices and/or networks operating in accordance with existing IEEE 802.11 standards (including IEEE 802.11-2016 (IEEE 802.11-2016, IEEE Standard for Information technology--Telecommunications and information exchange between systems Local and metropolitan area networks--Specific requirements Part 11: Wireless LAN Medium Access Control (MAC) and Physical Layer (PHY) Specifications, December 7, 2016); IEEE802.11ay (P802.11ay Standard for Information Technology--Telecommunications and Information Exchange Between Systems Local and Metropolitan Area Networks--Specific Requirements Part 11: Wireless LAN Medium Access Control (MAC) and Physical Layer (PHY) Specifications--Amendment: Enhanced Throughput for Operation in License-Exempt Bands Above 45 GHz)) and/or future versions and/or derivatives thereof, devices and/or networks operating in accordance with existing WiFi Alliance (WFA) Peer-to-Peer (P2P) specifications (including WiFi P2P technical specification, version 1.5, August 4, 2015) and/or future versions and/or derivatives thereof, devices and/or networks operating in accordance with existing Wireless-Gigabit-Alliance (WGA) specifications (including Wireless Gigabit Alliance, Inc WiGig MAC and PHY Specification Version 1.1, April 2011, Final specification) and/or future versions and/or derivatives thereof, devices and/or networks operating in accordance with existing cellular specifications and/or protocols, e.g., 3rd Generation Partnership Project (3GPP), 3GPP Long Term Evolution (LTE) and/or future versions and/or derivatives thereof, units and/or devices which are part of the above networks, and the like. Some aspects may be used in conjunction with one way and/or two-way radio communication systems, cellular radio-telephone communication systems, a mobile phone, a cellular telephone, a wireless telephone, a Personal Communication Systems (PCS) device, a PDA device which incorporates a wireless communication device, a mobile or portable Global Positioning System (GPS) device, a device which incorporates a GPS receiver or transceiver or chip, a device which incorporates an RFID element or chip, a Multiple Input Multiple Output (MIMO) transceiver or device, a Single Input Multiple Output (SIMO) transceiver or device, a Multiple Input Single Output (MISO) transceiver or device, a device having one or more internal antennas and/or external antennas, Digital Video Broadcast (DVB) devices or systems, multi-standard radio devices or systems, a wired or wireless handheld device, e.g., a Smartphone, a Wireless Application Protocol (WAP) device, or the like. Some aspects may be used in conjunction with one or more types of wireless communication signals and/or systems, for example, Radio Frequency (RF), Infra-Red (IR), Frequency-Division Multiplexing (FDM), Orthogonal FDM (OFDM), Orthogonal Frequency-Division Multiple Access (OFDMA), Spatial Divisional Multiple Access (SDMA), FDM Time-Division Multiplexing (TDM), Time-Division Multiple Access (TDMA), Multi-User MIMO (MU-MIMO), Extended TDMA (E-TDMA), General Packet Radio Service (GPRS), extended GPRS, Code-Division Multiple Access (CDMA), Wideband CDMA (WCDMA), CDMA 2000, single-carrier CDMA, multi-carrier CDMA, Multi-Carrier Modulation (MDM), Discrete Multi-Tone (DMT), Bluetooth, Global Positioning System (GPS), Wi-Fi, Wi-Max, ZigBeeTM, Ultra-Wideband (UWB), Global System for Mobile communication (GSM), 2G, 2.5G, 3G, 3.5G, 4G, Fifth Generation (5G) mobile networks, 3GPP, Long Term Evolution (LTE), LTE advanced, Enhanced Data rates for GSM Evolution (EDGE), or the like. Other aspects may be used in various other devices, systems and/or networks. The term "wireless device", as used herein, includes, for example, a device capable of wireless communication, a communication device capable of wireless communication, a communication station capable of wireless communication, a portable or non-portable device capable of wireless communication, or the like. In some demonstrative aspects, a wireless device may be or may include a peripheral that is integrated with a computer, or a peripheral that is attached to a computer. In some demonstrative aspects, the term "wireless device" may optionally include a wireless service. The term "communicating" as used herein with respect to a communication signal includes transmitting the communication signal and/or receiving the communication signal. For example, a communication unit, which is capable of communicating a communication signal, may include a transmitter to transmit the communication signal to at least one other communication unit, and/or a communication receiver to receive the communication signal from at least one other communication unit. The verb communicating may be used to refer to the action of transmitting and/or the action of receiving. In one example, the phrase "communicating a signal" may refer to the action of transmitting the signal by a first device, and may not necessarily include the action of receiving the signal by a second device. In another example, the phrase "communicating a signal" may refer to the action of receiving the signal by a first device, and may not necessarily include the action of transmitting the signal by a second device. Some demonstrative aspects may be used in conjunction with a WLAN, e.g., a WiFi network. Other aspects may be used in conjunction with any other suitable wireless communication network, for example, a wireless area network, a "piconet", a WPAN, a WVAN and the like. Some demonstrative aspects may be used in conjunction with a wireless communication network communicating over a frequency band above 45 Gigahertz (GHz), e.g., 60 GHz. However, other aspects may be implemented utilizing any other suitable wireless communication frequency bands, for example, an Extremely High Frequency (EHF) band (the millimeter wave (mmWave) frequency band), e.g., a frequency band within the frequency band of between 20 GHz and 300 GHz, a frequency band above 45 GHz, a frequency band below 20 GHz, e.g., a Sub 1 GHz (S1G) band, a 2.4 GHz band, a 5 GHz band, a WLAN frequency band, a WPAN frequency band, a frequency band according to the WGA specification, and the like. As used herein, the term "circuitry" may, for example, refer to, be part of, or include, an Application Specific Integrated Circuit (ASIC), an integrated circuit, an electronic circuit, a processor (shared, dedicated, or group), and/or memory (shared, dedicated, or group), that execute one or more software or firmware programs, a combinational logic circuit, and/or other suitable hardware components that provide the described functionality. In some aspects, circuitry may include logic, at least partially operable in hardware. In some aspects, the circuitry may be implemented as part of and/or in the form of a radio virtual machine (RVM), for example, as part of a Radio processor (RP) configured to execute code to configured one or more operations and/or functionalities of one or more radio components. The term "logic" may refer, for example, to computing logic embedded in circuitry of a computing apparatus and/or computing logic stored in a memory of a computing apparatus. For example, the logic may be accessible by a processor of the computing apparatus to execute the computing logic to perform computing functions and/or operations. In one example, logic may be embedded in various types of memory and/or firmware, e.g., silicon blocks of various chips and/or processors. Logic may be included in, and/or implemented as part of, various circuitry, e.g., radio circuitry, receiver circuitry, control circuitry, transmitter circuitry, transceiver circuitry, processor circuitry, and/or the like. In one example, logic may be embedded in volatile memory and/or non-volatile memory, including random access memory, read only memory, programmable memory, magnetic memory, flash memory, persistent memory, and/or the like. Logic may be executed by one or more processors using memory, e.g., registers, buffers, stacks, and the like, coupled to the one or more processors, e.g., as necessary to execute the logic. The term "antenna", as used herein, may include any suitable configuration, structure and/or arrangement of one or more antenna elements, components, units, assemblies and/or arrays. In some aspects, the antenna may implement transmit and receive functionalities using separate transmit and receive antenna elements. In some aspects, the antenna may implement transmit and receive functionalities using common and/or integrated transmit/receive elements. The antenna may include, for example, a phased array antenna, a single element antenna, a set of switched beam antennas, and/or the like. The phrase "peer to peer (PTP) communication", as used herein, may relate to device-to-device communication over a wireless link ("peer-to-peer link") between devices. The PTP communication may include, for example, a WiFi Direct (WFD) communication, e.g., a WFD Peer to Peer (P2P) communication, wireless communication over a direct link within a Quality of Service (QoS) basic service set (BSS), a tunneled direct-link setup (TDLS) link, a STA-to-STA communication in an independent basic service set (IBSS), or the like. Some demonstrative aspects are described herein with respect to WiFi communication. However, other aspects may be implemented with respect to any other communication scheme, network, standard and/or protocol. In some demonstrative aspects, a wireless communication device may implement a millimeter wave (mmWave) radio front end module (RFEM), e.g., as described below. Millimeter wave may be defined as a frequency range spanning about 30 GHz to about 300 GHz, and in practice currently covers several discrete licensed and unlicensed frequency bands. The unlicensed mmWave frequency band currently available is in the vicinity of 60 GHz. Licensed frequency bands are likely to include 28 GHz, 39 GHz, 73 GHz and 120 GHz. The availability of these bands and the specific frequency range of each varies by regulatory jurisdiction, and in some cases (specifically for licensed band operation) there is still significant uncertainty as to regulations in some countries. Challenges associated with mmWave-based cellular communications include limited range, directionality of antennas of the range, signal loss because of use of regular cables instead of traces, and challenges with integrating multiple antennas for beamforming. These challenges are addressed in this patent as discussed below in accordance with some aspects, and may include use of polarization innovations, trace and other line use to avoid signal loss, and an improved ability for use in beamforming. FIG. 1 illustrates an exemplary user device according to some aspects. The user device 100 may be a mobile device in some aspects and includes an application processor 105, baseband processor 110 (also referred to as a baseband sub-system), radio front end module (RFEM) 115, memory 120, connectivity sub-system 125, near field communication (NFC) controller 130, audio driver 135, camera driver 140, touch screen 145, display driver 150, sensors 155, removable memory 160, power management integrated circuit (PMIC) 165, and smart battery 170. In some aspects, application processor 105 may include, for example, one or more central processing unit (CPU) cores and one or more of cache memory, low drop-out voltage regulators (LDOs), interrupt controllers, serial interfaces such as SPI, I2C or universal programmable serial interface sub-system, real time clock (RTC), timer-counters including interval and watchdog timers, general purpose IO, memory card controllers such as SD/MMC or similar, USB interfaces, MIPI interfaces, and/or Joint Test Access Group (JTAG) test access ports. In some aspects, baseband processor 110 may be implemented, for example, as a solder-down substrate including one or more integrated circuits, a single packaged integrated circuit soldered to a main circuit board, and/or a multi-chip module including two or more integrated circuits. Applications of mmWave technology can include, for example, WiGig and future 5G, but the mmWave technology can be applicable to a variety of telecommunications systems. The mmWave technology can be especially attractive for short-range telecommunications systems. WiGig devices operate in the unlicensed 60 GHz band, whereas 5G mmWave is expected to operate initially in the licensed 28 GHz and 39 GHz bands. A block diagram of an example baseband sub-system 110 and RFEM 115 in a mmWave system is shown in FIG. 1A. FIG. 1A illustrates a mmWave system 100A, which can be used in connection with the device 100 of FIG. 1 according to some aspects of the present disclosure. The system 100A includes two components: a baseband sub-system 110 and one or more radio front end modules (RFEMs) 115. The RFEM 115 can be connected to the baseband sub-system 110 by a single coaxial cable 190, which supplies a modulated intermediate frequency (IF) signal, DC power, clocking signals and control signals. The baseband sub-system 110 is not shown in its entirety, but FIG. 1A rather shows an implementation of analog front end. This includes a transmitter (TX) section 191A with an upconverter 173 to intermediate frequency (IF) (around 10 GHz in current implementations), a receiver (RX) section 191B with downconversion 175 from IF to baseband, control and multiplexing circuitry 177 including a combiner to multiplex/demultiplex transmit and receive signals onto a single cable 190. In addition, power tee circuitry 192 (which includes discrete components) is included on the baseband circuit board to provide DC power for the RFEM 115. In some aspects, the combination of the TX section and RX section may be referred to as a transceiver, to which may be coupled one or more antennas or antenna arrays of the types described herein. The RFEM 115 can be a small circuit board including a number of printed antennas and one or more RF devices containing multiple radio chains, including upconversion/downconversion 174 to millimeter wave frequencies, power combiner/divider 176, programmable phase shifting 178 and power amplifiers (PA) 180, low noise amplifiers (LNA) 182, as well as control and power management circuitry 184A and 184B. This arrangement can be different from Wi-Fi or cellular implementations, which generally have all RF and baseband functionality integrated into a single unit and only antennas connected remotely via coaxial cables. This architectural difference can be driven by the very large power losses in coaxial cables at millimeter wave frequencies. These power losses can reduce the transmit power at the antenna and reduce receive sensitivity. In order to avoid this issue, in some aspects, PAs 180 and LNAs 182 may be moved to the RFEM 115 with integrated antennas. In addition, the RFEM 115 may include upconversion / downconversion 174 so that the IF signals over the coaxial cable 190 can be at a lower frequency. Additional system context for mmWave 5G apparatuses, techniques and features is discussed herein below. FIG. 2 illustrates an exemplary base station or infrastructure equipment radio head according to some aspects. The base station radio head 200 may include one or more of application processor 205, baseband processors 210, one or more radio front end modules 215, memory 220, power management integrated circuitry (PMIC) 225, power tee circuitry 230, network controller 235, network interface connector 240, satellite navigation receiver (e.g., GPS receiver) 245, and user interface 250. In some aspects, application processor 205 may include one or more CPU cores and one or more of cache memory, low drop-out voltage regulators (LDOs), interrupt controllers, serial interfaces such as SPI, I2C or universal programmable serial interface, real time clock (RTC), timer-counters including interval and watchdog timers, general purpose IO, memory card controllers such as SD/MMC or similar, USB interfaces, MIPI interfaces and Joint Test Access Group (JTAG) test access ports. In some aspects, baseband processor 210 may be implemented, for example, as a solder-down substrate including one or more integrated circuits, a single packaged integrated circuit soldered to a main circuit board or a multi-chip sub-system including two or more integrated circuits. In some aspects, memory 220 may include one or more of volatile memory including dynamic random access memory (DRAM) and/or synchronous DRAM (SDRAM), and nonvolatile memory (NVM) including high-speed electrically erasable memory (commonly referred to as Flash memory), phase-change random access memory (PRAM), magnetoresistive random access memory (MRAM), and/or a three-dimensional crosspoint memory. Memory 220 may be implemented as one or more of solder down packaged integrated circuits, socketed memory modules and plug-in memory cards. In some aspects, power management integrated circuitry 225 may include one or more of voltage regulators, surge protectors, power alarm detection circuitry and one or more backup power sources such as a battery or capacitor. Power alarm detection circuitry may detect one or more of brown out (under-voltage) and surge (over-voltage) conditions. In some aspects, power tee circuitry 230 may provide for electrical power drawn from a network cable. Power tee circuitry 230 may provide both power supply and data connectivity to the base station radio head 200 using a single cable. In some aspects, network controller 235 may provide connectivity to a network using a standard network interface protocol such as Ethernet. Network connectivity may be provided using a physical connection which is one of electrical (commonly referred to as copper interconnect), optical or wireless. In some aspects, satellite navigation receiver 245 may include circuitry to receive and decode signals transmitted by one or more navigation satellite constellations such as the global positioning system (GPS), Globalnaya Navigatsionnaya Sputnikovaya Sistema (GLONASS), Galileo and/or BeiDou. The receiver 245 may provide, to application processor 205, data which may include one or more of position data or time data. Time data may be used by application processor 205 to synchronize operations with other radio base stations or infrastructure equipment. In some aspects, user interface 250 may include one or more of buttons. The buttons may include a reset button. User interface 250 may also include one or more indicators such as LEDs and a display screen. FIG. 3A illustrates exemplary mmWave communication circuitry according to some aspects; FIGS. 3B and 3C illustrate aspects of transmit circuitry shown in FIG. 3A according to some aspects; FIG. 3D illustrates aspects of radio frequency circuitry shown in FIG. 3A according to some aspects; FIG. 3E illustrates aspects of receive circuitry in FIG. 3A according to some aspects. Millimeter wave communication circuitry 300 shown in FIG. 3A may be alternatively grouped according to functions. Components illustrated in FIG. 3A are provided here for illustrative purposes and may include other components not shown in FIG. 3A. Millimeter wave communication circuitry 300 may include protocol processing circuitry 305 (or processor) or other means for processing. Protocol processing circuitry 305 may implement one or more of medium access control (MAC), radio link control (RLC), packet data convergence protocol (PDCP), radio resource control (RRC) and non-access stratum (NAS) functions, among others. Protocol processing circuitry 305 may include one or more processing cores to execute instructions and one or more memory structures to store program and data information. Millimeter wave communication circuitry 300 may further include digital baseband circuitry 310. Digital baseband circuitry 310 may implement physical layer (PHY) functions including one or more of hybrid automatic repeat request (HARQ) functions, scrambling and/or descrambling, coding and/or decoding, layer mapping and/or de-mapping, modulation symbol mapping, received symbol and/or bit metric determination, multi-antenna port pre-coding and/or decoding which may include one or more of space-time, space-frequency or spatial coding, reference signal generation and/or detection, preamble sequence generation and/or decoding, synchronization sequence generation and/or detection, control channel signal blind decoding, and other related functions. Millimeter wave communication circuitry 300 may further include transmit circuitry 315, receive circuitry 320 and/or antenna array circuitry 330. Millimeter wave communication circuitry 300 may further include RF circuitry 325. In some aspects, RF circuitry 325 may include one or multiple parallel RF chains for transmission and/or reception. Each of the RF chains may be connected to one or more antennas of antenna array circuitry 330. In some aspects, protocol processing circuitry 305 may include one or more instances of control circuitry. The control circuitry may provide control functions for one or more of digital baseband circuitry 310, transmit circuitry 315, receive circuitry 320, and/or RF circuitry 325. FIGS. 3B and 3C illustrate aspects of transmit circuitry shown in FIG. 3A according to some aspects. Transmit circuitry 315 shown in FIG. 3B may include one or more of digital to analog converters (DACs) 340, analog baseband circuitry 345, up-conversion circuitry 350 and/or filtering and amplification circuitry 355. DACs 340 may convert digital signals into analog signals. Analog baseband circuitry 345 may perform multiple functions as indicated below. Up-conversion circuitry 350 may up-convert baseband signals from analog baseband circuitry 345 to RF frequencies (e.g., mmWave frequencies). Filtering and amplification circuitry 355 may filter and amplify analog signals. Control signals may be supplied between protocol processing circuitry 305 and one or more of DACs 340, analog baseband circuitry 345, up-conversion circuitry 350 and/or filtering and amplification circuitry 355. Transmit circuitry 315 shown in FIG. 3C may include digital transmit circuitry 365 and RF circuitry 370. In some aspects, signals from filtering and amplification circuitry 355 may be provided to digital transmit circuitry 365. As above, control signals may be supplied between protocol processing circuitry 305 and one or more of digital transmit circuitry 365 and RF circuitry 370. FIG. 3D illustrates aspects of radio frequency circuitry shown in FIG. 3A according to some aspects. Radio frequency circuitry 325 may include one or more instances of radio chain circuitry 372, which in some aspects may include one or more filters, power amplifiers, low noise amplifiers, programmable phase shifters and power supplies. Radio frequency circuitry 325 may also in some aspects include power combining and dividing circuitry 374. In some aspects, power combining and dividing circuitry 374 may operate bidirectionally, such that the same physical circuitry may be configured to operate as a power divider when the device is transmitting, and as a power combiner when the device is receiving. In some aspects, power combining and dividing circuitry 374 may include one or more wholly or partially separate circuitries to perform power dividing when the device is transmitting and power combining when the device is receiving. In some aspects, power combining and dividing circuitry 374 may include passive circuitry including one or more two-way power divider/combiners arranged in a tree. In some aspects, power combining and dividing circuitry 374 may include active circuitry including amplifier circuits. In some aspects, radio frequency circuitry 325 may connect to transmit circuitry 315 and receive circuitry 320 in FIG. 3A. Radio frequency circuitry 325 may connect to transmit circuitry 315 and receive circuitry 320 via one or more radio chain interfaces 376 and/or a combined radio chain interface 378. In some aspects, one or more radio chain interfaces 376 may provide one or more interfaces to one or more receive or transmit signals, each associated with a single antenna structure. In some aspects, the combined radio chain interface 378 may provide a single interface to one or more receive or transmit signals, each associated with a group of antenna structures. FIG. 3E illustrates aspects of receive circuitry in FIG. 3A according to some aspects. Receive circuitry 320 may include one or more of parallel receive circuitry 382 and/or one or more of combined receive circuitry 384. In some aspects, the one or more parallel receive circuitry 382 and one or more combined receive circuitry 384 may include one or more Intermediate Frequency (IF) down-conversion circuitry 386, IF processing circuitry 388, baseband down-conversion circuitry 390, baseband processing circuitry 392 and analog-to-digital converter (ADC) circuitry 394. As used herein, the term “intermediate frequency” refers to a frequency to which a carrier frequency (or a frequency signal) is shifted as in intermediate step in transmission, reception, and/or signal processing. IF down-conversion circuitry 386 may convert received RF signals to IF. IF processing circuitry 388 may process the IF signals, e.g., via filtering and amplification. Baseband down-conversion circuitry 390 may convert the signals from IF processing circuitry 388 to baseband. Baseband processing circuitry 392 may process the baseband signals, e.g., via filtering and amplification. ADC circuitry 394 may convert the processed analog baseband signals to digital signals. FIG. 4 illustrates exemplary RF circuitry of FIG. 3A according to some aspects. In an aspect, RF circuitry 325 in FIG. 3A (depicted in FIG. 4 using reference number 425) may include one or more of the IF interface circuitry 405, filtering circuitry 410, up-conversion and down-conversion circuitry 415, synthesizer circuitry 420, filtering and amplification circuitry 424, power combining and dividing circuitry 430, and radio chain circuitry 435. FIG. 5A and FIG. 5B illustrate aspects of a radio front end module useable in the circuitry shown in FIG. 1 and FIG. 2, according to some aspects. FIG. 5A illustrates an aspect of a radio front end module (RFEM) according to some aspects. RFEM 500 incorporates a millimeter wave RFEM 505 and one or more above-six gigahertz radio frequency integrated circuits (RFIC) 515 and/or one or more sub-six gigahertz RFICs 522. In this aspect, the one or more sub-six gigahertz RFICs 515 and/or one or more sub-six gigahertz RFICs 522 may be physically separated from millimeter wave RFEM 505. RFICs 515 and 522 may include connection to one or more antennas 520. RFEM 505 may include multiple antennas 510. FIG. 5B illustrates an alternate aspect of a radio front end module, according to some aspects. In this aspect both millimeter wave and sub-six gigahertz radio functions may be implemented in the same physical radio front end module (RFEM) 530. RFEM 530 may incorporate both millimeter wave antennas 535 and sub-six gigahertz antennas 540. FIG. 6 illustrates a multi-protocol baseband processor 600 useable in the system and circuitry shown in FIG. 1 or FIG. 2, according to some aspects. In an aspect, baseband processor may contain one or more digital baseband subsystems 640A, 640B, 640C, 640D, also herein referred to collectively as digital baseband subsystems 640. In an aspect, the one or more digital baseband subsystems 640A, 640B, 640C, 640D may be coupled via interconnect subsystem 665 to one or more of CPU subsystem 670, audio subsystem 675 and interface subsystem 680. In an aspect, the one or more digital baseband subsystems 640 may be coupled via interconnect subsystem 645 to one or more of each of digital baseband interface 660A, 660B and mixed-signal baseband subsystem 635A, 635B. In an aspect, interconnect subsystem 665 and 645 may each include one or more of each of buses point-to-point connections and network-on-chip (NOC) structures. In an aspect, audio subsystem 675 may include one or more of digital signal processing circuitry, buffer memory, program memory, speech processing accelerator circuitry, data converter circuitry such as analog-to-digital and digital-to-analog converter circuitry, and analog circuitry including one or more of amplifiers and filters. FIG. 7 illustrates an exemplary of a mixed signal baseband subsystem 700, according to some aspects. In an aspect, mixed signal baseband subsystem 700 may include one or more of IF interface 705, analog IF subsystem 710, down-converter and up-converter subsystem 720, analog baseband subsystem 730, data converter subsystem 735, synthesizer 725 and control subsystem 740. FIG. 8A illustrates a digital baseband processing subsystem 801, according to some aspects. FIG. 8B illustrates an alternate aspect of a digital baseband processing subsystem 802, according to some aspects. In an aspect of FIG. 8A, the digital baseband processing subsystem 801 may include one or more of each of digital signal processor (DSP) subsystems 805A, 805B, …805N, interconnect subsystem 835, boot loader subsystem 810, shared memory subsystem 815, digital I/O subsystem 820, and digital baseband interface subsystem 825. In an aspect of FIG. 8B, digital baseband processing subsystem 802 may include one or more of each of accelerator subsystem 845A, 845B, … 845N, buffer memory 850A, 850B, … 850N, interconnect subsystem 835, shared memory subsystem 815, digital I/O subsystem 820, controller subsystem 840 and digital baseband interface subsystem 825. In an aspect, boot loader subsystem 810 may include digital logic circuitry configured to perform configuration of the program memory and running state associated with each of the one or more DSP subsystems 805. Configuration of the program memory of each of the one or more DSP subsystems 805 may include loading executable program code from storage external to digital baseband processing subsystems 801 and 802. Configuration of the running state associated with each of the one or more DSP subsystems 805 may include one or more of the steps of: setting the state of at least one DSP core which may be incorporated into each of the one or more DSP subsystems 805 to a state in which it is not running, and setting the state of at least one DSP core which may be incorporated into each of the one or more DSP subsystems 805 into a state in which it begins executing program code starting from a predefined memory location. In an aspect, shared memory subsystem 815 may include one or more of read-only memory (ROM), static random access memory (SRAM), embedded dynamic random access memory (eDRAM) and/or non-volatile random access memory (NVRAM). In an aspect, digital I/O subsystem 820 may include one or more of serial interfaces such as Inter-Integrated Circuit (I2C), Serial Peripheral Interface (SPI) or other 1, 2 or 3-wire serial interfaces, parallel interfaces such as general-purpose input-output (GPIO), register access interfaces and direct memory access (DMA). In an aspect, a register access interface implemented in digital I/O subsystem 820 may permit a microprocessor core external to digital baseband processing subsystem 801 to read and/or write one or more of control and data registers and memory. In an aspect, DMA logic circuitry implemented in digital I/O subsystem 820 may permit transfer of contiguous blocks of data between memory locations including memory locations internal and external to digital baseband processing subsystem 801. In an aspect, digital baseband interface subsystem 825 may provide for the transfer of digital baseband samples between baseband processing subsystem and mixed signal baseband or radio-frequency circuitry external to digital baseband processing subsystem 801. In an aspect, digital baseband samples transferred by digital baseband interface subsystem 825 may include in-phase and quadrature (I/Q) samples. In an aspect, controller subsystem 840 may include one or more of each of control and status registers and control state machines. In an aspect, control and status registers may be accessed via a register interface and may provide for one or more of: starting and stopping operation of control state machines, resetting control state machines to a default state, configuring optional processing features, and/or configuring the generation of interrupts and reporting the status of operations. In an aspect, each of the one or more control state machines may control the sequence of operation of each of the one or more accelerator subsystems 845. There may be examples of implementations of both FIG. 8A and FIG. 8B in the same baseband subsystem. FIG. 9 illustrates a digital signal processor (DSP) subsystem 900 according to some aspects. In an aspect, DSP subsystem 900 may include one or more of each of DSP core subsystem 905, local memory 910, direct memory access (DMA) subsystem 915, accelerator subsystem 920A, 920B…920N, external interface subsystem 925, power management circuitry 930 and interconnect subsystem 935. In an aspect, local memory 910 may include one or more of each of read-only memory, static random access memory or embedded dynamic random access memory. In an aspect, the DMA subsystem 915 may provide registers and control state machine circuitry adapted to transfer blocks of data between memory locations including memory locations internal and external to DSP subsystem 900. In an aspect, external interface subsystem 925 may provide for access by a microprocessor system external to DSP subsystem 900 to one or more of memory, control registers and status registers which may be implemented in DSP subsystem 900. In an aspect, external interface subsystem 925 may provide for transfer of data between local memory 910 and storage external to DSP subsystem 900 under the control of one or more of the DMA subsystem 915 and the DSP core subsystem 905. FIG. 10A illustrates an example of an accelerator subsystem 1000 according to some aspects. FIG. 10B illustrates an example of an accelerator subsystem 1000 according to some aspects. In an aspect, accelerator subsystem 1000 may include one or more of each of control state machine 1005, control registers 1010, memory interface 1020, scratchpad memory 1025, computation engine 1030A…1030N and dataflow interface 1035A, 1035B. In an aspect, control registers 1010 may configure and control the operation of accelerator subsystem 1000, which may include one or more of: enabling or disabling operation by means of an enable register bit, halting an in-process operation by writing to a halt register bit, providing parameters to configure computation operations, providing memory address information to identify the location of one or more control and data structures, configuring the generation of interrupts, or other control functions. In an aspect, control state machine 1005 may control the sequence of operation of accelerator subsystem 1000. FIGS. 11A-11D illustrate frame formats, according to some aspects. FIG. 11A illustrates a periodic radio frame structure 1100, according to some aspects. Radio frame structure 1100 has a predetermined duration and repeats in a periodic manner with a repetition interval equal to the predetermined duration. Radio frame structure 1100 is divided into two or more subframes 1105. In an aspect, subframes 1105 may be of predetermined duration which may be unequal. In an alternative aspect, subframes 1105 may be of a duration which is determined dynamically and varies between subsequent repetitions of radio frame structure 1100. FIG. 11B illustrates a periodic radio frame structure using frequency division duplexing (FDD) according to some aspects. In an aspect of FDD, downlink radio frame structure 1110 is transmitted by a base station or infrastructure equipment to one or more mobile devices, and uplink radio frame structure 1115 is transmitted by a combination of one or more mobile devices to a base station. A further example of a radio frame structure that may be used in some aspects is shown in FIG. 11D. In this example, radio frame 1100 has a duration of 10ms. Radio frame 1100 is divided into slots 1125, 1135 each of duration 0.1ms, and numbered from 0 to 99. Additionally, each pair of adjacent slots 1125, 1135 numbered 2i and 2i+1, where i is an integer, is referred to as a subframe. In some aspects, time intervals may be represented in units of Ts, where Ts is defined as 1/(75,000 × 2048) seconds. In FIG. 11D, a radio frame is defined as having duration 1,536,600xTs, and a slot is defined as having duration 15,366xTs. In some aspects using the radio frame format of FIG. 11D, each subframe may include a combination of one or more of downlink control information, downlink data information, uplink control information and/or uplink data information. The combination of information types and direction may be selected independently for each subframe. An example of a radio frame structure that may be used in some aspects is shown in FIG. 11E, illustrating downlink frame 1150 and uplink frame 1155. According to some aspects, downlink frame 1150 and uplink frame 1155 may have a duration of 10ms, and uplink frame 1155 may be transmitted with a timing advance 1160 with respect to downlink frame 1150. According to some aspects, downlink frame 1150 and uplink frame 1155 may each be divided into two or more subframes 1165, which may be 1ms in duration. According to some aspects, each subframe 1165 may consist of one or more slots 1170. In some aspects, according to the examples of FIG. 11D and FIG. 11E, time intervals may be represented in units of Ts. According to some aspects of the example illustrated in FIG. 11D, Ts may be defined as 1/(30,720 × 1000) seconds. According to some aspects of FIG. 11D, a radio frame may be defined as having duration 30,720.Ts, and a slot may be defined as having duration 15,360.Ts. According to some aspects of the example illustrated in FIG. 11E, Ts may be defined asTs =1/(∆fmax . Nf),where fmax = 480×103 and Nf = 4,096. According to some aspects of the example illustrated in FIG. 11E, the number of slots may be determined based on a numerology parameter, which may be related to a frequency spacing between subcarriers of a multicarrier signal used for transmission. FIGS. 12A to 12C illustrate examples of constellation designs of a single carrier modulation scheme that may be transmitted or received according to some aspects. Constellation points 1200 are shown on orthogonal in-phase and quadrature axes, representing, respectively, amplitudes of sinusoids at the carrier frequency and separated in phase from one another by 90 degrees. FIG. 12A represents a constellation including two points 1200, known as binary phase shift keying (BPSK). FIG. 12B represents a constellation including four points 1200, known as quadrature phase shift keying (QPSK). FIG. 12C represents a constellation including 16 points 1200, known as quadrature amplitude modulation (QAM) with 16 points (16QAM or QAM16). Higher order modulation constellations, comprising for example 64, 256 or 1024, points may be similarly constructed. In the constellations depicted in FIGS. 12A-12C, binary codes 1220 are assigned to the points 1200 of the constellation using a scheme such that nearest-neighbor points 1200, that is, pairs of points 1200 separated from each other by the minimum Euclidian distance, have an assigned binary code 1220 differing by only one binary digit. For example, in FIG. 12C the point assigned code 1000 has nearest neighbor points assigned codes 1001, 0000, 1100 and 1010, each of which differs from 1000 by only one bit. FIGS. 13A and 13B illustrate examples of alternate constellation designs of a single carrier modulation scheme that may be transmitted and received, according to some aspects. Constellation points 1300 and 1315 of FIG. 13A are shown on orthogonal in-phase and quadrature axes, representing, respectively, amplitudes of sinusoids at the carrier frequency and separated in phase from one another by 90 degrees. In an aspect, the constellation points 1300 of the example illustrated in Figure 13A may be arranged in a square grid, and may be arranged such that there is an equal distance on the in-phase and quadrature plane between each pair of nearest-neighbor constellation points. In an aspect, the constellation points 1300 may be chosen such that there is a pre-determined maximum distance from the origin of the in-phase and quadrature plane of any of the allowed constellation points, the maximum distance represented by a circle 1310. In an aspect, the set of allowed constellation points may exclude those that would fall within square regions 1305 at the corners of a square grid. Constellation points 1300 and 1315 of FIG. 13B are shown on orthogonal in-phase and quadrature axes, representing, respectively, amplitudes of sinusoids at the carrier frequency and separated in phase from one another by 90 degrees. In an aspect, constellation points 1315 are grouped into two or more sets of constellation points, the points of each set arranged to have an equal distance to the origin of the in-phase and quadrature plane, and lying on one of a set of circles 1320 centered on the origin. FIG. 14 illustrates an example of a system for generating multicarrier baseband signals for transmission according to some aspects. In the aspect, data 1430 may be input to an encoder 1400 to generate encoded data 1435. Encoder 1400 may perform a combination of one or more of error detecting, error correcting, rate matching, and interleaving. Encoder 1400 may further perform a step of scrambling. In an aspect, encoded data 1435 may be input to a modulation mapper 1405 to generate complex-valued modulation symbols 1440. Modulation mapper 1405 may map groups including one or more binary digits, selected from encoded data 1435, to complex valued modulation symbols according to one or more mapping tables. In an aspect, complex-valued modulation symbols 1440 may be input to layer mapper 1410 to be mapped to one or more layer mapped modulation symbol streams 1445. Representing a stream of complex-valued modulation symbols 1440 as d(i) where i represents a sequence number index, and the one or more streams 1445 of layer mapped symbols as x(k)(i) where k represents a stream number index and i represents a sequence number index, the layer mapping function for a single layer may be expressed as: x^((0) ) (i)=d(i) and the layer mapping for two layers may be expressed as: x^((0) ) (i)=d(2i) x^((1) ) (i)=d(2i+1) Layer mapping may be similarly represented for more than two layers. In an aspect, one or more streams of layer mapped modulation symbol streams 1445 may be input to precoder 1415, which generates one or more streams of precoded symbols 1450. Representing the one or more streams 1445 of layer mapped symbols as a block of vectors: [x^((0) ) (i)…x^((υ-1) ) (i)]^T where i represents a sequence number index in the range 0 to M_symb^layer-1the output is represented as a block of vectors: [z^((0) ) (i)…z^((P-1) ) (i)]^T where i represents a sequence number index in the range 0 to M_symb^ap-1. The precoding operation may be configured to include one of direct mapping using a single antenna port, transmit diversity using space-time block coding, or spatial multiplexing. In an aspect, each stream of precoded symbols 1450 may be input to a resource mapper 1420, which generates a stream of resource mapped symbols 1455. The resource mapper 1420 may map precoded symbols to frequency domain subcarriers and time domain symbols according to a mapping which may include contiguous block mapping, randomized mapping or sparse mapping according to a mapping code. In an aspect, resource mapped symbols 1455 may be input to multicarrier generator 1425 which generates time domain baseband symbol 1460. Multicarrier generator 1425 may generate time domain symbols using, for example, an inverse discrete Fourier transform (DFT), commonly implemented as an inverse fast Fourier transform (FFT) or a filter bank including one or more filters. In an aspect, where resource mapped symbols 1455 are represented as sk(i), where k is a subcarrier index and i is a symbol number index, a time domain complex baseband symbol x(t) may be represented as x(t)=∑_k▒〖s_k (i) p_T (t-T_sym )exp[j2πf_k (t-T_sym-τ_k)] 〗, where pT(t) is a prototype filter function, Tsym is the start time of the symbol period, k is a subcarrier dependent time offset, and fk is the frequency of subcarrier k. Prototype functions pT(t) may be, for example, rectangular time domain pulses, Gaussian time domain pulses or any other suitable function. In some aspects, a sub-component of a transmitted signal including a subcarrier in the frequency domain and a symbol interval in the time domain may be termed a resource element. FIG. 15 illustrates resource elements 1505 depicted in a grid form, according to some aspects. In some aspects, resource elements may be grouped into rectangular blocks including a plurality of subcarriers (e.g., 12 subcarriers) in the frequency domain and the number, P, of symbols contained in one slot in the time domain. The number P may be 6, 7, or any other suitable number of symbols. In the depiction of FIG. 15, each resource element 1505 within resource block 1500 can be indexed as (k, l) where k is the index number of subcarrier, in the range 0 to NxM-1, where N is the number of subcarriers in a resource block, and M is the number of resource blocks. FIG. 16A, FIG. 16B, FIG. 16C, and FIG. 16D illustrate example of coding, according to some aspects.FIG. 16A illustrates an example of coding process 1600 that may be used in some aspects. Coding process 1600 may include one or more physical coding processes 1605 that may be used to provide coding for a physical channel that may encode data or control information. Coding process 1600 may also include multiplexing and interleaving 1635 that generates combined coded information by combining information from one or more sources, which may include one of more of data information and control information, and which may have been encoded by one or more physical coding processes 1605. Combined coded information may be input to scrambler 1640 which may generate scrambled coded information. Physical coding process 1605 may include one or more of CRC attachment block 1610, code block segmentation 1615, channel coding 1620, rate matching 1625, and code block concatenation 1630. CRC attachment block 1610 may calculate parity bits denoted {p_0,p_1,…,p_(L-1) } from input bits denoted {a_0,a_1,…a_(A-1) } to generate a sequence of output bits {b_0,b_1,…,b_(A+L-1) }, such that the polynomial over the finite field GF(2) in the variable D using the output sequence bits as coefficients (i.e., polynomial b_0 D^(A+L-1)+b_1 D^(A+L-2)+⋯+b_(A+L-2) D^1+b_(A+L-1)), has a predetermined remainder when divided by a predetermined generator polynomial g(D) of order L. In an aspect, the predetermined remainder may be zero, L may be 24 and the predetermined polynomial g(D) may be D^24+D^23+D^18+D^17+D^14+D^11+D^10+D^7+D^6+D^5+D^4+D^3+D+1. In some aspects, the process of code block segmentation 1615 may generate one or more segmented code blocks, each including a portion of the data input to code segmentation 1615. Code block segmentation 1615 may have minimum and maximum block size constraints as parameters, determined according to a selected channel coding scheme. Code block segmentation 1615 may add filler bits to one or more output segmented code blocks, in order to ensure that the minimum block size constraint is met. Code block segmentation 1615 may divide data input to the process into blocks in order to ensure that the maximum block size constraint is met. In some aspects, code block segmentation 1615 may append parity bits to each segmented code block. Such appending of parity bits may be determined based on one or more of the selected coding scheme and whether the number of segmented code blocks to be generated is greater than one. In some aspects, the process of channel coding 1620 may generate code words from segmented code blocks according to one or more of a number of coding schemes. As an example, channel coding 1620 may make use of one or more of convolutional coding, tail biting convolutional coding, parallel concatenated convolutional coding and polar coding. An encoder 1620 that may be used to encode data according to one of a convolutional code and a tail-biting convolutional code according to some aspects is illustrated in FIG. 16B. According to some aspects, input data 1645 may be successively delayed by each of two or more delay elements 1650, generating a data word consisting of elements that include the current input data and two or more copies of the current input data, each copy delayed respectively by a different number of time units. According to some aspects, encoder 1620 may generate one or more outputs 1660, 1665 and 1670, each generated by calculating a linear combination of the elements of a data word generated by combining input data 1645 and the outputs of two or more delay elements 1650. According to some aspects, the input data may be binary data and the linear combination may be calculated using one or more exclusive or functions 1655. According to some aspects, encoder 1620 may be implemented using software running on a processor and delay elements 1650 may be implemented by storing input data 1645 in a memory. According to some aspects, a convolutional code may be generated by using convolutional encoder 1620 and initializing delay elements 1650 to a predetermined value, which may be all zeros or any other suitable value. According to some aspects, a tail-biting convolutional code may be generated by using convolutional encoder 1620 and initializing delay elements 1650 to the last N bits of a block of data, where N is the number of delay elements 1650. An encoder 16C100 that may be used to encode data according to a parallel concatenated convolutional code (PCCC) that may be referred to as a turbo code, according to some aspects is illustrated in FIG. 16C. According to some aspects, encoder 16C100 may include an interleaver 16C110, upper constituent encoder 16C115 and lower constituent encoder 16C117. According to some aspects, upper constituent encoder 16C115 may generate one or more encoded data streams 16C140 and 16C145 from input data 16C105. According to some aspects, interleaver 16C110 may generate interleaved input data 16C119 from input data 16C105. According to some aspects, lower constituent encoder 16C117 may generate one or more encoded data streams 16C150 and 16C155 from interleaved input data 16C105. According to some aspects, interleaver 16C110 may output interleaved output data 16C119 that has a one to one relationship with the data contained in input data 16C105, but with the data arranged in a different time order. According to some aspects, interleaver 16C110 may be a block interleaver, taking as input one or more blocks of input data 16C105, which may be represented as {c_0,c_1,…,c_(K-1)}, where each ci is an input data bit and K is the number of bits in each block, and generating an output corresponding to each of the one or more such input blocks, which may be represented as {c_Π(1) ,c_Π(2) ,…,c_Π(K-1) }. Π(i)is a permutation function, which may be of a quadratic form and which may be represented by Π(i)=(f_1 i+f_2 i^2 )"mod" K, where f1 and f2 are constants that may be dependent on the value of the block size K. According to some aspects, each of upper constituent encoder 16C115 and lower constituent encoder 16C117 may include input bit selector 16C118 which may generate a selected input bit stream 16C119 that may be selected from one of an encoder input bit stream during a data encoding phase and a linear combination of stored bits during a trellis termination phase. According to some aspects, each of upper constituent encoder 16C115 and lower constituent encoder 16C117 may store bits in two or more delay elements 16C120 arranged to function as a shift register, the input to the shift register consisting of a linear combination of a bit from a selected input bit stream 16C119 and previously stored bits, the stored bits being initialized to a predetermined value prior to an encoding phase, and having a predetermined value at the end of a trellis termination phase. According to some aspects, each of upper constituent encoder 16C115 and lower constituent encoder 16C117 may generate one or more outputs 16C140 and 16C145, each of which may be one of a selected input bit stream 16C119 and a linear combination of stored bits. According to some aspects, each of upper constituent encoder 16C115 and lower constituent encoder 16C117 may have a transfer function during an encoding phase that may be represented as H(z)= [1,(1+z^(-1)+z^(-3))/(1+z^(-2)+z^(-3) )]. According to some aspects, encoder 16C100 may be implemented as software instructions running on a processor in combination with memory to store data input to interleaver 16C110 and stored bits of each of upper constituent encoder 16C115 and lower constituent encoder 16C117. An encoder 16D200 that may be used to encode data bits according to a low density parity check (LDPC) code according to some aspects is illustrated in FIG. 16D. According to some aspects, data bits 16D230 input to encoder 16D200 may be stored in data store 16D210, stored data bits may be input to parity bit generator 16D220 and encoded bits 16D240 may be output by parity bit generator 16D220. According to some aspects, data bits input to LDPC encoder 16D200 may be represented as c={c_0,c_1,…,c_(K-1)}, encoded data bits 16D240 may be represented as d={c_0,c_1,…,c_(K-1),p_0,p_1,…,p_(D-K-1)}, and parity bits pi may be selected such that H.d^T=0,where H is a parity check matrix, K is the number of bits in the block to be encoded, D is the number of encoded bits and D-K is the number of parity check bits. According to an aspect, parity check matrix H may be represented as: H=[■(P^(a_0,0 )&P^(a_0,1 )&P^(a_0,2 )&&P^(a_(0,M-2) )&P^(a_(0,M-1) )@P^(a_1,0 )&P^(a_1,1 )&P^(a_1,2 )&…&P^(a_(1,M-2) )&P^(a_(1,M-1) )@P^(a_2,0 )&P^(a_2,1 )&P^(a_2,2 )&&P^(a_(2,M-2) )&P^(a_(1,M-1) )@&⋮&&⋱&&@P^(a_(N-1,0) )&P^(a_(N-1,1) )&P^(a_(N-1,2) )&&P^(a_(N-1,M-2) )&P^(a_(N-1,M-1) ) )], where P^(a_(i,j) ) is one of a zero matrix or a cyclic permutation matrix obtained from the Z×Z identity matrix by cyclically shifting the columns to the right by ai,j, Z is the size of the constituent permutation matrix, the number of encoded bits D is equal to ZM and the number of bits K in the block to be encoded is equal to ZN. FIG. 17illustrates a DTC structure 23000 in accordance with some aspects. The DTC structure 23000 may be provided in a DTx transmitter of a communication device. The DTC structure 23000 may be incorporated in digital transmit circuitry 365 of transmit circuitry 315 shown in FIG. 3C, although the structure 23000 is not limited to such. FIG. 17shows a simplified architecture; the DTC structure 23000 may include more elements than are shown in other aspects. The DTC structure 23000 shown in FIG. 17may provide a time-interleaved DTC 23010 coupled with sub-harmonic injection locking in a mmWave injection-locked oscillator 23024, as discussed in more detail below. The use of the combination of the time-interleaved DTC 23010 and mmWave injection-locked oscillator 23024 in a DTC-based phase modulator and phase shifter may permit the creation of amplitude and phase modulated signals over the bandwidth used in next generation systems. The DTC structure 23000 may operate at an RF frequency that is lower than a target mmWave frequency. The clock 23002 for the DTC 23010 may be derived from a reference signal (REF). In particular, the reference signal may be supplied to the clock 23002 either through a phase lock loop (PLL) or a multiplying delay-locked loop (MDLL) 23004. An output of the PLL/MDLL 23004 may be supplied to a digitally controlled oscillator (DCO) 23006. The output of the DCO 23006 may range over the channel bandwidth, e.g., from 1700 MHz to the desired mmWave frequency. The output of the DCO 23006 may be supplied as an input to each of the individual DTCs 23012 of the time-interleaved DTC 23010 as well as being supplied as feedback to the PLL/MDLL 23004. In some aspects, means for receiving a reference oscillation signal and/or means for reducing a frequency of the reference oscillation signal to a lower frequency signal may be implemented by the DCO 23006. The time-interleaved DTC 23010 may contain individual DTCs 23012 and a logical combiner 23014. The logical combiner 23014 may in some aspects be an OR gate or an exclusive OR (XOR) gate. In some aspects, a single logical combiner 23014 may be used. The use of multiple individual DTCs 23012 in conjunction with the logical combiner 23014 may enable a higher rate of operation than that of the individual DTCs 23012 alone. The time-interleaved DTC 23010 may be restricted to operate at frequencies of up to about 6 GHz, although in some aspects higher frequencies may be obtained. In some aspects, means for modulating, dependent on the input signal, a phase of the lower frequency signal at the DTC to generate a phase-modulated signal at a frequency higher than that of the lower frequency signal and/or means for transmitting the phase-modulated signal from the DTC to an oscillator circuit may be implemented by the time-interleaved DTC 23010. For QPSK or higher modulation, I/Q data may be supplied to a rectangular to polar converter 23028. In some aspects, means for converting a rectangular input signal into a polar output signal may be implemented by the rectangular to polar converter 23028. The rectangular to polar converter 23028 may convert the complex numbers to a polar form. The result may be an analog phase modulated signal. The phase modulated signal may be combined with a predetermined phase shift (1) at a combiner 23030 to advance or delay the phase modulated signal by a predetermined amount. The output from the combiner 23030 may be supplied to a serial to parallel converter 23026. The serial to parallel converter 23026 may convert the combiner output into a digital word and provide multiple copies of the digital words simultaneously to all of the individual DTCs 23012 of the time-interleaved DTC 23010. The digital word may indicate the timing of which of the individual DTCs 23012 is to provide a pulse at a particular time. Each individual DTC 23012 may provide a pulse at a lower frequency than the RF-DCO 23006 and whose phase differs, such that the individual DTCs 23012 activate and deactivate at different times. As in the exemplary aspect above, the individual DTCs 23012 may be combined at the logical combiner 23014 to provide an intermediate frequency signal, which may be n times higher frequency than that of the individual DTCs 23012 alone, where n is the number of individual DTCs 23012 in the time-interleaved DTC 23010. The individual DTCs 23012 may apply the desired phase modulation based on the digital word. The time-interleaved DTC 23010 may in some aspects thus also implement one or more of means for providing a digital word to a plurality of individual DTCs 23012 of the time-interleaved DTC 23010, the digital word dependent on the polar output signal, means for triggering the individual DTCs 23012 based on the digital word, means for generating parallel copies of the digital word, to send to the individual DTCs 23012, based on the polar output signal, means for logically combining outputs from the individual DTCs 23012 to generate the phase-modulated signal, means for dynamically delaying an edge of the reference oscillator signal every period to introduce phase modulation to generate the phase-modulated signal, or means for using edge interpolation to generate self-aligned phase signals based on the lower frequency signal. The output of the time-interleaved DTC 23010 may be provided to an output clock circuit 23020. The output clock circuit 23020 may contain a pulse shaper 23022 and an mmWave injection-locked oscillator 23024. The output of the DTC 23010 may be conditioned in the pulse shaper 23022 to amplify the relative harmonic content of the output of the DTC 23010 (i.e., m x fDTC). The harmonic content may be at the target mmWave frequency. The conditioned DTC output from the pulse shaper 23022 may be injected into the injection-locked oscillator 23024, which may lock onto the harmonic content and produce an output at the target mmWave frequency. In some aspects, as shown in FIG. 20below, the pulse shaper 23022 may be incorporated into the injection-locked oscillator 23024. In some aspects, means for generating a phase-modulated signal at a mmWave frequency at the oscillator circuit based on the phase-modulated signal may be implemented by the output clock circuit 23020. The output clock circuit 23020 may in some aspects also implement one or more of means for amplifying a harmonic of the phase-modulated signal and means for locking an oscillator signal of the oscillator circuit to the harmonic to produce the output oscillator signal or means for injecting, via series connected transistors, current into a tank circuit to induce the tank circuit to resonate at the mmWave frequency. FIG. 18illustrates an open loop calibrated DTC architecture 23100 in accordance with some aspects. The DTC architecture 23100 may be the same DTC architecture as shown in FIG. 17. The DTC architecture 23100 may contain a PLL/MPLL 23104 and phase injection (PI) circuit 23130. A voltage controlled oscillator (VCO) 23102 may provide an output supplied to the PLL/MPLL 2314. The VCO 23102 and PLL/MPLL 23104 may be the same as that shown in FIG. 17, except illustrating in more detail circuitry in the PLL/MPLL 23104. The PLL/MPLL 23104 may contain a multi-modulus divider (MMD) 23106 and a pair of flip-flops 23108. The MMD 23106 may reduce the frequency of the signal from the VCO 23102 to a frequency that is manageable by the DTCs (and less power-intensive). The output of the MMD 23106 may be supplied to the input of each of the flip-flops 23108. The positive and negative edges of the clock signal from the VCO 23102 may be used to trigger different flip-flops 23108, also referred to as a positive edge flip-flop and a negative edge flip-flop. The outputs from the positive and negative edge flip-flops 23108 may be supplied to the PI circuit 23130. The outputs from the positive and negative edge flip-flops 23108 may be supplied to sets of inverters (buffers) 23110 in the PI circuit 23130. The set of inverters 23110 may include, for example, two pairs of inverters. The set of inverters 23108 may include, for example, two pairs of inverters. The outputs from the flip-flops 23108 may be provided as inputs to each pair of the inverters 23110. The outputs from a first pair of the inverters 23110 may be provided to a multiplexer (MUX) 23112, and the outputs from a second pair of the inverters 23110 may be provided to a Course Edge Interpolator (CEI) 23114. The outputs from the MUX 23112 and CEI 23114 may be supplied to a programmable Digitally Controlled Course Edge Interpolator (PG-DCEI) 23120. The MUX 23112 and CEI 23114 may be used to select one of the signals from the inverters 23110. The PG-DCEI 23120 may contain a pair of inverters 23122 that receive the signals from the MUX 23112 and CEI 23114. The entrance inverter outputs may be fed to a plurality of cells 23124, each comprising a MOSFET chain, each of whose output swings between ground and a supply voltage. The number of cells 23124, in some aspects, may be 2N, where N is a positive integer. The output of each cell 23124 may be provided to an exit inverter 23126 before being supplied as the output of the DTC to the logical combiner. FIG. 19Aillustrates time interleaving of DTCs to increase the clock frequency in accordance with some aspects; FIG 232B illustrates clock signals of FIG. 19Ain accordance with some aspects. The architecture 23200 shown in FIG. 19Amay be a version of the DTC shown in FIG. 17. The architecture 23200 may, for example, contain a pair of DTCs, each of which may contain an analog part 23210 and a digital part 23220. This may be considered a simplification, for convenience, of the architecture shown in FIGS. 230 and 231. In practice, the number of analog parts 23210 and digital parts 23220 may be greater than two. A reference oscillator signal may be supplied to the analog part 23210 and may include, as above, the MMD 23212, as well as the PI 23214. The MMD 23212 output may be supplied as a clock signal to the digital part 23220, whose output may, in turn be fed back to the MMD 23212 and provided to the PI 23214. The output signal (f0) from the DTC analog parts 23210 may be supplied to an exclusive OR (XOR) 23222, which may be used to double the DTC frequency to 2f0. As shown in FIG. 19B, a number of stages are used to create the DCO clock signal. Based on a reference clock signal, each DTC in the time interleaved DTC may provide a forward and reverse clock signal having a frequency less than that of the DCO clock signal from the VCO. The number of DTCs shown in FIG. 19Bis two (N=2), although this number may vary, as above. As shown, the reverse and forward clock signals of the first DTC are respectively offset by 0 and 1/4 of the cycle and the reverse and forward clock signals of the second DTC are respectively offset by 1/2 and 3/4 of the cycle. The reverse and forward clock signals of each of the DTC may be individually XORed, which produces an XORed clock signal that doubles the frequency of the reference clock signal. The XORed clock signals from the different DTCs are then also XORed, to produce the DCO clock signal at the desired mmWave frequency. The signal produced by the DTC 23010 and injected into the oscillator 23024 may be at the frequency of the RF-DCO 23006, or may be different, depending on the aspect. FIG. 20illustrates a series injection locking oscillator 23300 with pulse shaping in accordance with some aspects. As shown in the aspect of FIG. 20, the pulse shaper 23022 and the injection-locked oscillator 23024 may be integrally formed as the injection locking oscillator 23300, instead of being provided in separate circuits or chips. In other aspects, however, the two circuits – the first to amplify the desired harmonic and the second to lock onto the harmonic and produce an output signal – may be provided in different circuits. The injection locking oscillator 23300 may contain a tank circuit 23302 as well as an injection locking circuit 23320. The injection locking circuit 23300 may rely on adding parallel devices (MOSFETs) 23306 to the cross-coupled pair 23310 to inject the perturbation into the tank circuit 23302. The perturbation is introduced through a RC shunt 23304 to the input of the parallel circuit. To improve the phase noise, the oscillator 23300 can be tuned to be approximately at the exact harmonic of the injected signal through a process, such as an automatic bank selection (ABS) process. With parallel injection, the tank current 23302 may provide a signal that is the superposition of the free-running oscillator current and the injected signal. This permits the tank voltage and current to experience a phase shift relative to the injected signal. To increase the strength of the injected signal into the tank circuit 23302, the RC shunt 23304 may be sized up. This may create trade-offs between injection strength, phase noise and tuning of the oscillator natural frequency. Instead of using a single injection device, a series injection locking circuit 23320 may be used as shown. Note that in some aspects the series injection locking circuit 23320 may be provided at both the positive and negative edge inputs. The series injection locking circuit 23320 may include multiple devices 23306 to which different signals are injected. Specifically, the injected signal may comprise individual signals that have different phases, such that both individual signals are only the same value (as shown positive) over a relatively short period compared with the length of the pulse of the individual signals. The tank circuit 23302 may be forced or adjusted to be in phase with the injected signal (current), improving the trade-off indicated above. Additionally, this may provide an increase of injection strength without increasing current consumption or worsening the loaded Q of the oscillator. A phase modulated local oscillator (LO) may drive a saturated power amplifier to provide a polar transmitter. In some aspects, a class C/D/D-1/E/F/F-1 power amplifier may be used rather than a class A or A/B amplifier, thereby reducing the amplifier power consumption. Amplitude modulation can be introduced in the power amplifier through various means such as weighted currents, capacitance, or supply modulation. FIG. 21illustrates a method of providing a mmWave frequency signal in accordance with some aspects. The method may be performed by the structures shown in FIGS. 17-20. At operation 23402, the reference oscillator may generate an RF oscillation signal. The RF oscillation signal may be generated at a frequency range that leads to increased inefficiency for DTC operation, e.g., higher than about 6 GHz. This RF oscillation signal may be used to generate a phase modulated output signal at a mmWave frequency. The RF oscillation signal received may be reduced at operation 23404 to a lower frequency signal. The lower frequency signal may be reduced by a multi modulus sub-system and thus be the RF oscillation signal divided by an integer. The reduced frequency signal may be substantially less than about 6Hz, e.g., hundreds of MHz to a couple of GHz. At operation 23406, a rectangular (I/Q) input signal may be received. The rectangular input signal may be converted into a polar signal (amplitude/phase). The polar signal may be further converted to a digital word and supplied to a DTC. The DTC may contain multiple individual DTCs whose outputs are combined using a logical OR or XOR gate. The digital word may be simultaneously provided to the individual DTCs. At operation 23408, the phase of the lower frequency signal may be modulated at the DTC. The phase modulation may be controlled by the converted input signal. The output from the individual DTCs may be combined to generate a phase-modulated signal at a frequency higher than that of the lower frequency signal. In some aspects, the higher frequency is that of the RF oscillation signal. The phase-modulated signal may be transmitted from the DTC to an oscillator circuit. The oscillator circuit may at operation 23410 generate a phase-modulated signal at the mmWave frequency. The oscillator circuit may amplify a harmonic of the input phase-modulated signal at the mmWave frequency and inject current into a tank circuit at the harmonic to induce the tank circuit to resonate at the mmWave frequency. The current injection may lock the output signal of the oscillator circuit to the harmonic to produce the output oscillator signal at the mmWave frequency. The current injection may be through series connected transistors. During communication, communication devices may also convert signals between analog and digital signals in the transmitter and receiver chain. In some communication devices, the transmitter and receiver chain may contain, among others, filters and amplifiers. Such circuitry, as well as backplane issues, may cause inhomogeneities in the creation of an output signal and may cause a non-ideal output signal to be produced. Communication device designers continue to determine the causes of deviations from signal ideality and correct the deviations through channel equalization that employ one or both hardware or software solutions. Channel equalization may be performed through feedback equalization using a decision feedback equalizer (DFE) and/or through feedforward equalization via a feedforward equalizer (FFE) in the receiver. Receiver FFE designs in general, which unlike transmitter FFE may be implemented solely in the analog domain, may be insufficient for some demands. The analog implementation may be challenging to design and implement due to the desire for increased data rate, number of taps, and energy efficiency, as well as the limited circuit area available. With the advent of multi-Gigabit (mmWave) communications and the concomitant high-speed performance of various components, as well as multipath effects, a symbol transmitted from a transmitter and received by a receiver may experience an amount of inter-symbol interference (ISI). Energy appearing before a given symbol is pre-symbol ISI or pre-cursor, while energy appearing after the symbol is post-symbol ISI or post-cursor, both of which may increase with the use of the mmWave band. One consideration of high-speed mmWave communications is that, unlike lower frequency and speed communications, extensive differences may exist in the post- and pre-cursor spread for LOS channels, which may have low to moderate post-cursor ISI spreads (1–4 ns), and NLOS channels, which may have wider ISI spreads of up to about 12 ns. A multi-tap finite impulse response (FIR) filter may be used to correct for pre-cursor effects. The use of high-speed multi-Gb/s data communications may increase the implementation difficulty due to the functionality involved, which may include delay, multiply, and addition of analog signals in a single UI. Some mmWave wireless channels have long pre-cursor tails. For example, for mmWave channels at 5GS/s a pre-cursor tail may be about 10ns in length (50UI). To correct for this extended tail and at the high data rates, a large number of taps (e.g., 50) may be used in the FFE. FFE implementation using a large number of taps may employ a correspondingly large amount of circuit area and may use more power. Power consumption in the FFE may increase exponentially with the number of taps and the occupied area is proportional to the square of the number of taps in a switching-matrix design. This may be further implicated when Quadrature Phase Shift Keying (QPSK) modulation or higher order modulation is used. In a dual-polarization wireless receiver, the FFE design may increase complications with respect to cross-talk cancellation. In particular, in communication devices in which I/Q signals are used, I/Q-based coherent modulation such as QPSK, 16QAM, etc., may exhibit cross-talk ISI between the I stream and Q stream. In the dual-polarization transceiver, the vertically polarized (V) stream and the horizontally polarized (H) stream may encounter direct ISI and cross-talk ISI. Aspects described herein may independently cancel multiple different types of ISI, including one or more of: VI-to-VI ISI, VI-to-VQ, VI-to-HI, VI-to-HQ, VQ-to-VI, VQ-to-VQ, VQ-to-HI, VQ-to-HQ, HI-to-VI, HI-to-VQ, HI-to-HI, HI-to-HQ, HQ-to-VI, HQ-to-VQ, HQ-to-HI, and HQ-to-HQ. FIG. 22illustrates a receiver in accordance with some aspects. FIG. 22illustrates basic components of a receiver 23500. Other circuitry such as filters and mixers (to mix the received signal down to baseband) and the like may be present, but are not shown for simplicity. The receiver 23500 may be incorporated in a communication device, such as an eNB, AP or UE, and may include an antenna 23502, a FFE 23504, a DFE 23506, a controller 23510 and a baseband processor 23512. The FFE 23504 may be a cascaded FFE, as discussed in more detail below. The antenna 23502 may be configured to receive signals from one or more transmitters over the same or different radio access technologies and using one or more different standards, such as 24GPP or IEEE 802.11. The signals may be provided by one or more communication devices, such as an eNB, an AP or another UE. The antenna 23502 may receive beamformed signals from the transmitter. In some aspects, the beamformed signals may be dual polarized signals, including V and H polarized signals. In other aspects, the cascaded FFE arrangement may not be limited to a dual-polarization transceiver. The received signals may be provided to the FFE 23504, which may be used to compensate for the pre-cursor tails in the signal. The pre-cursor compensated signal may then be supplied to the DFE 23506, which may further compensate for the post-cursor tails. The pre- and post-cursor compensated signal may be supplied to the baseband processor 23512. The FFE coefficients, DFE coefficients, comparator thresholds, clock timing, and other circuit settings such as the timing of the output of one or more of the FFE 23504, DFE 23506 may be controlled by the controller 23510. The baseband processor 23512 may in some aspects act as the controller 23510. FIG. 23shows a basic implementation of a FFE in accordance with some aspects. The FFE 23600 shown in FIG. 23may be provided in a receiver and may include a plurality of analog-domain delay circuits (delays) 23602 (such as a track-and-hold circuit), a plurality of multipliers 23604 and a combiner 23606. The input and output of the FFE 23600 may be analog. Each delay circuit 23602 may be formed from analog circuit components such as switches 23612 in series, with a capacitor 23614 to ground disposed between the switches 23612 and a buffer 23616 that buffers the output from the last switch 23612. The delays 23602 may be disposed in series. An analog voltage may be supplied to each delay 23602. The amount of delay provided by the delay 23602 may be predetermined and may be a single unit interval (UI). The delay may be adjustable by changing the clock frequency, although in other aspects if the UI or symbol rate is fixed, the delay may be unable to be changed. The delay 23602 of the track-and-hold circuit may be determined by the clock frequency/period rather than by capacitance. The voltage provided to each delay 23602 may also be weighted at a multiplier 23604. Each multiplier 23604 may have an individual coefficient (or weight) c0, c1, … cn associated therewith. The coefficient c0, c1, … cn of the multipliers 23604 may be the same or at least one may be different from at least one other weight. The coefficients can take any positive or negative value, including 1 or 0. The coefficients may be determined by the channel and may be different, for example, for NLOS and LOS channels. The weighted signal from the multiplier 23604 may be supplied to a combiner 23606. The combiner 23606 may combine the weighted output before a delay 23602 with the weighted output after the same delay 23602. The combiner 23606 may be disposed such that the output from all of the delays 23602 may be combined as an output of the FFE 23600. The outputs from the multipliers 23604 may be combined together simultaneously. In this case, the input signal may be a continuous analog signal while the output signal may be a discrete analog signal. Power dissipation may increase based on a number of taps and parasitic capacitance. To help alleviate this, FIG. 24Aand FIG. 24Billustrate a FFE 23700 in accordance with some aspects. The FFE 23710 may be used in the receiver shown in FIG. 22. The FFE 23700 may comprise multiple FFE stages 23710, which may operate at baseband. Each FFE stage 23710 may contain one or more delays 23704, multipliers 23702, as well as combiners 23706. In some aspects, the number of delays/FFE stage 23710 may be limited to by design optimization and may be dependent on the process technology. The FFE 23700 may be incorporated in the baseband processing circuitry 392 shown in FIG. 3E, although the FFE 23700 is not limited to such incorporation. In some aspects, means for providing a plurality of types of signals to a plurality of series-connected FFE stages may be implemented by the FFE 23700. The signal from the antenna (not shown in FIGS. 24A-24B) to each FFE stage 23710 may be split into polarized and quadrature signals. In I/Q-based coherent modulation, the signal may have both I and Q components. In a dual-polarization transceiver, a vertically polarized signal and horizontally polarized signal may be present. Each of V-signal and H-signal may have two (I and Q) data streams. Thus, as shown in FIGS. 24A-24B, there may be four data streams (VI, VQ, HI, HQ) in total in the dual-polarization transceiver. The two kinds of ISI may be cancelled: direct ISI (e.g., VI-to-VI ISI) and cross-talk ISI (e.g., VQ-to-VI, VQ-to-HI, VQ-to-HQ, etc.). Thus, the individual signals to each FFE stage 23710 may include either or both vertically and horizontally polarized signals, or I/Q signals. The vertically and horizontally polarized signals may be respectively provided along vertically and horizontally polarized signal lines as inputs to the delays 23704 on the vertically and horizontally polarized signal lines; the I and Q signals similarly may be respectively provided along I and Q signal lines as inputs to the delays 23704 on the I and Q signal lines. As shown, the individual signals may be cross-coupled at the taps before and after each delay 23704 to provide cancellation among the data streams. Each of the individual streams may have its own output from the FFE stage 23710. Thus, for example, before and after each delay 23704, the vertical and horizontal for each of the I/Q input signals may be weighted using weighting coefficients and then combined. In some aspects in which both vertical and horizontal polarized input signals and I/Q input signals are provided, such as that shown in FIGS. 24A-24B, each signal may be combined with each other signal before and after each delay 23704. Although only two FFE stages 23710 are shown, greater than two FFE stages may be used. The use of multiple FFE stages 23710 may reduce the number of taps per each FFE stage 23710 and thereby reduce power consumption, area, and complexity. In some aspects, the FFE 23700 may thus also implement as shown one or more of means for delaying input VI, VQ, HI and HQ signals through a series of delays to form a plurality of sets of delayed VI, VQ, HI and HQ signals, means for weighting each of the VI, VQ, HI and HQ signals at each tap with each of a plurality of types of weighting coefficients to form VI, VQ, HI and HQ weighted signals at the tap, means for combining the VI weighted signals at each tap to form a VI output signal, the VQ weighted signals at each tap to form a VQ output signal, the HI weighted signals at each tap to form a HI output signal and the HQ weighted signals at each tap to form a HQ output signal, means for providing each of the VI, VQ, HI and HQ output signal one of as a VI, VQ, HI and HQ input signal to another FFE stage or as a VI, VQ, HI and HQ output of the FFE, means for using the VI, VQ, HI and HQ weighted signals at each tap to cancel a different pre-cursor ISI type, means for repeating the delaying, weighting and combining on input signals for successive FFE stages, means for initially setting the VI, VQ, HI and HQ weighting coefficients for each of the VI, VQ, HI and HQ signal, other than at an initial tap, to a pre-defined value and/or means for updating the VI, VQ, HI and HQ weighting coefficients during an adaption process to converge and stabilize the VI, VQ, HI and HQ weighting coefficients during the weighting. Power consumption of each FFE stage is proportional to the exponential of the number of taps, and the area is proportional to the square of the number of taps. To provide an example of reduced power consumption, if the total number of FFE taps = Ntap, then: As can be seen, both the power and the area may be reduced as the number of stages increases but the number of taps/stage reduces for the given total number of FFE taps. In some aspects, a minimum number of taps, such as two, may be present in each FFE stage. The FFE stages 23710 may be disposed on the same chip or circuit or on different chips or circuits. In some aspects, the number of taps may be the same in each FFE stage 23710 (evenly distributed). In some aspects, the number of taps may be different in at least one of the FFE stages 23710. For example, the number of taps may taper down from a larger number of FFE stages 23710 to a smaller number of taps or may taper up from a smaller number to a larger number to improve the overall performance. Moreover, the taps in one or more of the FFE stages 23710 may be able to be individually activated or deactivated, or activated or deactivated in groups of more than one tap. If able to be controlled (e.g., by the controller shown in FIG. 22) in groups, the taps may be controlled to have a consistent distribution. For example, every other tap may be active, or every third tap may be active. In such aspects, the deactivated taps may be bypassed. Similarly, the FFE stages 23710 may be able to be individually activated or deactivated by the controller. The activation and deactivation may be dependent on one or more factors. These factors may include clock rate, modulation scheme, signal type (e.g., standard used, signal frequencies), and channel conditions, and number of taps, among other factors. In such aspects, the deactivated FFE stages 23710 may be bypassed (e.g., using switches) so that active FFE stages 23710 are connected together. This may, for example, allow power consumption to be tailored as desired. Each delay 23704 may be fixed to one UI. In addition, each multiplier 23702 within a particular FFE stage 23710 may have an individual weight associated therewith. The weights of the multipliers 23702 within the particular FFE stage 23710 may be the same or at least one may be different from at least one other weight. As above, the specifics of the multipliers 23702 within the FFE stage 23710 may be different from those of other FFE stages 23710. This is to say that, for example, although the multipliers 23702 of one FFE stage 23710 may have the same weights between delays 23704 and/or between different individual signals, either or both may not be the same in a different FFE stage 23710. In some aspects, the weighting coefficients in each FFE stage 23710 may be simultaneously updated due to adaptation to channel conditions and/or signal type, among other factors. In some aspects, the weighting coefficients in each FFE stage 23710 may be updated at different times such that adaptation due to coefficient multiplication in one or more FFE stages 23710 may occur at a particular time while the weighting coefficients in one or more other FFE stages 23710 remains fixed, and coefficient adaptation in the one or more other FFE stages 23710 may be performed at a different time while the weighting coefficients in the one or more FFE stages 23710 remains fixed. FIG. 25illustrates a method of providing analog signal equalization according to some aspects. The method 23800 may be performed by the FFE shown in FIG. 237. At operation 23802, input vertically and horizontally polarized signals may be provided to an initial FFE stage of a FFE that contains multiple FFE stages. The FFE stages may be series-connected and the inputs may be in parallel. In some aspects, I/Q signals may be provided to the FFE stages. In some aspects, VI, VQ, HI, HQ signals may be provided to each FFE stage. At operation 23804, the various signals at the tap may be weighted. The vertically and horizontally polarized signals respectively form weighted vertically and horizontally polarized signals. The I/Q signals may similarly be weighted to respectively form weighted I/Q polarized signals. As above, each of V-signal and H-signal may have two (I and Q) data streams. Each type of signal may be weighted using multiple independent coefficients to form multiple independent weighted signals. Thus, for example, each signal may be weighted with a VI coefficient, a VQ coefficient, a HI coefficient and a HQ coefficient. Moreover, the coefficients for each signal may be independent for the same type of coefficient. Thus, the VI coefficient for the VI signal may be independent of the VI coefficient for the HQ signal. At operation 23806, each weighted signal at the present tap that is weighted with the same type of coefficient may be combined to form a combined signal. That is, for example, all of the signals at the present tap weighted with VI coefficients may be combined to form a combined weighted VI signal. Each type of signal (VI, HI, VQ, HQ) may form a combined weighted signal. This provides cross-correlation among the signals. At operation 23808, it is determined whether any more taps are present in the FFE stage. As above, the FFE stage may have multiple delays, and thus taps. The number of taps may be independent among the FFE stages and thus may be the same or may be different for each FFE stage. If more taps are present, at operation 23810, each signal may be supplied to a delay. Each signal may be delayed by the same amount before returning to operation 23804. Thus, each combined signal may be combined with similar signals from previous taps. That is, for example, all of the signals at the present tap weighted with VI coefficients may be combined with all of the signals at all previous taps weighted with VI coefficients to form the combined weighted VI signal. The combined weighted signals from all taps may also be indicated as VI′, VQ′, HI′, HQ′. If no more taps are present, it may then be determined, at operation 23808, that the last delay of the present FFE stage has been reached. At operation 23812, it may be determined whether the last FFE stage has been reached. The FFE may comprise at least two FFE stages. If it is determined at operation 23812 that the last FFE stage has not been reached, the process of operations 23804-23808 (weighting, combining and delaying) may then be repeated for the delays in the next FFE stage. At operation 23814, the output signals from the last FFE stage (VI′, VQ′, HI′, HQ′) may be used as input signals for the next FFE stage. If it is determined at operation 23812 that the last FFE stage has been reached, the process may provide output signals. This is to say that the combined signals of each type may be taken at operation 23816 to be the output signals from the FFE. The FFE may generate output signals depending on the input signals and coefficients. The adaptation process may calculate and update the coefficients for each signal in each stage while the FFE is running. Initially, the coefficients may all be zero (or some pre-defined values) except the main taps. The coefficients may then be updated based on the received data and the adaptation process. Eventually, the coefficients may converge and stabilize by the adaptation. The adaptation may continually follow the process (23804 - 23814). As above, equalization may be used to compensate for limited channel bandwidth, reflection and interference. Equalization may also be used to cancel the response of symbols of the long channel response under both LOS and NLOS conditions, which may be an aspect to consider for mmWave signals. An increased amount of inter-symbol interference (ISI) (in the tens of symbols) may exist in the mmWave bands (e.g., 60 GHz band) due to the increased attenuation and multipath issues, among others. Equalization may be used to compensate or cancel out the pre- and post-cursor ISI. Even if a channel is ideal, transmitter and receiver circuits in a communication device may limit overall bandwidth. In some cases, equalization can be used to abrogate bandwidth limitations established by the transmitter and receiver circuits. A DFE is one of the equalizers that can be used to combat the effects of post-cursor ISI. The DFE may be used in the receiver. While NLOS channels may suffer a greater amount of post-cursor ISI than LOS channels, post-cursor ISI may be significant. LOS channels may have relatively fewer ISI taps and enable more efficient modulations like 16QAM and 64QAM than NLOS channels. It thus may be desirable to increase the number of DFE taps for NLOS channels. The number of taps used in a DFE may be hard-coded. As the number of taps does not change with modulation, this could lead to waste of hardware resources and chip/board area that could be used for other purposes. In accordance with exemplary aspects, a configurable DFE design is provided. A DFE tap number may be adjusted according to the modulation used. In some aspects, the DFE tap design may select quadrature phase-shift keying (QPSK) or 16 Quadrature amplitude modulation (QAM) for wireless communications by controlling a single signal (note that although this may also be applicable to Pulse-amplitude modulation (PAM2) or PAM4 for wireline communications, QPSK and 16QAM will be referred to herein for convenience). In some aspects, up to 150 post-cursors can be cancelled out and about one half of the post-cursors can be cancelled out in 16QAM mode for LOS channels that have a higher signal-to-noise ratio (SNR) and fewer post-cursor ISIs. The timing for the first DFE tap may be more stringent than for later DFE taps. FIGS. 26Aand 26Billustrate configurations of a reconfigurable DFE in accordance with some aspects. The DFE 23900 may be incorporated in the baseband processing circuitry 392 shown in FIG. 3E, although the DFE 23900 is not limited to such incorporation. FIGS. 27Aand 27Billustrate selector/DFF combination configurations of a reconfigurable DFE in accordance with some aspects. As shown in FIGS. 26Aand 26B, the DFE 23900 may comprise a comparator 23910, a SR latch 23920, latches 23930 and selector/D flipflop (DFF) combinations 23940. Down-converted signals from an antenna may be received at the DFE 23900 and used to generate an output of the DFE 23900. The components of the DFE 23900 may be provided with the same clock signal (CLK). The comparator 23910 may be supplied with a differential input. The binary output of the comparator 23910 may be supplied to the SR latch 23920. The differential input of the SR latch 23920 may be converted to a single-ended signal at the output. The output of the SR latch 23920 may be supplied to a pair of latches 23930. The first DFE tap may be taken from between the SR latch 23920 and the first latches 23930. The output from the DFE 23900 may be provided via the second latch 23932. The output of the second latch 23932 may be taken as the second DFE tap. The output of the second latch 23932 may be provided to a first of the selector/DFF combinations 23940. In some aspects, the first selector/DFF combination 23940 may include only a DFF. In other aspects, each of the selector/DFF combinations (also referred to later as latch) 23942, 23944, 23946, 23948 may include both a multiplexer and a DFF. Although a minimal number of taps are shown (after each first selector/DFF combination 23940), in some aspects, up to 74 flip-flops (delays) may be used in each chain in the DFE 23900. The total number of delays, and thus taps, may consequently be 150 (2x74 + 2). The number of flip-flops, however, may not be limited to a maximum of 74 in other aspects. The selector of each selector/DFF combination 23940 may in some aspects be a multiplexer. The inputs of the selector may be the output from two different selector/DFF combinations 23940. The selector/DFF combinations 23940 may be arranged to form a path such that the inputs of the selector/DFF combinations 23940 (other than the initial two) are from sequential and parallel selector/DFF combinations 23940, also referred to as chains. This is to say that the inputs may be from a next lower numbered selector/DFF combination 23940 (i.e., immediately lower number) and from an alternating lower numbered selector/DFF combination 23940 (i.e., last even or odd numbered selector/DFF combination 23940, dependent on whether the selector/DFF combination 23940 is even or odd numbered). The selector/DFF combinations 23940 may be arranged such that the adjacent numbers form a sequential chain through each of the selector/DFF combinations 23940 while the alternating numbers form parallel chains through the selector/DFF combinations 23940. The selector/DFF combinations 23940 may be connected such that the selector may be used to adjust the path to select one of the two chains. In particular, selectors in the selector/DFF combinations 23940 may be connected to the same selection signal (control input) that is used to select the input (data input) of the selector/DFF combination 23940. This may enable selection of the sequential chain shown in FIG. 26A for a first selector input and the parallel chains shown in FIG. 26B for a second selector input. The inputs of each selector may be the outputs of the immediately previous delay/tap in the serial and parallel chain. The number of taps (and the locations in the selector/DFF combinations 23940) may be dependent on the selector input, and thus chain. For example, as shown in the sequential chain shown in FIG. 26A, which shows a 1bit output DFE, the output of the first selector/DFF combination 23942 may be taken as the third DFE tap and provided as an input to the third selector/DFF combination 23946. The output of the third selector/DFF combination 23946 is taken as the fourth DFE tap and provided as an input to the second selector/DFF combination 23944. The output of the second selector/DFF combination 23944 is provided as an input the fourth selector/DFF combination 23948. The outputs of the second and fourth selector/DFF combination 23944, 23948 may respectively be taken as the DFE tap 5 and 6. In some aspects, means for determining a modulation scheme of a signal received at the DFE may be implemented by the DFE 23900. In some aspects, the DFE 23900 may also implement as shown one or more of means for determining, based on the modulation scheme, the tap number of taps to use in the DFE, means for selecting which of a serial chain and parallel chains to use in the DFE based on the tap number, and/or means for compensating for post-cursor ISI of the signal using outputs from the taps. In further aspects, the DFE 23900 may also implement as shown one or more of means for simultaneously triggering a plurality of delays, and/or when the parallel chains are selected, means for selecting a least significant bit (LSB) using a latched output between a first and second of the taps of a most significant bit (MSB) and/or means for avoiding affecting a delay of the first tap by providing: means for taking the first tap from an input of a first latch and the second tap from an output of a second latch and means for connecting an output of the first latch with an input of the second latch in a first of the parallel paths and with a selector input of a multiplexer in a second of the parallel paths. In some aspects, the means for selecting which of a serial chain and parallel chains to use may comprise means for applying a same selector signal to a plurality of multiplexers that are each associated with a different delay and have an output connected with an input of the associated delay and/or means for selecting the serial chain for QPSK and the parallel chains for 16QAM or higher. The selector/DFF combination 23940 is shown in more detail in FIG. 27A. As shown, the output of each selector (MUX) 24010, 24012, 24014, 24016 may be supplied to the input of a different delay 24020, 24022, 24024, 24026 to form a single delay chain. Each delay 24020, 24022, 24024, 24026 may be formed from a single D-type flipflop. The output of each delay 24020, 24022, 24024, 24026 may be supplied to one of the inputs of the next selector 24010, 24012, 24014, 24016, which is shown as 0 but in other aspects may be 1. The selection of each selector 24010, 24012, 24014, 24016 may be the same – that is, the same selection signal may be applied to each selector 24010, 24012, 24014, 24016. Although only four DFE taps are shown, in some aspects this may be extended so that up to 150 DFE 1bit taps may be used to cancel out up to 150 post-cursors, for example. In some aspects, more than 150 taps may be used, and thus more than 150 post-cursors may be cancelled. The number of DFE 1bit taps, however, may not be limited to a maximum of 150 in other aspects. The arrangement shown in FIG. 26Amay be used for the QPSK mode and provide the delays in a single daisy chain as shown. FIG. 26Bshows the arrangement that further includes circuitry for the least significant bit (LSB) as well as the MSB in a 27bit output DFE. The LSB portion of the DFE 23900 may include LSB comparators 23912, 23914. The output of LSB comparators 23912, 23914 may be respectively coupled with LSB SR latches 23922, 23924. The outputs from the SR latches 23920, 23922, 23924 may be taken in parallel as the first DFE tap. The output from the SR latches 23922, 23924 may be provided respectively as inputs to LSB latches 23936, 23938. The output from the LSB latches 23936, 23938 may be provided as inputs to a LSB multiplexer 23950. The MSB bit may be used as a selector signal for the LSB multiplexer 23950, which in turn may provide the LSB. The LSB may subsequently be provided to a third latch 23934, whose output may be taken as another input to the third selector/DFF combination 23946. The selector/DFF combination 23960 control bits may be different than that of the selector/DFF combination 23940 shown in FIG. 26A, although the hardware may be the same. The cross-coupling between the selector/DFF combinations 23940 may be eliminated as shown in FIG. 26Bso that two parallel chains are provided. The second DFE tap may be taken from the parallel output of the second and third latch 23932, 23934. The third DFE tap may be taken from the parallel output of the first and third latch 23942, 23946. The fourth DFE tap may be taken from the parallel output of the second and fourth latch 23942, 23948. The arrangement shown in FIG. 26Bmay be used for the 16QAM (PAM4) mode and provide the delays in two parallel chains. Although only four DFE taps are shown, this may be extended so that, in some aspects, up to 76 DFE 2bit taps (other than the tri-bit DFE tap 1) may be used to cancel out up to 76 post-cursors. This can be extended to a 64QAM (PAM6) modulation or higher. As above, in other aspects, a greater number of bits than 76 bits may be used. In some aspects, output of the selector/DFF combination may be a most significant bit (MSB) and a least significant bit (LSB). In particular, 16QAM may have I and Q PAM4 streams (two orthogonal PAM4 streams). This is to say that two bits may be used to represent four levels: one MSB and one LSB. In some aspects, at Tap1, 1 (the output of SR latch 23920), 1 (the output of SR latch 23922), 1 (the output of SR latch 23924) may represent the highest level, while the other levels may be represented by 1-0-1, 0-0-1, 0-0-0 (the lowest level). As shown, because the threshold of the slicer 23910 is 0, the threshold of the slicer 23912 is +2 and the threshold of the slicer 23914 is -2. Here 0, +2, -2 are relative numbers, not absolute, based on the four signal levels of -3, -1, +1 and +3. The Tap1 design (FIG. 26Aand 26B) may be used to provide an output based on the stringent DFE Tap1 delay constraint. Thus, by separating a flip-flop into two serial latches (23930 and 23932 in FIG. 26A) may enable the MUX 23950 to be placed after the initial latches (23930, 23936, 23938). Thus, delay caused by the MUX 23950 may avoid affecting the DFE Tap1 delay. If the MUX 23950 were to be placed before the latches 23930, 23936, 23938, then the DFE Tap1 delay may not be able to meet the DFE Tap1 delay constraint due to the high delay of the MUX 23950. The selector/DFF combination 23960 is shown with additional detail in FIG. 27B. The outputs of selectors 24030, 24032, 24034, 24036 may be supplied to the input of a different delay 24040, 24042, 24044, 24046 to form parallel MSB and LSB delay chains of half the length of the chain of FIG. 27A. The outputs of delays 24040, 24042, 24044, 24046 may be supplied to one of the inputs of the next selector 24030, 24032, 24034, 24036, which is shown as 1 but in other aspects be 0. The selection of selectors 24030, 24032, 24034, 24036 may be the same – that is, the same selection signal may be applied to selectors 24030, 24032, 24034, 24036. FIG. 28is a method of configuring a DFE in accordance with some aspects. The method 24100 may be performed using the structures of FIGS. 26A-26Band 27A-27B. At operation 24102, the modulation scheme may be determined. The DFE may identify the modulation scheme. The modulation scheme may be dependent on, for example, the channel ISI. Both the transmitter and the receiver may be configured to use the same modulation scheme. The modulation scheme may be, in some aspects, QPSK (PAM2) and 16QAM (PAM4). The modulation scheme may further be dependent on the type of channel (LOS or NLOS) and the parallel chains for a LOS channel when using mmWave frequencies. Once the modulation scheme has been determined, the DFE may at operation 24104 determine the chain type and tap number to use in the DFE. In some aspects, the tap number may be up to about 150 taps in PAM2 for NLOS channels and about one half (76 taps) in PAM4 mode for LOS channels. The signals from the taps may be used to cancel post-cursors in mmWave frequencies. At operation 24106, the DFE may select which of a serial chain and parallel chains to use based on the tap number. The serial chain and parallel chains may have different tap numbers, with the serial chain providing a single bit for NLOS channels and the parallel chains providing a MSB and LSB for LOS channels. In some aspects, any two or more of operations 24102, 24104 and 24106 may be combined. In operation, the DFE may trigger a plurality of DFFs that form the serial chain and parallel chains. The DFE may trigger the plurality of DFFs simultaneously. The taps may be taken from an output of a different DFF. A multiplexer may provide an input to each DFF. Each multiplexer may be associated with a different DFF. Each multiplexer may be provided with the same selector signal to select which of the serial chain or parallel chains to use. When the parallel chains are selected, a LSB multiplexer may be used to select the LSB. The LSB multiplexer output may be selected using a latched output between a first and second of the taps of the MSB. This is to say that the first tap may be taken before the first latch and the second tap may be taken after the second latch. Whether the serial chain or parallel chains are used, at operation 24108, the output from the taps may be used to cancel the ISI of a symbol. The number of frequency bands used in communications has increased due to the incorporation of carrier aggregation of licensed and unlicensed bands and the upcoming use of the mmWave bands. MmWave UEs may use both high (above 6 GHz) and low frequencies (LTE band). The higher frequencies may provide a large amount of bandwidth for data communications, enabling very high data rates, while the lower frequencies may provide higher reliability. The higher bandwidths, while used to increase the communication data rate, may affect operation aspects including system power consumption. To communicate, received RF signals may be converted to digital signals for processing at the mobile device or UE, while digital data may be converted to RF signals for transmission from the mobile device or UE. Elements in the receiver chain may include an analog-to-digital converter (ADC) that receives an RF signal from an antenna and converts the RF signal to a digital signal. The digital signal from the ADC may be provided to a front end, which may contain an analog front end and a digital front end. The digital front end may provide channelization and filtering of the RF signal from RF to baseband, digitization, sample rate conversion and perhaps synchronization. Due to the high path loss caused by atmospheric absorption and high attenuation through solid materials, massive multiple-input-multiple-output (MIMO) systems may be used for transmission in the mmWave bands. The use of beamforming to search for unblocked directed spatial channels may involve additional considerations with respect to mmWave architecture when compared to the architecture used for communication through a WPAN/WLAN. In such MIMO systems, each antenna output may use a pair of ADCs for digital processing such as low latency initial access, spatial multiplexing and multi-user communications. The power consumption of the ADC may increase linearly with sampling rate and exponentially with number of resolution bits per sample. As a result, the total power dissipation at the ADCs can be large due to the large number of antennas and wideband communications when high-resolution ADCs are used. This can create issues for a wide variety of mobile devices with respect to battery life and may be exacerbated in machine type communication (MTC) devices, whose batteries are small and expected to last for an extended amount of time. FIG. 29illustrates a mmWave architecture 24200 in accordance with some aspects. The mmWave architecture 24200 may provide hybrid beamforming. The mmWave architecture 24200 may be incorporated in the receive circuitry 320 shown in FIG. 3E, although the mmWave architecture 24200 is not limited to such incorporation. Hybrid beamforming architectures may include both digital and analog beamforming. Digital beamforming may provide flexibility in beam shaping at the cost of a one-to-one correspondence between transmitter RF chain and antenna, increasing the cost, complexity and power consumption due to the large number of antennas operating over the wide bandwidth. Channel estimation between transmitter and receiver antenna pairs may further increase the digital beamforming complexity. Analog beamforming, on the other hand, may shape the output beam with only one RF chain using phase shifters. Analog beamforming may use beam searching to find the optimal beams at the transmitter and the receiver. The beam searching may use codebooks, whose size, as well as the alignment issues, may increase with narrowing beam size. Unlike digital beamforming, analog beamforming may be limited to directivity gain due to the single RF chain used. Analog beamforming alone further may have the highest potential performance loss in the data plane due to a lack of capabilities such as multi-user communication, interference cancellation, and multi-beam formation, and the highest latency in the control plane caused by factors such as slow initial link-layer connection between the UE and eNB and ongoing synchronization. In some aspects, hybrid beamforming may use both digital and analog beamforming to increase the number of antenna elements while limiting the number of RF chains. The mmWavearchitecture 24200 shown in FIG. 29, may contain an analog beamforming architecture 24210 (also referred to as an analog phased array architecture) and a digital beamforming architecture 24220. The analog beamforming architecture 24210 and the digital beamforming architecture 24220 may include shared circuitry 24206 that include low noise amplifiers (LNAs) 24212, mixers 24214, variable gain amplifiers (VGAs) 24216, low pass filters 24218 and an oscillator 24222. The digital beamforming architecture 24220 may include multiple variable (or low) resolution ADCs 24232, while the analog beamforming architecture 24210 may include a single high-resolution ADC 24234. The resolution of the low-resolution ADCs 24232 may be 29-3 bits, for example. The mmWavearchitecture 24200 may have low latency at the control plane and high throughput at the data plane. Although not shown, other elements may be present, such as feedforward or feedback compensation circuitry. As shown, the mmWavearchitecture 24200 may receive RF signals from a plurality of antennas 24202. The signals from the antennas 24202 may be supplied to LNAs 24212 of the analog beamforming architecture 24210 and digital beamforming architecture 24220. The output of each LNA 24220 may be supplied to a different pair of mixers 24214. The mixers 24214 may downconvert the complex (I/Q) RF signals to baseband or intermediate frequency (IF) signals using the local oscillator signals from an oscillator 24222. Each of the downconverted signals from the mixers 24214 may be provided to a different VGA 24216. The amplified signal from the VGA 24216 is provided to a low pass filter 24218, which filters the amplified signal to baseband. As above, phase shifters 24226 in the analog beamforming architecture 24210 may be used to adjust the phase of each pair of signals originating from a corresponding antenna 24202. The phase-shifted signals from the phase shifters 24226 may then be combined at a combiner 24228 and supplied to a single ADC 24234 or single pair of ADCs 24234. In some aspects, the ADC 24234 may be a high-resolution ADC (e.g., 8 bits or more). In the digital beamforming architecture 24220, each filtered signal may be supplied to a different variable or low-resolution ADC 24232 without being phase shifted. The mmWave architecture 24200 may further include current mirrors or switches 24224 (hereinafter referred to merely as switches for convenience) after the filters 24218. The switches 24224 may enable direction of the received signal to either the phase shifters 24226 or the variable (low) resolution ADCs 24232. The switches 24224 may be controlled by the controller 24240. The controller 24240 may be a baseband or other processor. The controller 24240 may determine the channel type (e.g., LOS or NLOS), signal type (e.g., control or data plane), channel conditions based on one or more measured qualities (e.g., SNR, blockage), UE mobility (e.g., low), and/or modulation schemes, among others. The controller 24240 may determine, based on one or more of these characteristics, whether to switch to use the analog or digital path. FIG. 30illustrates a transmitter hybrid beamforming architecture 24300 in accordance with some aspects. The transmitter hybrid beamforming architecture 24300 may be similar to the receiver mmWave architecture 24200 shown in FIG. 29. The transmitter hybrid beamforming architecture 24300 may contain an analog beamforming architecture 24310 (also referred to as an analog phased array architecture) and a digital beamforming architecture 24320. The analog beamforming architecture 24310 and the digital beamforming architecture 3020 may include shared circuitry 24306 that include power amplifiers (PAs) 24312, mixers 24314, variable gain amplifiers (VGAs) 24316, low pass filters 24318 and an oscillator 24322. In an exemplary aspect, the digital beamforming architecture 24320 may include multiple variable (or low) resolution DACs 24332, while the analog beamforming architecture 24310 may include a single high-resolution DAC 24334. The resolution of the low-resolution DACs 24332 may be 1 or 2 bits, for example. As shown, the transmitter hybrid beamforming architecture 24300 may receive digital signals from the DFE (not shown). The signals from the DFE may be supplied to the DAC 24334, and from the DAC 24334 to a separator 24328. Pairs of analog signals from the analog beamforming architecture 24310 may be provided to phase shifters 24326. The phase shifted signals from the phase shifters 24326, along with signals from DACs 24332 of the digital beamforming architecture 24320, may be provided to the switches 24324. The switches 24324 may enable switching between the pairs of phase shifted signals and the output from the digital (low-resolution) DAC 24332. Each signal from the switches 24324 may be provided a low pass filter 24318, which filters the signal to baseband prior to amplification by the VGA 24316. The amplified signal may then be upconverted to the RF frequency using mixers 24314 supplied with the local oscillator signals from oscillator 24322. The RF signals may then be amplified by PA 24312 before being provided to a plurality of antennas 24302. In an aspect, the transmitter and receiver architectures in FIGS. 242 and 243 can be designed for modular architectures. For example, an architecture containing M antenna receivers and transmitters can be built, and then multiple copies of the architecture can be used to build a N=k*M antenna system. In some aspects, means for determining channel and signal characteristics of mmWave signals to be communicated may be implemented by the receiver mmWave architecture 24200 and/or transmitter hybrid beamforming architecture 24300. In some aspects, as shown, the receiver mmWave architecture 24200 and/or transmitter hybrid beamforming architecture 24300 may further implement, based on a determination from the channel and signal characteristics of the mmWave signals that high-resolution quantization in the receiver mmWave architecture 24200 or conversion from digital to analog is to be used in the transmitter hybrid beamforming architecture 24300, means for selecting an analog beamforming architecture, of a hybrid beamforming architecture that comprises the analog beamforming architecture and a digital beamforming architecture, to use in communicating the mmWave signals. In some aspects, as shown, the receiver mmWave architecture 24200 and/or transmitter hybrid beamforming architecture 24300 may further implement, based on a determination from the channel and signal characteristics of the mmWave signals that low-resolution quantization or conversion from digital to analog is to be used, means for selecting the digital beamforming architecture to use in communicating the mmWave signals, e.g., via controller 24240. In some aspects, as shown, the receiver mmWave architecture 24200 and/or transmitter hybrid beamforming architecture 24300 may further implement means for communicating the mmWave signals via beamforming using the analog or digital beamforming architecture selected, e.g., via the antennas 24202, 24302. In some aspects, as shown, the receiver mmWave architecture 24200 and/or transmitter hybrid beamforming architecture 24300 may further implement means for varying a resolution of each of the ADCs and DACs dependent on the channel and signal characteristics of the mmWave signals, e.g., via controller 24240 and the ADCs 24232 and/or DACs 24334. In some aspects, as shown, when the analog beamforming architecture is selected, the receiver mmWave architecture 24200 and/or transmitter hybrid beamforming architecture 24300 may further implement means for phase shifting each of the mmWave signals to produce phase shifted signals, e.g., via phase shifters 24226, 24326, and means for combining the phase shifted signals to form a combined signal to be quantized, e.g., via combiners 24228. In some aspects, as shown, the receiver mmWave architecture 24200 and/or transmitter hybrid beamforming architecture 24300 may further implement means for controlling selection of the analog or digital beamforming architecture based at least on which of a LOS or NLOS channel is to be used to communicate the mmWave signals, which of a control or data signal the mmWave signals are, a signal to noise ratio (SNR), and a modulation scheme to be used to communicate the mmWave signals, e.g., via controller 24240. In some aspects, as shown, the receiver mmWave architecture 24200 and/or transmitter hybrid beamforming architecture 24300 may further implement means for sharing analog components between the analog and digital beamforming architecture. In some aspects, the analog beamforming portion may be used when there is a LOS channel, very high SNR, low UE mobility, and blockage, as high SNR and high-resolution ADC may lead to the use of high order modulation schemes. Additionally, when there is high spatial, in-band, or adjacent channel interference, the architecture may switch from digital beamforming to analog beamforming by setting phase shifters to compute the optimal phase values digitally for fast operation. On the other hand, the digital beamforming portion may be used when the transceiver containing the receiver and transmitter shown in FIGS. 242 and 243 is operating in the control plane and either receives signals from multiple directions simultaneously (as analog beamforming does sector sweep which has a high delay) and is to have fast synchronization, initial access, UE discovery, and fast recovery from blockage, or is to communicate control plane signaling, as such signaling may use low order modulation (e.g., BPSK, QPSK) that may avoid use of a high-resolution ADC. The digital beamforming portion may be used when the transceiver is operating in the data plane and: communicates over a NLOS channel that has multiple paths as combining multiple paths to increase the effective SNR; when the SNR can be low, which may be achieved by low-resolution ADC with negligible or no loss; Spatial multiplexing; Interference nulling; and Multi-user communications. One consideration for control plane communications may be latency for initial access and UE discovery. Analog beamforming architectures may rely on highly directional transmissions. To accomplish this, both the UE and the eNB may perform a beam search to determine the optimal beam. The beam search may slow down initial access due to large beam space. When both the UE and eNB use directional beamforming, the access delay may increase. A fully digital architecture, in which multiple directions may be simultaneously determined, may permit a reduction in the initial access. As noted above, there is a trade-off between number of antennas and resolution of ADC when determining the total receiver dissipated power. FIG. 244 shows an exemplary simulation of communication rate in accordance with some aspects. In particular, FIG. 244 shows an achievable communication rate under total dissipated power consumption when the number of antennas and resolution of ADC is optimized. As shown, digital beamforming may have a higher achievable rate than analog combining as digital beamforming has the benefit of spatial sampling and combining. A NLOS channel may have a low SNR. This may translate to the use of low order modulations such as BPSK and QPSK, which allows the replacement of high-resolution ADCs with low-resolution ADCs. For a LOS channel, the SNR can be large. This can support high order modulations that use high-resolution ADCs or a large number of antennas. FIG. 32shows a simulation of SNR in accordance with some aspects. In particular, FIG. 32shows a simulation of effective SNR with analog and digital architectures over a mmWave channel. For a deterministic mmWave channel, the SNR loss due to analog beamforming may be determined. In some simulations, analog beamforming may have a 3dB combining loss, depending on the correlation between paths. In addition, for a statistical mmWave channel simulation with 64 antennas at the transmitter and 16 antennas at the receiver, no SNR loss was observed in a LOS channel due to analog beamforming. In an exemplary simulation, digital beamforming for an NLOS channel resulted in a 5-7 dB SNR benefit. Power consumption in the hybrid structures shown in FIGS. 242 and 243 may be reasonable as the analog baseband beamforming and digital beamforming share most of the components. A difference may be the use of analog baseband phase shifters and a single pair of high-resolution ADC for analog beamforming, and the use of a variable (or low) resolution ADC for digital beamforming. In some aspects, a single phase rotator (phase shifter) may consume power similar to one pair of low to medium resolution ADCs at 2 Gbps. Therefore, in an aspect, replacing the phase shifters with ADCs, analog baseband and digital beamforming may consume, for example, the same power. As a result, mixed architectures according to aspects disclosed herein may have similar power consumption as analog beamforming, and less when a high-resolution ADC is used, while having a performance gain. FIG. 33illustrates a method 24600 of communicating beamformed mmWave signals in accordance with some aspects. The method 24600 may be performed by the hybrid architecture shown in FIGS. 242 and 243. At operation 24602, the method 24600 may determine various characteristics of mmWave signals to be communicated. These characteristics may include both channel and signal characteristics. The former may include, for example, whether the channel is LOS or NLOS, while the latter may include, for example, SNR, RSSI or other measures of signal quality. The determination may be performed on previous beamformed mmWave signals that have been transmitted or received by the hybrid architecture. At operation 24604, based on a determination from the channel and signal characteristics of the mmWave signals that high-resolution quantization or conversion from digital to analog is to be used, an analog beamforming architecture, of a hybrid beamforming architecture comprising the analog beamforming architecture and a digital beamforming architecture, may be selected to be used in communicating the mmWave signals. The analog beamforming structure comprises either a single ADC or a single DAC, dependent on whether a receiver or transmitter architecture is used. Similarly, the digital beamforming structure comprises either a plurality of ADCs or a plurality of DACs. In the analog beamforming structure, each of the mmWave signals may be phase shifted to produce phase shifted signals. The phase shifted signals may be subsequently combined to form a combined signal to be quantized. At operation 24606, based on a determination from the channel and signal characteristics of the mmWave signals that low-resolution quantization or conversion from digital to analog is to be used, the digital beamforming architecture may be selected to be used in communicating the mmWave signals. The number of converters in the analog (1 converter) and digital (multiple converters) beamforming architecture may be different. The resolution of the digital beamforming architecture converters may be fixed (low) or variable. At operation 24608, the mmWave signals may be communicated (received or transmitted) using the analog or digital beamforming architecture selected. Beamforming may be used. Transceivers may provide analog, digital or hybrid beamforming. Digital beamforming may provide flexibility in beam shaping at the cost of a one-to-one correspondence between transmitter RF chain and antenna, increasing the cost, complexity and power consumption due to the large number of antennas operating over the wide bandwidth. Channel estimation between transmitter and receiver antenna pairs may further increase the digital beamforming complexity. Digital architectures may also suffer performance degradations when there is inband and adjacent channel interference, or when the SNR is very high. Analog beamforming may shape the output beam with only one RF chain using phase shifters. Analog beamforming may use beam searching to find the optimal beams at the transmitter and the receiver. The beam searching may use codebooks, whose size, as well as the alignment issues, may increase with narrowing beam size. Unlike digital beamforming, analog beamforming may be limited to directivity gain due to the single RF chain used. Analog beamforming may also be power hungry due to the use of high-resolution ADCs and DACs. Analog beamforming alone further may have the highest potential performance loss in the data plane due to a lack of capabilities such as multi-user communication, interference cancellation, and multi-beam formation, and the highest latency in the control plane caused by factors such as slow initial link-layer connection between the UE and eNB and ongoing synchronization. Hybrid beamforming may be used to provide benefits of both analog and digital beamforming, while limiting disadvantages. Moreover, a hybrid architecture may be used in which adaptive ADCs and/or DACs may be incorporated. The hybrid architecture may adapt resolution of the ADCs (DACs) according to the channel, interference, SNRs, and/or number of UEs, among others. Since the power consumption of the ADCs and DACs may decrease exponentially with reduced resolution bits, such an architecture may enable low power millimeter wave systems. FIGS. 34Aand 34Billustrate a transceiver structure in accordance with some aspects. In particular, FIG. 34Aillustrates a mmWave receiver architecture (or receiver beamforming architecture) 24700 in accordance with some aspects. The mmWave receiver architecture 24700 may provide digital beamforming. The mmWave receiver architecture 24700 may be incorporated in the parallel receive circuitry 382 shown in FIG. 3E, although the mmWave receiver architecture 24700 is not limited to such incorporation. The mmWave receiver architecture / receiver beamforming architecture 24700 shown in FIG. 34Amay include low noise amplifiers (LNAs) 24712, mixers 24714, variable gain amplifiers (VGAs) 24716, low pass filters 24718, ADCs 24732 and an oscillator 24722. The ADCs 24732 may be variable resolution ADCs 24732. The resolution of the variable resolution ADCs 24732 may vary between 34 or 35 bits, for example to a much greater number of bits, as desired. As shown, the receiver beamforming architecture 24700 may receive RF signals from a plurality of antennas 24702. The signals from the antennas 24702 may be supplied to LNAs 24712. The amplified signal from each LNA 24712 may be split into dual amplified signals and then supplied to a pair of mixers 24714. The amplified signal from each LNA 24712 may be supplied to a different, non-overlapping mixer pair of mixers 24714. The mixers 24714 may downconvert the RF signals to baseband or intermediate frequency (IF) signals using the local oscillator signals from an oscillator 24722. Each of the downconverted signals from the mixers 24714 may be provided to a different VGA 24716. The amplified signal from the VGA 24716 is provided to a low pass filter 24718, which filters the amplified signal to baseband. Each antenna 24702 may be connected to a single pair of adaptive resolution ADCs 24732. The total number of ADCs 24732, 〖2N〗_(r,) may thus be twice the number of receive antennas, N_r. A mmWave transmitter architecture (or transmitter beamforming architecture) 24710 is shown in FIG. 34B. The transmitter beamforming architecture 24710 may provide digital beamforming. The transmitter beamforming architecture 24710 may contain, for example, power amplifiers (PAs) 24728, mixers 24714, variable gain amplifiers (VGAs) 24716, low pass filters 24718, variable resolution DACs 24734 and an oscillator 24722 (numbering shown in FIG. 34A). The resolution of the variable resolution DACs 24734 may vary in a manner similar to the ADCs 24732. As shown, the transmitter beamforming architecture 24710 may receive digital signals from the DFE (not shown). The digital signals from the DFE may be supplied to the DAC 24734, where the signals may be converted to analog signals. The analog signal from each DAC 24734 may be provided a low pass filter 24718, which filters the analog signal to baseband prior to amplification by the VGA 24716. The amplified signal from the VGA 24716 may then be upconverted to the RF frequency (mmWave) using mixers 24714 supplied with the local oscillator signals from oscillator 24722. The RF signals from corresponding pairs of mixers 24714 may then be amplified by a LNA 24712 (or PA) before being provided to a plurality of antennas 24702. Each antenna 24702 may be connected to a single pair of adaptive resolution DACs 24734. The total number of DACs 24734, 2N_(t,) may thus be twice the total number of transmit antennasN_t. FIGS. 35Aand 35Billustrate a transceiver structure in accordance with some aspects. In particular, an exemplary mmWave transmitter architecture (or transmitter beamforming architecture) 3510 is shown in FIG. 35A. The transmitter beamforming architecture 24810 may provide analog beamforming. The transmitter beamforming architecture 24810 may contain, for example, power amplifiers (PAs) 24828, mixers 24814, variable gain amplifiers (VGAs) 24816, low pass filters 24818 (numbering shown in FIG. 35B), variable resolution DACs 24834, phase shifters 24824, a separator 24828 and an oscillator 24822. As shown, the transmitter beamforming architecture 24810 may receive digital signals from the DFE (not shown). The digital signals from the DFE may be supplied to the DAC 24834, where the signals may be converted to analog signals. The analog signal from the DAC 24834 may be supplied to the separator 24828, which may separate the signal into pairs of analog signals. Each pair of analog signals may then be provided to a phase shifter 24724. The phase shifted signals from each phase shifter 24724 may be provided a pair of low pass filters 24818, which may filter the analog signals to baseband prior to amplification by a pair of VGAs 24816. The amplified signals from the pair of VGAs 24816 may then be upconverted to the RF frequency (mmWave) using a pair of mixers 24814 supplied with the local oscillator signals from oscillator 24822. The RF signals from the pair of mixers 24814 may then be amplified by a PA 24828 before being provided to a plurality of antennas 24802. FIG. 35Billustrates a mmWave receiver architecture (or receiver beamforming architecture) in accordance with some aspects. The mmWave receiver architecture 24800 may provide analog beamforming. The mmWave receiver architecture/receiver beamforming architecture 24800 shown in FIG. 35A, may include low noise amplifiers (LNAs) 24812, mixers 24814, variable gain amplifiers (VGAs) 24816, low pass filters 24818, phase shifters 24824, a combiner 24826, ADCs 24832 and an oscillator 24822. As in the mmWave receiver architecture 24700, the ADCs 24832 may be variable resolution ADCs. The receiver beamforming architecture 24800 may receive RF signals from a plurality of antennas 24802. The signals from the antennas 24802 may be supplied to LNAs 24812. The amplified signal from each LNA 24812 may be split into dual amplified signals and then supplied to a pair of mixers 24814. The amplified signal from each LNA 24812 may be supplied to different, non-overlapping mixers 24814. The mixers 24814 may downconvert the RF signals to baseband or intermediate frequency (IF) signals using the local oscillator signals from an oscillator 24822. Each of the downconverted signals from the mixers 24814 may be provided to a different VGA 24816. Each amplified signal from the VGA 24816 is provided to a low pass filter 24818, which filters the amplified signal to baseband. Rather than being provided to multiple ADCs as in the mmWave receiver architecture 24700, the signals from the corresponding pairs of filters 24818 may be supplied to phase shifters 24824. The phase shifters 24824 may be used to adjust the phase of each pair of filtered signals originating from a corresponding antenna. The phase-shifted signals from the phase shifters 24824 may then be combined at a combiner 24826 and supplied to a single ADC 24832 or single pair of ADCs 24832. The digital architecture 24700 and 24710 shown in FIGS. 34Aand 34Band analog architecture 24800 and 24810 shown in FIGS. 35Aand 35Bmay be combined in parallel to provide alternate selectable transmitter and receiver architectures. Although not shown, switches may be disposed after the low pass filters to direct the signals between the filters and either the phase shifters of the digital architecture or directly with the variable resolution ADCs or DACs. The hybrid architecture may have N_rf^t RF-chains and N_t antennas at the transmitter, and N_rf^r RF-chains and N_r antennas at the receiver. As above, each RF-chain at the transmitter may be connected to one pair of adaptive resolution DACs, and each RF-chain at the receiver may be connected to one pair of adaptive resolution ADCs. In some aspects, the architectures may adaptively set the dynamic range of the ADC/DAC for optimal power consumption and a desired signal fidelity (SNR) for a use case. In some aspects, the resolution may be decreased, for example, for control plane communications such as synchronization, initial access and UE discovery. In some aspects, the resolution may be decreased based on channel conditions, such as when the SNR or the modulation order decreases. Conversely, the resolution may be increased when the SNR or the modulation order increases. The resolution may also be increased when a high dynamic range is to be used due to the presence of a substantial amount of interference, either or both in-band or adjacent channel. The resolution may also be decreased when the number of UEs served by the eNB decreases in MU-MIMO, which may correspond to a low Peak to Average Power Ratio (PAPR). On the other hand, the resolution may be increased to reduce the effect of quantization noise on MU-MIMO UEs with a low SNR when the various UEs served by the eNB have diverse SNRs or when the number of multiplexed UE is increased (and have a higher PAPR). The resolution may further be decreased and increased when the measured DC offset, i.e., mean estimate, is respectively less or greater than a predetermined set point. In some aspects, the resolution may be decreased based on timing conditions, such as during the eNB (or access point) search or during communication of the preamble or midamble. In some aspects, the resolution may be decreased for NLOS channels having an increased number of multipaths, and thus higher PAPR. In some aspects, means for receiving a first set of mmWave beamformed signals at a plurality of antennas may be implemented by the mmWave receiver architecture 24700 and/or mmWave receiver architecture 24800 and means for transmitting a second set of mmWave beamformed signals from the antennas may be implemented by the transmitter architecture 24710 and/or transmitter architecture 24810. In some aspects, as shown, the receiver architecture 24700/24800 and the transmitter architectures 24710/24810 may further respectively implement, as shown, means for setting a resolution of an ADC used in the receiving and DAC used in the transmitting based on a transceiver power dissipation constraint and free from reducing a number of ADCs or DACs. The apparatus may further comprise means for converting the first or second set of mmWave beamformed signals between analog and digital signals based on the resolution of the ADC or DAC. In some aspects, as shown, the receiver architectures 24700/24800 and the transmitter architectures 24710/24810 may further implement, means for selecting which of an analog beamforming architecture and a digital beamforming architecture of a hybrid beamforming architecture to use to receive or transmit the mmWave beamformed signals, via a controller, for example. In some aspects, as shown, the receiver architecture 24700/24800 and the transmitter architecture 24710/24810 may further implement, means for adjusting the resolution of the ADC and DAC based on which of the analog and digital beamforming architecture is selected, e.g., similarly using a controller and the ADCs/DACs. In some aspects, as shown, the receiver architectures 24700/24800 may further implement, as shown means for combining complex mmWave signals received from the antennas into a combined signal, e.g., via combiner 24826 (FIG. 35A), and means for supplying the combined signal to the single DAC as an input. FIG. 36illustrates an adaptive resolution ADC power consumption in accordance with some aspects. In particular, FIG. 36shows an achievable rate of Eigen beamforming with adaptive resolution ADCs for a MIMO downlink system. In the simulation, N_t=64 antennas at the transmitter and N_r=16 antennas at the receiver, and Rayleigh fading channel. Considering Walden’s figure of merit (FOM) (empirical): FOM =Power/(f_s 2^ENOB ) (3) where f_s = sampling frequency, ENOB = effective number of bits that is less than the total number of bits due to offset, gain errors, differential and integral non-linearity, harmonic distortions, jitter noise etc. The performance of a MIMO downlink channel may be: y_q=Q(Hx+n) where H is channel, x is input and n is additive Gaussian noise with unit variance. The achievable rate at the receiver may be determined by computing numerical mutual information, R=E_H {I(x,y_q )}. The performance of an unquantized ADC may nearly be achieved using a low (1-3) bit ADC. For example, using a 2-bit ADC closely approximates the capacity of 16QAM modulation. As given in Table 9, the total power consumption for a 2-bit ADC for 16 antennas at the receiver may be 25.6 mW. If a fixed ADC resolution of 8 bits is used for 16QAM modulation, the power consumption may increase 50 fold to 1638.4 mW, for example. Thus, in using adaptive ADCs according to some aspects, the power saving can be about 98.4%. As a result, depending on modulation order, the resolution of the ADC may be adapted to reduce power consumption. Resolution: Total Power Consumption (mW) 8 bits 1638.4 2 bits 25.6 Table 9: N_r=16,f_s=2Gsps,FOM=100fJ FIG. 37illustrates bit error rate (BER) performance in accordance with some aspects, showing an adaptive resolution ADC uncoded bit error rate (BER) performance in a mmWave channel in accordance with some aspects. As shown in FIG. 37, the performance of a receiver that comprises an unquantized ADC may be almost achieved by using a low bit ADC. FIG. 38illustrates an exemplary method 25100 of communicating beamformed mmWave signals in accordance with some aspects. The method 25100 may be performed by the hybrid architecture shown in FIGS. 247 and 248. At operation 25102, the method 25100 may determine whether mmWave signals are to be communicated. The mmWave signals may be beamformed MIMO signals that may be communicated via an LOS or NLOS channel. The mmWave signals may be received at operation 25104 or transmitted at operation 25118. The mmWave signals may be communicated via a plurality of antennas that connected with a hybrid analog/digital beamforming architecture. The hybrid analog/digital beamforming architecture may be used to receive and/or transmit the mmWave beamformed signals. After the mmWave signals have been received at operation 25104, the resolution of one or more ADCs used during reception may be set at operation 25106. In the analog domain, the complex (I/Q) output from the antennas may be combined before being provided to a single ADC. In the digital domain, there may be two ADCs for each antenna (one for I and the other for Q). Similarly, before transmission of the mmWave signals at operation 25118, the resolution of one or more DACs used during transmission may be set at operation 25114. In the analog domain, the complex (I/Q) signals to be provided to the antennas may be separated before being provided to a single DAC. In the digital domain, there may be 35 DACs for each antenna (one for I and the other for Q). Whether the mmWave signals are received or transmitted, the resolution may be based on a transceiver power dissipation constraint. The power reduction may be free from reducing the number of ADCs or DACs provided in the hybrid structure or used during the conversion process. After the resolution of the ADCs has been set at operation 25106, the mmWave beamformed signals may be converted to digital signals at operation 25108. The converted signals may be processed in a baseband processor, e.g., to compensate for in-band or adjacent channel interference. In some aspects, the resolution may be different dependent on whether the mmWave beamformed signals are being transmitted or received, or based on which of the analog and digital beamforming architecture is selected. Similarly, after the resolution of the DACs has been set at operation 25114, the mmWave beamformed signals may be converted to analog signals at operation 25116 for transmission via the antennas. The digital signals may be supplied from a baseband processor. In some aspects, the resolution of the ADC or DAC may be dependent on one or more factors and may be able to implement a single binary change (increase/decrease) or a plurality of changes, dependent on the dynamic range of the ADC/DAC and the factor. Factors may include, for example, signal type (control/data), signal quality (e.g., SNR), modulation (e.g., 16QAM), number of UEs served (for eNBs) or operation associated with the mmWave beamformed signals. In some aspects, the resolution may be decreased for synchronization, initial access, UE discovery or eNB search, with decreasing SNR/modulation order/number of UEs (low PAPR), when a measured DC offset is less than a predetermined set point or during a preamble or midamble of a signal (as opposed to the signal load). On the other hand, the resolution may be augmented as a result of: the SNR or modulation order increasing, a high dynamic range being used due to interference, UEs communicating with the eNB in which the hybrid structure is disposed having diverse SNRs (which may be used to reduce the effect of quantization noise on UEs with low SNR), the measured DC offset being greater than the predetermined set point; and with increasing multiplexed UEs (higher PAPR) or with an increasing number of multipaths (higher PAPR) in an NLOS channel. As the power consumption of phase shifters in analog and hybrid beamforming structures increases with the resolution of the phase shifters, low-bit phase shifters are attractive for low-power mmWave systems. However, in some cases, low-bit phase shifters may result in high gating lobe, power loss at the main beam, and beam steering angle error due to quantization noise. The memory size may be reduced for a codebook that contains the angles used for beam steering. The reduced codebook may be used in conjunction with a determination of the optimal phase values for subarray antennas (analog or hybrid beamforming). FIGS. 39Aand 39Billustrate a transceiver structure in accordance with some aspects In particular, FIG. 39Aillustrates a mmWave receiver architecture (or receiver beamforming architecture) 25200 in accordance with some aspects. The mmWave receiver architecture/receiver beamforming architecture 25200 may provide analog beamforming. The receiver beamforming architecture 25200 shown in FIG. 39Amay include low noise amplifiers (LNAs) 25212, mixers 25214, variable gain amplifiers (VGAs) 25216, low pass filters 25218, phase shifters 25224, a combiner 25226, an ADC 25232 and an oscillator 25222. The receiver beamforming architecture 25200 may receive RF signals from a plurality of antenna elements 25202. The signals from the antenna elements 25202 may be supplied to LNAs 25212. The amplified signal from each LNA 25212 may be split into dual amplified signals and then supplied to a pair of mixers 25214. The amplified signal from each LNA 25212 may be supplied to a different, non-overlapping mixer 25214. The mixers 25214 may downconvert the RF signals to baseband or intermediate frequency (IF) signals using local oscillator signals from an oscillator 25222. Each of the downconverted signals from the mixers 25214 may be provided to a different VGA 25216. Each amplified signal from the VGA 25216 is provided to a low pass filter 25218, which filters the amplified signal to baseband. Rather than being provided to multiple ADCs as in a digital receiver architecture, the signals from the corresponding pairs of filters 25218 may be supplied to phase shifters 25224. The phase shifters 25224 may be used to adjust the phase of each pair of filtered signals originating from a corresponding antenna. The phase-shifted signals from the phase shifters 25224 may then be combined at a combiner 25226 and supplied to a single ADC 25232 or single pair of ADCs 25232. Although only one set of phase shifters 25224 is shown, multiple sets may be used. These sets may include primary phase shifters, for RF and baseband, and secondary phase shifters, for IF and digital phase shifters. An exemplary mmWave transmitter architecture (or transmitter beamforming architecture) 25210 is shown in FIG. 39B. The transmitter beamforming architecture 25210 may provide analog beamforming. The transmitter beamforming architecture 25210 may contain, for example, power amplifiers (PAs) 25230, mixers 25214, variable gain amplifiers (VGAs) 25216, low pass filters 25218, variable resolution DACs 25234, phase shifters 25224, a separator 25228 and an oscillator 25222. As shown, the transmitter beamforming architecture 25210 may receive digital signals from the DFE (not shown). The digital signals from the DFE may be supplied to the DAC 25234, where the signals may be converted to analog signals. The analog signal from the DAC 25234 may be supplied to the separator 25228, which may separate the signal into pairs of analog signals. Each pair of analog signals may then be provided to a phase shifter 25224. The phase shifted signals from each phase shifter 25224 may be provided a pair of low pass filters 25218, which may filter the analog signals to baseband prior to amplification by a pair of VGAs 25216. The amplified signals from the pair of VGAs 3916 may then be upconverted to the RF frequency (mmWave) using a pair of mixers 25214 supplied with the local oscillator signals from oscillator 25222. The RF signals from the pair of mixers 25214 may then be amplified by a PA 25230 before being provided to a plurality of antenna elements 25202. Analog beamforming may shape the output beam with only one RF chain using phase shifters. The antenna elements in the transceiver structures (i.e., architectures 25200, 25210) of FIGS. 39Aand 39Bmay be arranged in a fixed, pre-defined pattern, with the entire antenna array being able to be divided into subarray antennas. As each antenna element may be connected to a single analog phase shifter, a set of unique phase shifting values for each antenna element, known as a codebook entry, may define a unique signal beam direction. The set of all codebook entries supported by the transceiver may be arranged into a codebook, which may be pre-loaded into the transceiver. Analog beamforming may use beam searching to find the optimal beams at the transmitter and the receiver. The size of the codebooks used for beam searching, and thus the memory used, may increase with narrowing beam size. As the power consumption of the phase shifters increases with the resolution of the phase shifters, to decrease the power consumption of the transceiver shown in FIGS. 39Aand 39B, low (1-3) bit phase shifters may be used. However, in some cases, the use of low bit phase shifters may have several detrimental effects, including resulting in the presence of high grating lobes, power loss at the main beam, and beam steering angle error due to quantization noise. To this end, a new codebook may be used for both primary and secondary phase shifters for low power phase array communications systems with low bit phase shifters. Using properties of an optimal beam steering, the memory size used for the codebook may be reduced, and the optimal phase values found for subarray antennas using the reduced codebook. In addition to reduction of the codebook size, the codebook may result in minimal main beam power loss, smaller grating lobe power (and thus less interference) and better beam steering accuracy. The codebook may be may be incorporated in the protocol processing circuitry 305 shown in FIG. 3A and/or radio chain circuitry 372 shown in FIG. 3D, although the codebook is not limited to such incorporation. FIG. 40illustrates an array structure 25300 in accordance with some aspects. The array structure 25300 may be used in an analog or hybrid beamforming architecture. The array structure 25300 may contain a uniform linear array with a subarray structure. In other aspects, the arrangement in FIG. 40may be extended to a tertiary, quaternary, etc., subarray structure. In FIG. 40, if there are M secondary phase shifters (IF phase shifter, digital phase shifter, etc.) 25314 and L primary (low bit, e.g., 39-3 bit) phase shifters 25312 in each contiguous subarray, an array factor for the beam steering angle ϕ can be written as: A(ϕ)=∑_(m=1)^M▒∑_(l=1)^L▒e^(j(θ_((m-1)L+l)+φ_m-kd((m-1)L+l)cos(ϕ))) (4) where θ_i, i=1,…,ML, and φ_j,i=1,…,M are primary phase shifter values for antenna element i and secondary phase shifter values for subarray j, respectively. In addition, k=2π/λ is the wave number and λ is wavelength, d is the distance between each antenna element. Without loss of generality, d=λ/2. Note that the calculations described herein may be performed by a processor, such as a baseband processor of the analog or hybrid beamforming architecture, and stored as a codebook to be used to generate the steering angles of the antennas. In this approach, the phase values of the phase shifters 25312, 25314 (both IF and RF) may be increased progressively based on their relative positions to each other. That is, θ_((m-1)L+l)=((m-1)L+l)θ, and φ_m=mφ, where θ and φ are progressive phase values. However, grating lobes may appear. FIG. 41shows a simulation of grating lobes in accordance with some aspects. This may be due to fact that the distance between the secondary phase shifters 25314 is d=2λ. Note that the number of grating lobes is equal to 2d/λ. In some aspects, means for limiting a size of a codebook used for beam steering of antennas to a subset of steering angles over which the antennas are to be steered may be implemented by the receiver architecture 25200 and/or transmitter architecture 25210. In some aspects, as shown, the receiver architecture 25200 and/or transmitter architecture 25210 may further implement means for determining a particular steering angle, outside the subset of steering angles, to which to steer the antennas, means for determining a limited steering angle within the subset of steering angles corresponding to the particular steering angle, means for determining a shift value to shift the limited steering angle to the particular steering angle and means for steering the antennas by applying the limited steering angle and the shift value, e.g., via a controller. In some aspects, as shown, the receiver architecture 25200 and/or transmitter architecture 25210 may further implement one or more of means for applying a limited steering angle value to a plurality of primary phase shifters to steer the antennas to the limited steering angle and means for applying the shift value to a plurality of secondary phase shifters to shift the limited steering angle to the particular steering angle, and/or means for applying a unitary multiplier that indicates whether the particular steering angle is set directly by the limited steering angle and shift value or whether the particular steering angle is set by a reflection of the limited steering angle and shift value around shift value around 180º. As shown in FIG. 41, the number of grating lobes is equal to 2d/λ=4λ/λ=4. As can be seen, the power of the first grating lobe is higher than the first side lobe. This may create high interference to other UEs and reduce the power of the main beam. Optimization may be used to increase the power of the main lobe and reduce grating lobes. Using the array factor, the optimization problem for a steering angle ϕ can be written as follows: max⁡〖 |∑_(m=1)^M▒∑_(l=1)^L▒e^(j(θ_((m-1)L+l)+φ_m-kd((m-1)L+l)cos(ϕ))) |^2 〗 Subject to θ_i∈{((j-1)360°)/2^(b_p ) ,j=1,…,2^(b_p )-1} , i=1,…,ML 〖 φ〗_i∈{((j-1)360°)/2^(b_s ) ,j=1,…,2^(b_s )-1}, i=1,…,M where b_p and b_s are resolution bits of the secondary and primary phase shifters. Note that the optimization problem given above may be a non-deterministic polynomial-time (NP)-hard mixed integer program. In addition, the objective function may not be convex and may have 2^LM number of possible solutions only for the primary phase shifters. The maximum of the objective function can be achieved when the term in the objective function (θ_((m-1)L+l)+φ_m-π((m-1)L+l)cos(ϕ))=C is constant for ∀ m,l. One special case is θ_((m-1)L+l)+φ_m=π((m-1)L+l)cos(ϕ) without loss of optimality. Then, the optimization problem can be reformulated as follows: min⁡〖 ∑_(m=1)^M▒∑_(l=1)^L▒〖〖|θ〗_((m-1)L+l)+φ_m-kd((m-1)L+l)cos(ϕ)|〗〗 (5) Subject to θ_i∈{((j-1)360°)/2^(b_p ) ,j=1,…,2^(b_p )-1} , i=1,…,ML 〖 φ〗_i∈{((j-1)360°)/2^(b_s ) ,j=1,…,2^(b_s )-1}, i=1,…,M Next, the size of search space may be reduced using properties of quantized phase shifters. Returning to the array factor given in (4) and assuming that the optimal primary θ^*=[θ_1^*,…,θ_ML^*] and secondary φ^*=[φ_1^*,…,φ_M^*] phase shifter vectors have been obtained for beam angleϕ, i.e., |A(ϕ)|=|∑_(m=1)^M▒〖∑_(l=1)^L▒e^j(θ_((m-1)L+l)^*+φ_m^*-kd((m-1)L+l) cos⁡(ϕ) ) |〗=ML. Then, the above equation may be modified as follows: |A(ϕ_s )|=|∑_(m=1)^M▒∑_(l=1)^L▒e^j(θ_((m-1)L+l)^*+φ_m^*+((m-1)L+l) s2π/2^(b_p ) -kd((m-1)L+l) cos⁡(ϕ_s ) ) |=ML where 2π/2^(b_p ) is due to b_p-bit primary phase shifters. When the exponential terms given in the above equations are compared: kd((m-1)L+l) cos⁡(ϕ)=((m-1)L+l) s2π/2^(b_p ) +kd((m-1)L+l) cos⁡(ϕ_s ) cos⁡(ϕ)=s2π/(kd2^(b_p ) )+cos⁡(ϕ_s ) ϕ_s=arccos⁡(s/2^(b_p-1) +cos⁡〖(ϕ))〗 if d=λ/2 where arccos(1/2^(b_p-1) )<ϕ≤90°, and sϵ{-2^(b_p-1),..,-1,0,1,…,2^(b_p-1)-1}. As a result, the optimal primary and secondary phase values may be determined for all steering angles 0<ϕ≤90°, if an optimal codebook for the steering angles between arccos(1/2^(b_p-1) )°<ϕ≤90° is known. θ_m^*←θ_m^*+(m-1)sπ/2^(b_p-1) , m=1,…,ML, and s=-2^(b_p-1),..,-1,0,1,…,2^(b_p-1)-1 (6) FIG. 42illustrates a simulation of optimal phase values in accordance with some aspects, providing an example of a determination of optimal primary and secondary phase values for 3-bit primary phase shifters. As shown, if the phased array system has an optimal codebook for steering angles between, for example, 75.5° and 90° (shaded area), then optimal codewords for the eight regions between the arrows may be calculated. In addition, using a backlobe of the array factor, the codebook size may be further reduced to arccos(1/2^(b_p ) )°<ϕ^*≤90°. Then, a unitary multiplier may be used. By simply multiplying the optimal primary and secondary phase values by -1, the steering angle 180-ϕ^* may be obtained. That is, θ_l^*←-θ_l^*, l=1,…,ML, φ_m^*←〖-φ〗_m^*, m=1,…,M The primary and secondary phase shifters may have the same number of bits or may have different bits in different aspects. The primary phase shifters thus determine the region in which beam steering is to occur and the secondary phase shifters determine where within the selected region the beam steering angle is located. FIG. 43illustrates another simulation of optimal phase values in accordance with some aspects, providing an example of determination of optimal primary and secondary phase values for 4-bit primary phase shifters. As shown, if the phased array system has an optimal codebook for steering angles between 82.81° and 90° (shaded area), the optimal codewords may be computed for RHS of the shaded area by multiplying the optimal phase values by -1. The optimal phase values may subsequently be determined for all sixteen regions using Eq. (6). The settings for the primary and secondary phase shifters may be established in an initial training sequence and may be periodically updated, e.g., based on a predetermined amount of time elapsing from the last training session. As a result, the codebook size may be reduced to determining the steering angles arccos(1/2^(b_p ) )°<ϕ^*≤90°. The main beam may subsequently be steered to any desired angle by using a simple progressive phase change. This property allows storage of only a codebook corresponding to steering angle arccos(1/2^(b_p ) )°<ϕ^*≤90°, and to quickly switch the steering angle. Turning to the memory size reduction, examples are provided for 41-bit primary phase shifters and 12-bit secondary phase shifters. AssumeM=8,L=4. For a beam resolution of 0.5° in 82.81°<ϕ^*≤90°, the memory size may be 2.69 kb instead of the conventional 43 kb, reducing the codebook size by 93.7%. In addition, the codebook may be optimized only for the steering angles arccos(1/2^(b_p ) )°<ϕ^*≤90°. Since ϕ may be limited to arccos(1/2^(b_p ) )°<ϕ^*≤90°, the primary phase shifter values for the first subarray may be limited to between [0,0,0,…,0] and [0,1,2,…,L-1] π/2^(b_p ) . For example, for L=4 andb_p=3, the primary phase values may be limited to one of the rows of the following matrix. T=[■(0&0&0&0@0&0&0&45@0&0&45&45@0&0&45&90)] The values of the primary phase shifters for the mth subarray can be one of rows of matrix (T+45ml), m = 0, 1,…, M-1, l = 1,…, L i.e., matrix T is shifted up by 45ml. Note that the phase offset, i.e., 45ml, can be performed by a secondary phase shifter. Accordingly, the optimization problem in (5) can be reduced to: min⁡〖 ∑_(m=1)^M▒∑_(l=1)^L▒〖〖|θ〗_((m-1)L+l)+φ_m-kd((m-1)L+l)cos(ϕ)|〗〗 Subject to [θ_((m-1)L+1),…,θ_mL ]∈T , m=1,…,M 〖 φ〗_i∈{((j-1)360°)/2^(b_s ) ,j=1,…,2^(b_s )-1}, i=1,…,M FIG. 44illustrates a process for a phase shifter in accordance with some aspects. An illustration of a process for a steering angle of 85º is provided in FIG. 44for a two subarray, M=2,L=4, 3-bit primary phase shifter. For each subarray, the process may select a row from matrix T, then find an optimal secondary phase shifter value such that the distance between ideal and quantized phases is minimized. As shown, the optimal phase values generally modulate around the ideal phase values. FIG. 45illustrates a phase value determination in accordance with some aspects, showing ideal and quantized phase values for a steering angle 85°. Similar to above, FIG. 45is provided for a two subarray, M=2,L=4, 3-bit primary phase shifter and an infinite resolution secondary phase shifter. As can be seen, the optimized phase values are closer to the ideal value for the antenna indexes. In some aspects, the process may be: T=[■(0&…&0@:&:&:@:&:&:@0&…&(L-1)π/2^(b_p ) )] First, find codebook for steering angles arccos(1/2^(b_p ) )°<ϕ^ ≤90° using: min⁡〖 ∑_(m=1)^M▒∑_(l=1)^L▒〖〖|θ〗_((m-1)L+l)+φ_m-kd((m-1)L+l)cos(ϕ)|〗〗 Subject to [θ_((m-1)L+1),…,θ_mL ]∈T , m=1,…,M 〖 φ〗_i∈{((j-1)360°)/2^(b_s ) ,j=1,…,2^(b_s )-1}, i=1,…,M Then, compute the phase shifter values for angle ϕ_s using codebooks of ϕ obtained above by: ϕ_s=arccos⁡(s/2^(b_p-1) +cos⁡〖(ϕ))〗 θ_m^*←θ_m^*+(m-1)sπ/2^(b_p-1) , m=1,…,ML, and s=-2^(b_p-1),..,-1,0,1,…,2^(b_p-1)-1 or θ_l^*←-θ_l^*, l=1,…,ML, φ_m^*←〖-φ〗_m^*, m=1,…,M An example of the performance for aM=8,L=4 2-bit primary phase shifter resolution and infinite resolution secondary phase shifters is provided below. To compare the process above with the simple quantization: θ_m^ =Q((m-1)kdcos(ϕ)) where ϕ is the steering angle and m is the antenna index, and Q(.) is a b-bit quantizer. FIG. 46illustrates a performance comparison in accordance with some aspects. Specifically, FIG. 46illustrates a comparison in performance between the optimized codebook with simple quantization. As shown, the optimized codebook has 0.5 dB more gain and less grating lobe power than the use of simple quantization. FIG. 47illustrates another performance comparison in accordance with some aspects. In particular, FIG. 47illustrates the power loss of the main beam. As can be seen, the main beam power loss increases relatively slowly as the steering angle moves from 90º when the optimized codebook is used, compared with a simple quantization approach. Using the simple quantization approach results in a rapid drop near 90º and then relatively constant power loss. The optimized codebook may also have a better beam steering accuracy. FIG. 48illustrates a method 26100 of providing beam steering in a communication device in accordance with some aspects. The method 26100 may be performed by the analog or hybrid architecture such as those shown in FIGS. 39A-39Band 253. At operation 26102, the method 26100 may limit a size of a codebook used for beam steering of antennas to a subset of steering angles over which the antennas are to be steered. The antennas may be used to beam steer mmWave signals. In some aspects, the codebook may be limited to steering angles between arccos(1/2^(b_p ) )°<ϕ≤90°, where bp is a number of bits of each primary phase shifter. In some aspects, the codebook may be limited to steering angles between arccos(1/2^(b_p-1) )°<ϕ≤90°. At operation 26104, the processing circuitry may determine the desired steering angle to which to steer the antennas. The processing circuitry may determine that the desired steering angle is within the subset of steering angles or outside of the subset of steering angles. After determining the desired steering angle at operation 26104, at operation 26106, the processing circuitry may determine a limited steering angle within the subset of steering angles. The limited steering angle may be used to apply a control signal to each phase shifter for each antenna. The value used to control each antenna may be independent of the values used for the other antennas. The limited steering angle may correspond to the desired steering angle. The primary phase shifter values may be limited to between [0,0,0,…,0] and [0,1,2,…,L-1] π/2^(b_p ) , where L is the number of primary phase shifters. In some aspects, the range of values of the limited steering angle may further be limited through the use of a unitary multiplier (+1/-1) that indicates whether the particular steering angle is set directly by the limited steering angle and shift value (+1) or whether the particular steering angle is set by a reflection of the limited steering angle and shift value around 180º (-1). After determining the limited steering angle at operation 26106, the processing circuitry may determine a shift value at operation 26108. The shift value may be the value used to shift the limited steering angle to the desired steering angle. Each of the secondary phase shifters may apply the shift value. This may shift a region of the limited steering angle to the appropriate region. In some aspects, the shift value may take positive and negative values or may take positive values that correspond to values provided by a total number of bits of the secondary phase shifters. Note that the operations 26104 and 26106 may occur in any order, as desired. After the limited steering angle and shift values (and perhaps unitary multiplier) are determined, at operation 26110, the processing circuitry may adjust the antennas to the desired steering angle via the primary and secondary phase shifters. The values determined may be applied to the primary and secondary phase shifters. Charge pumps are DC to DC converters that may be used to generate power at a particular level. One or more capacitors are used to store energy to provide the desired power level, with the capacitors connected with a voltage source in a storage mode when energy is to be stored and to a load circuit in a use mode when energy is to be dissipated. FIGS. 49Aand 49Billustrate an aspect of a charge pump in accordance with some aspects. The charge pump 26200 may be incorporated in the radio chain circuitry shown in FIG. 3D, although the charge pump 26200 is not limited to such incorporation. As shown, the charge pump 26200 may be a circuit that uses one or more digital inputs from control logic 26202 to modulate or control an analog output voltage at an output load capacitor 26206. The control logic 26202 may be applied to current sources 26204 disposed on either side of the capacitor 26206 and respectively connected with a voltage rail and ground as shown in FIG. 49A. The control logic 26202 may be responsible for activation of the current sources 26204 that inject charge into the output capacitor 26206 to produce a desired voltage step. Alternatively, the control logic 26202 may be applied to switches 26208, with the capacitor 26206 connected between the switches 26208 and the switches 26208 connected with a different one of the current sources 26204. The control logic 26202 may provide clock-triggered control signals or otherwise triggered to provide pulsed injections of charge to the capacitor 26206. The charge pump 26200 can be used for at least two general alternative purposes or class of applications. The first class of applications may be found in power integrated circuits (ICs) to provide a voltage that is higher than the voltage of the power supply and then produce a higher supply voltage internally to a system-on-a-chip (SoC). The second class of applications may be broader and aims to generate a voltage that is within the supply rails. This latter class of applications may be finely controlled at a clock or other digitally controlled rate. FIG. 50illustrates an aspect of a charge pump 26300 in accordance with some aspects. The charge pump 26300 may be used for the second class of applications described above. The charge pump 26300 may be provided in basic circuits such as comparators or phase-frequency detectors or bigger systems such as frequency synthesizers or ADCs that represent building blocks in a front end of a communication device. The charge pump 26300 may be incorporated, for example, in high-speed transceivers such as mmWave transceivers and the like for wireless standards. While the charge pumps in power ICs may be employed at a high frequency and with an adjustable clock to increase their output power within a reasonable size of total capacitance used for charge transfer and the operating frequency, in mixed signal applications such as phase locked loops (PLLs), frequency locked loops (FLLs) or ADCs, the operating frequency may be unable to be adjusted easily since the operating frequency may be set by the circuit operating rate (the reference clock in PLLs and the sampling clock in ADCs). Thus, charge pumps may operate within the frequency range expected for the application. In addition, to be adopted in SoC for wireless standards and portable applications such as those for the Internet of Things (IoT), certain features are desirable. Aspects disclosed herein include charge pumps that may be compact in terms of circuit area to help avoid impact on SoC area and power efficiency. These may be of interest for comparators and ADCs charge pumps since they may serve as ancillary calibration circuits that may not be dominant in terms of area and in terms of power consumption. Charge pump topologies may use two input signals (UP-DOWN) originating from a finite state machine, in addition to switches, current generators and a capacitor. For high speed applications, designing charge pumps with fine voltage regulation, low power consumption, compact area and high speed may involve a number of considerations. For example, fast and accurate response may be affected by capacitive coupling effects between control signals and an output node. Current generators and references may consume static power and use complex circuitry to help ensure current accuracy. Accurate current mirrors for the current references may use large devices for good matching, and the generation of low (nA range) and accurate currents in highly scaled CMOS processes may be difficult due to leakage phenomena. Fine resolution may use either very low current and/or large output capacitance, e.g., more area, and the high-speed low-resistive switches used are more likely to introduce switching noise. In some cases, it may therefore be appropriate to, among others, avoid the use of a current generator in a charge pump. The charge pump 26300 of FIG. 50may be provided in a communication device, such as a UE, eNB or AP. The charge pump 26300 may exploit capacitive coupling effects and subsequent sub-threshold injection instead of using current generators to inject the desired charge on an output capacitor 26320. This permits the amount of injected charge per step to be able to be small without the use of accurate low current generators or a DC biasing circuit, as well as limiting the output noise. The charge pump 26300 may contain control logic 26302 that may provide two control signals (UP/DOWN). The control logic 26302 may be in a baseband processor in the communication device, or may be logic separate from the baseband processor. The control logic 26302 may be connected with a pair of dynamically driven switches 26310 through digital logic. The dynamically driven switches 26310 may be connected to a set of one or more pMOS (MP) and nMOS (MN) subthreshold switches 26312. The set of switches 26312 may be configured by preset bits to be on or off. The preset bits may be for the equivalent length of the MP2 and MN2 devices (DP and DN), the pulse-width of the control signals (ddel,N, ddel,P) and the output capacitor (Dc) 26320. Any number of switches 26312 may be used, with the eventual resulting change in output voltage being finer as the number of switches 26312 increases. In some aspects, one to five switches 26312 may be used due to power considerations, among others. In some aspects, the preset bits may be preprogrammed during device testing and stored in a non-volatile memory of the communication device. In some aspects, the calibration (and thus value of the preset bits) of the charge pump 26300 may be determined during a power up sequence of the communication device and/or in the background when the communication device is in operation. The communication device may recalibrate the charge pump 26300 after a certain number of cycles and/or as a function of temperature. As the capacitive coupling and subthreshold current may be temperature dependent, calibration may occur for different temperatures. In some aspects, different values of the preset bits may be stored in memory, with each set of preset bits to be used at a different temperature of the charge pump 26300. The different sets of preset bits may be used either when a particular temperature has been reached, or when the temperature change of the charge pump 26300 meets a predetermined threshold. Timing circuitry 26316 may connect the control logic 26302 and each of the dynamically driven switches 26310 for both the UP and DOWN control signals. The timing circuitry 26316 may include a delay line 26304 that may receive the control signal from the control logic 26302 (or other processor) as an input and can be programmed to set the pulse width of the control signals using the preset bits. The output of the delay line 26304 may be fed to the input of an inverter 26306. The output of the inverter 26306 may be supplied to an input of an AND gate 26308, whose other input may be supplied with the control signal from the control logic 26302. This may control the pulse width as the inverted output from the inverter 26306 may be delayed by an amount of time configured by the delay line 26304. The output capacitor 26320 may comprise a plurality of capacitor-switch combinations in parallel. The switches may be activated/deactivated, as above, by the preset bits, thereby adjusting the capacitance of the output capacitor 26320. Each capacitor of the output capacitor 26320 may be between about 0.5 to about 10 fF, for example. Exemplary manners of charging and discharging the output capacitor 26320, thereby providing a controllable output voltage, are described in reference to FIGS. 51A– 53B. The aspect depicted in FIG. 50may not contain and use any analog current sources and may be implemented in any scaled CMOS technology with limited matching and accuracy. In some aspects, means for injecting charge across a gate-drain capacitance of a dynamic switch may be implemented by the charge pump 26300. In some aspects, as shown, the charge pump 26300 may further implement means for transferring the charge across a subthreshold switch to an output capacitance of the charge pump using subthreshold drain current after injection of the charge and means for terminating the charge transfer and current flow in the output capacitance to stop a voltage change of an output voltage after transfer of the charge, e.g., by the switches 26312 and control logic 26302. In some aspects, as shown, the charge pump 26300 may further implement means for controlling a pulse width of a control signal during the charge injection phase, e.g., via the timing circuitry 26316, which may comprise means for supplying the control signal and a delayed inverted copy of the control signal to an AND gate, and a set of preset bits to control an amount of delay of the delayed inverted copy of the control signal. In some aspects, as shown, the charge pump 26300 may further implement means for transferring the charge to the output capacitance across a number of subthreshold switches equal to a number of preset bits of the set of preset bits and/or means for controlling incorporation of a number of parallel internal capacitors to form the output capacitor, e.g., via the output capacitor 26320. FIG. 51Aillustrates a scheme of an output portion of a charge pump 26400 in accordance with some aspects. FIG. 51Billustrates a timing diagram of signals of the charge pump 26400 in accordance with some aspects. The charge pump 26400 may contain a pair of dynamic switches 26410 to which an UP or DOWN control signal may be supplied. The dynamic UP switch 26410 supplied with the UP control signal may be connected to the supply voltage (or one of the rail voltages/rails) and the dynamic DOWN switch 26410 supplied with the DOWN control signal may be connected to ground (or the other of the rails). The MP and MN switches 26412 may be respectively connected between the dynamic UP switch 26410 and the output capacitor 26420 and between the dynamic DOWN switch 26410 and the output capacitor 26420. In some aspects, when no control signals are supplied to the output portion shown in FIG. 51A, the MN1 and MP1 switches 26412 may both be on. The charge pump 26400 may tie nets an and ap, e.g., interconnections, shown in FIG. 51Arespectively to ground and Vcc through low channel resistances RON,n, and RON,p. In this situation, Vout may still be isolated from the supply rails through the MP2 and MN2 switches 26412 whose state is preset to off, and may offer a very high resistive path between nets an, ap and Vout. As shown in FIG. 51B, the output voltage of the capacitor 5120 can change under the occurrence of a desired control signal. The p-branch of charge pump 26400, which may be controlled by the control signal UP, devices MP1, MP2 switches 26410, 26412 and the output capacitance Cout of the output capacitor 26420 may be used to increase the output voltage. The output capacitor 26420 may be initially charged to half the dynamic Vcm. The UP control signal may be low in a “sleep” mode. Each time an UP control signal is supplied to MP1 switch 26412, the voltage at net ap may result in a pulse Vap over the same time period primarily because of charge injection and/or clock feed-through. The pulse Vap may result in a subthreshold or leakage current through MP2 switch 26412, and eventually a positive step increase of Vout of the output capacitance Cout of the output capacitor 26420 through the charging of the output capacitor 26420. Similarly, each time a DOWN control signal is supplied to MP2 switch 26412, the voltage at net an may result in a negative pulse Van over the same time period. The pulse Vanp may result in a decrease of Vout of the output capacitance Cout of the output capacitor 26420. The increase and decrease of the output capacitance Cout of the output capacitor 26420 may be symmetric. FIGS. 52A-52Cillustrate exemplary operations of a charge pump according to some aspects. FIG. 52Ashows parasitic capacitances of the p-branch of the circuit when the output capacitor is charging. FIG. 52Bshows a circuit model of the p-branch when the output capacitor is charging. FIG. 52Cshows a timing diagram of the p-branch. As shown in FIG. 52A, on the positive edge of the UP signal, the pMOS switch 26510 is turned off, and the voltage at net ap enters a high impedance state. At the same time, charge may be injected through the gate-drain capacitance of MP1 switch 26510 (Cgd,mp1), which results in a positive voltage step spike on net ap and the MP2 switch 26512 source. The other leakage capacitors associated with MP1 switch 26510 may be related to the gate, drain and source of the switches 26510, 26512 – i.e., Cgd,mp1, Csg,mp2, Csb,mp2, Csd,mp2 (for sake of generality). Cap 26514, shown in FIG. 52B, may group together the parasitic capacitors affecting net ap as a single modeled capacitor. In general, due to indirect capacitive coupling through Csd,mp2 it may be possible that any steep edge of the UP signal at the MP1 gate couples directly to the output. However, since Csd,mp2 may be very small compared to the other device parasitic capacitances (both intrinsic and layout associated), and since the bulk and the gate of MP2 switch 26512 may be low-impedance nets (Vcc) such phenomena can be considered negligible. For example, an amount of direct charge injection associated with the edges of the control signal, which could be significant, may be avoided. In addition, when UP rises, MP1 switch 26510 may be turned off. In this case, net ap may become a high impedance net that is subject to a charge injection due to the control signal edge. The variation of the voltage of net ap correspondent to the UP positive edge may be (when the pMOS MP1 switch 26510 is OFF) approximately given by: 〖∆V〗_ap=〖∆V〗_UP∙C_(gd,MP1)/(C_(gd,MP1)+〖〖C_(p,ap)+C〗_(sd,MP2)//C〗_out )≅V_cc∙C_(gd,MP1)/C_(p,ap) while the output voltage is still stable. After this operation, the net ap voltage may settle at a value that can be a few 10mVs to 100mV higher than the power supply level. Due to the consequent increase of Vsg,MP2,a subthreshold current may flow both through MP2 switch 26512 (and MP1 switch 26510 as well). The subthreshold current may contribute to a discharge of Cp,ap and a ∆Vdrop,p ap net voltage drop. The portion of current flowing through MP2 switch 26512 may feed to the output capacitor 26520, determining an increase of the output voltage. This charge may cause the positive step at the output voltage and may be basically transferred from Cp,ap to Cout. When the UP negative edge occurs, pMOS MP1 may again turn on. First, charge may be drawn by net ap through the Cgd,mp1 coupling path. This may determine a step down in the net ap voltage and a Cp,ap discharge to a voltage that is close to the initial value Vcc, minus ∆Vap. Meanwhile, with a small delay due to the channel resistance-associated time constant, MP1 switch 26510 may return to the ON state and pull net ap back to Vcc. The charge to pull back net ap to Vcc may be provided entirely by the supply and not drawn back from the output capacitance. Also in this step, no direct charge injection may occur to the output node, and the MP2 subthreshold current may stop flowing into Cout, thereby freezing the output voltage to the last, higher, value. As a new UP pulse occurs, the described transient may repeat. This may lead to another positive step of the output voltage occurring. To summarize, the operating principle of the p-branch of the charge pump can be synthesized and described in a few steps. FIGS. 53A-53C illustrate an exemplary operation of a charge pump according to some aspects. FIG. 53Aillustrates the charge injection phase. The charge injection phase may occur on the positive edge of the UP control signal. At this edge, MP1 may turn off, and the net ap voltage may increase and induce a positive Vsg,MP2. FIG. 53Billustrates the charge transfer phase. The charge transfer phase may occur after the charge injection phase. In particular, in the charge transfer phase, the subthreshold drain current of MP2 may transfer charge from Cp,ap to Cout determining an increase in the output voltage Vout. FIG. 53Cillustrates the shutdown phase. The shutdown phase may occur after the charge transfer phase. In particular, the shutdown phase may occur on the negative edge of the UP control signal, whose delay with respect to the positive edge may be controlled by the delay line 26304. At this point in time, MP1 may turn on, and the net ap voltage may return to Vcc. At this point, any current flow in Cout may cease. A three-operation model and analysis can be extended to the nMOS branch including MN1, MN2, the DOWN control signal and net an. In the nMOS branch instead of charging net ap to Vcc+Cout, the nMOS branch may determine a drop of net an voltage to a negative voltage. In some aspects, the maximum amount of charge that can be transferred during each operation may be the charge injected into Cp,ap during the charge injection phase: 〖∆V〗_ap 〖∙C〗_(p,ap)≅V_cc∙C_(gd,MP1) Considering a 1V supply, an output capacitance of 50pF and a 50fF gate-drain capacitance of MP1, the charge would correspond to a 1mV output voltage step. While the charge stored initially on Cp,ap may not depend on the Cp,ap size, the corresponding increase in the voltage of net ap may, on the contrary, depend on the Cp,ap size. This may in general affect the amount of current that MP2 is able to inject into the output capacitance during the charge transfer phase. In the design and sizing phase of this circuit, some solutions can be adopted to determine the step size and thus the sensitivity of the circuit. Since the sub-threshold current of the devices may depend linearly on the length of the transistors, the length of MP2 can be sized as desired. Alternatively, more devices can be placed in series in situations in which the fabrication process does not allow freedom in the sizing of the device length. Since the charge injected at the output capacitor may also depend on the duration of the charge transfer phase, a pulse-width controller with a programmable delay line as shown in FIG. 50can be introduced to control the waveform of the UP and DOWN signals. This may enable transfer of a large or complete amount of the available charge to the output. In some circumstances, an insufficient pulse-width may result with a charge transfer that is too small. Since the amount of the charge injection during the charge injection phase may depend on the gate-drain capacitance of MP1 (or MN1 in the nMOS branch), the MOS can be sized as desired. Since the output voltage step at a fixed amount of injected charge may depend on the size of the output capacitance, the output capacitance may be programmed using a configurable capacitive array. Simulations were performed on a charge pump implemented in a 14nm FinFET 10-bit ADC test-chip for comparators background calibration. The adopted output capacitance was 50fF. To verify this, emphasis has been dedicated to fast corner simulations. The pulse-width of an alternating series of UP and DOWN control signal was set to 50ps, the output capacitance to 50fF and the update rate was 1 GHz. Simulations were performed under nominal, fast, and slow corner at 27°C. The voltage step seen was about 600V (comparable with the LSB of a >11-bit fully differential, rail-to-rail converter) and stable across corners. The circuit, in general, may be compatible with higher resolution applications. To prove programmability, even in the presence of unfavorable conditions in terms of leakage currents (fast corner), simulations were performed with a focus on the p-branch, varying the size of the MP1 device, the pulse-width of the control signals and the equivalent length of the MP2 device. Simulations were performed, for a fast corner, 27°C, to determine the output voltage variation during a sequence of UP commands at 1 GHz rate, a constant 50ps UP pulse-width, for the implemented prototype, and for different widths of the MP1 device width. For an MP1 device width of 42nm, 84nm, 168nm, 336nm, the corresponding voltage steps were determined to be respectively 600µV, 1mV, 1.3mv, 1.5mV. Simulations were also performed to determine the output voltage variation for UP commands at a 1 GHz rate using different pulse-widths. These latter simulations performed on a device having a 42nm/28nm MP1/MP2 aspect ratio for a 20ps to 800ps UP signal pulse-width showed a linear relationship between pulse-width and output voltage. Further simulations were performed to determine the charge pump output voltage during a sequence of UP commands at 1 GHz rate, a constant 50ps UP pulse-width, for different widths of the MP2 device (56nm, 84nm, and 112 nm). The charge pump output voltage varied linearly with time and scaled approximately with MP2 width. The power consumption of the charge pump at an update rate of 1GS/s as shown in the simulations is less than 10µW in nominal corner and 27°C, and thus is negligible if compared to a GHz rate state-of-the art efficiency ADCs and PLLs. According to some aspects, charge pumps are thus provided that help avoid the use of a current reference or charge accumulation/storage devices other than the output capacitance. The charge pump may be suitable for PLL and ADC comparator offset calibration applications, and in general for all applications where fast rate (>1GS/s), fine resolution (<1mV) and ultra-low power consumption, for example, are desired. Some aspects may be used in ultra-low power PLLs, reducing the circuit area, and may also be used to perform a high-efficiency comparator calibration for high speed ADCs. FIG. 54illustrates a method 26700 of injecting charge in a charge pump in accordance with some aspects. The method 5400 may be performed by any one or more of the structures shown in FIGS. 49A-267. At operation 26702, charge may be injected into the structure(s). The charge may be injected across a gate-drain capacitance of a dynamic switch (MOSFET) during a charge injection phase. The charge injection may occur across a gate-drain capacitance of the dynamic switch on a positive edge of a control signal supplied to the dynamic switch. The charge injection may be controlled by controlling a pulse width of a control signal. In some aspects, the pulse width of the control signal may be controlled by supplying the control signal and a delayed inverted copy of the control signal to an AND gate, and a set of preset bits to control an amount of delay of the delayed inverted copy of the control signal. At operation 26704, after injection of the charge, the charge may be transferred across a subthreshold switch to an output capacitance of the charge pump. The charge may be transferred using subthreshold drain current during a charge transfer phase. During the charge transfer phase, the charge may be transferred to the output capacitance across a number of subthreshold switches equal to a number of preset bit of the set of preset bits. Each preset bit may control a different subthreshold switch. In addition, the number of parallel internal capacitors may be controlled to form the output capacitor using a different preset bit. After the charge has been transferred, at operation 26706 the charge transfer and current flow in the output capacitance may be terminated. This may stop the voltage change of the output voltage during a shutdown phase. The termination may occur on a negative edge of the control signal supplied to the dynamic switch. A voltage at a net between the dynamic switch and the subthreshold switch may return to a rail voltage to which the dynamic switch is connected. As mmWave communication systems rely on multiple directional transmissions over multiple paths, mmWave receivers may experience interference from different directions when the network becomes dense. To help address this, as described above, receivers may use analog, digital or hybrid beamforming. Analog beamforming may in some cases be insufficient to mitigate omni-directional interference due to high side-lobes and wide beam width, and digital domain beamforming is not sufficient to mitigate interference since interference may block the desired signal at low-resolution ADCs (low dynamic range). To mitigate this, aspects disclosed herein provide an architecture to help null out interference before quantizing to reduce the dynamic range and power consumption of ADC at the receiver. For example, a feedforward loop is provided for spatial interference mitigation so that coarsely quantized received signals may be processed to estimate high interference and then subtract the interference in analog domain. The nulling may be enabled for multiple interference angles, without using a long training sequence for iterative filter design at the ADC feedback loop. This may enable a low power fully digital mmWave receiver. FIG. 55illustrates a receiver architecture 26800 in accordance with some aspects. The receiver architecture 26800 may be incorporated in the parallel receive circuitry 382 shown in FIG. 3E, although the receiver architecture 26800 is not limited to such incorporation. The receiver architecture 26800 shown in FIG. 55may contain, for example, an RF front end 26820, delay lines 26802, sets of combiners 26810, 26812, 26814, 26818, sets of quantizers 26804, 26816, a feedforward filter 26806, digital-to-analog converters (DACs) 26808 and a baseband processor 26830. RF signals may be received by an antenna (not shown) and provided to the RF front end 26820. A plurality of antenna outputs r_i (t), i=1,…,N_r may be provided by the RF front end 26820 and may be split into two paths, one for determination of the interference and one for nulling. Specifically, each antenna output may be supplied both to one of the delay lines 26802 and to one of the first combiners 26810. The analog delay line 26802 may include a plurality of tapped latches (e.g., D latches) to enable the delay to vary by taking the output from different taps. Alternatively, the delay length may be fixed, with the only output of the analog delay line 26802 being taken from the last latch. At the first combiner 26810, the dithering noise for interference n_1 may be added to the antenna output. The dithering noise n_1 may depend on an estimate of the interference, which may be determined prior to providing the interference nulling. The output from the first combiner 26810 may be supplied to a b_1-bit quantizer 26804, which may coarsely quantize the analog signal and convert the analog signal to a digital signal. The quantized signal may then be provided to the feedforward filter 26806 prior to being digitized by the DAC 26808. The feedforward filter 26806 may be a multitap filter used to process the received quantized signal and estimate the interference signal. The interference signal may then be converted back into an analog signal by a d-bit DAC 26808. The resolution of the DAC 26808, like the quantizers 26804, 26816 may be fixed or variable. In the latter case, the resolution of one or more of the DAC 26808 and quantizers 26804, 26816 may be dependent on signal type (e.g., control/data) or channel conditions, among others. The converted interference signal may then be subtracted from the delayed antenna output from the analog delay line 26802 at the second combiner 26812 to produce a corrected signal. Dithering noise n2 may be added at the third combiner 26814 to the corrected signal, prior to quantizing the dithered corrected signal. The dithering noise n_2 may be dependent on receiver performance, which may be measured using one or more signal quality characteristics. For example, the dithering noise n_2 may be dependent on the BER performance. A b_2-bit quantizer 26816 may be used to quantize the dithered corrected signal. In some aspects, a resolution of the b_1-bit quantizer 26804 may be less than resolution of the b_2-bit quantizer 26816. The use of a coarse resolution to generally determine the interference may permit a reduction in power used by the receiver, as well as reducing the dynamic range of the in-line quantizer after compensation of the beamformed signal. The quantized signal from the quantizer 26816 may then be supplied to a baseband processor 26830 for further processing. The output from the quantizer 26816 and the interference signal from the feedforward filter 26806 may be combined at the fourth combiner 26818 to generate a Received Signal Strength Indicator (RSSI). The RSSI may be determined based on all of the quantized outputs (from each of the b_2-bit quantizers 26816 and from each of the outputs of the filter 26806) or may be based on fewer than all of the outputs. The RSSI may be used, for example, to adjust one or both the quantizer resolutions, the DAC resolution and/or the one or both dithering noise. The receiver shown in FIG. 55may thus be able to simultaneously mitigate (or null) from multiple interference sources in multiple beamformed signals without the addition of other components, such as phase shifters to form multiple analog beams. The receiver may also be able to mitigate interference without the use of a filter whose coefficients depend on a desired and interference signals, and thus use of a long training sequence. In some aspects, means for receiving beamformed signals from a plurality of antennas may be implemented by the receiver architecture 26800. In some aspects, as shown, the receiver architecture 26800 may further implement means for forming compensated signals by feedforward compensating the beamformed signals for the interferer signals, prior to quantizing compensated signals for output, e.g., via the feedforward routing in the receiver architecture 26800, and means for quantizing the compensated signals to form quantized output signals, e.g., via the quantizer 26816. In some aspects, as shown, the receiver architecture 26800 may further implement one or more of: means for quantizing the beamformed signals along the feedforward path to form quantized feedforward signals, means for compensating for the interferer signals in the quantized feedforward signals to provide digital compensation signals, e.g., via the filter 26806, means for converting the digital compensation signals to analog compensation signals, e.g., via the DAC 26808, and/or means for combining the analog compensation signals with the beamformed signals to form the compensated signals, e.g., via the combiner 26812. In some further aspects, as shown, the receiver architecture 26800 may further implement one or more of: means for adding first dithering noise to the beamformed signals prior to the quantizing the beamformed signals and means for adding second dithering noise to the compensated signals, e.g., via combiners 26810 and 26814; means for combining the digital compensation signals and digital versions of the compensated signals to provide a signal quality and means for controlling, based on the signal quality, at least one of: quantization of the beamformed signals, quantization of the compensated signals, the first dithering noise or the second dithering noise, e.g., via baseband processor 26830 and combiner 26818; means for estimating interference from each direction from: (i_k ) ̂[n]=a_r^H (θ_k )y[n], e.g., via baseband processor 26830 and/or means for delaying the beamformed signals sufficiently to permit the beamformed signals to be combined with the analog compensation signals, e.g., via the delay line 26802. Mathematically, consider uniform linear array with N_r antennas at the receiver. The received signal can be written as follows: r(t)=x(t)+i_1 (t) a_r (θ_1 )+⋯+i_I (t) a_r (θ_I )+n where x(t) is the desired signal vector, n is noise vector, and i_i (t),i=1,…,I, are the interference signals (I is the number of interferer directions) and array vector a_r (θ_i ),i=1,…I, is given by: a_r (θ_i )=〖1/√(N_r ) [1,e^(j 2π/λ d cos⁡〖θ_i 〗 ),e^(j 2π/λ d2 cos⁡〖θ_i 〗 ),…,e^(j 2π/λ d (N_r-1)cos⁡〖θ_i 〗 ) ]〗^T, Here, θ_i is the angle of arrival, d is the inter-antenna distance, and λ is wavelength. At the feedforward loop, noise may be added to de-correlate the received signal at the output of antennas and then the signal quantized, e.g., with a low bit (1-3 bit) ADC as follows: y[n]=Q_1 (r(t)+n_1 ) where n_1 is the dithering noise vector, Q_1 (∙) is the b_1-bit quantizer. The interference k may be estimated in the feedforward filter using an estimation vector. In some aspects, the estimation vector may use maximum ratio combining (MRC): (i_k ) ̂[n]=a_r^H (θ_k )y[n],k=1,…,I where a_r (θ_k ) is the estimation vector of interference from direction θ_k. The direction of interference may be determined using a digital process, such as the MUltiple SIgnal Classification (MUSIC) process. I may be total number of interference directions (interferers). Note that the receiver is considered to have a large antenna array so that a_r^H (θ_k ) a_r (θ_l )≅0 when l≠k. Then, a vector may be formed according to the angle of arrival as the following: i[n]=(i_1 ) ̂[n] a_r (θ_1 )+⋯+(i_I ) ̂[n] a_r (θ_I ) After digital samples are converted to the analog domain using d-bit DAC, the interferences may be subtracted from the received signal and dithering noise n_2 added before quantizing at the b_2-bit ADC as the following: 〖z[n]=Q〗_2 (r(t)-i(t)+n_2 ) FIG. 56illustrates the filter characteristic of a receiver according to some aspects. In the simulated filter, N_r=64 antennas and d=5 bits DAC, b_2=5 bits ADC, and two interference directions are present at θ=70° and θ=110°. Two cases are shown: case 1: a 1 bit ADC (b_1=1,) n_1~N(0,0.4σ_r^2), n_2~N(0,0); and case 2: a 2-bit ADC n_1~N(0,0.3σ_r^2), n_2~N(0,0). As shown, the receiver architecture can cancel interference of up to about 13.6dB when a 1-bit ADC is used, and up to about 23.32 dB when a 2-bit ADC is used. FIG. 57illustrates the BER performance of a receiver according to some aspects. The graph shows the BER performance of analog beamforming, digital beamforming and the architecture of FIG. 55. As above, N_r=64 antennas at the receiver in the line of sight (LOS) channel with 90° desired signal direction and 70° and 110° interference directions with SIR=-20dB. A 16QAM modulation is used, and the ADCs used are: b_1=2 bits ADC, d=5 bit DAC, b_2=5 bit ADC. The variance of Gaussian dithering noise may be chosen by the processing circuitry to randomize the quantization error. The bandwidth is 1 MHz, and interference and desired signal may communicate over the same band. A pulse shaping filter is a square root raised cosine filter with a filter length of eight symbols and a rolloff factor of 0.2. As shown in FIG. 57, a digital receiver without spatial interference cancellation before the ADC has a lower BER performance due to having an insufficient dynamic range. The analog beamforming also performs worse than the architecture of FIG. 55due to high side-lobes. FIG. 58illustrates additional receiver architectures according to some aspects. As above, N_r=64 antennas at the receiver in the line of sight (LOS) channel with 90° desired signal direction. A 16QAM modulation is used, and the ADCs used are: b_1=2 bits ADC, d=5 bit DAC, b_2=5 bit ADC. In this case, a 75° interference direction with SIR=-13dB was used. When a 1-bit ADC is used at the feedforward loop, the architecture of FIG. 55performs better than the analog and fully digital beamforming. FIG. 59illustrates a method 27200 of compensating for interferers in a receiver in accordance with some aspects. The method 27200 may be performed using the receiver of FIG. 55. At operation 27202, the receiver may receive beamformed signals from a plurality of antennas. The beamformed signals may be scanned over a range of angles. Each of at least some of the beamformed signals at a particular angle may comprise a signal from a transmitter and an interferer signal. The beamformed signals may be split to different routes before being recombined. In a feedforward route, the beamformed signals may be quantized and the interference estimated using a filter to form digital compensation signals at operation 27204. Prior to quantizing the beamformed signals, dithering noise may be added to de-correlate the signal. The digital compensation signals may then be converted to form analog compensation signals. In the direct path, the original beamformed signals may be delayed to provide the appropriate timing for combining the signals. At operation 27206, the beamformed and analog compensation signals may be combined. In some aspects, the analog compensation signals which may contain the interference estimation, may be subtracted from the beamformed signals. Dithering noise may be added to the resulting signals, and these signals may then be quantized. The resolution of quantization of the beamformed signals may be lower than the resolution of quantization of the compensated signals. At operation 27208, the quantized resulting signals may be supplied to a baseband processor for processing. The quantized resulting signals and the digital compensation signals may be combined to determine a signal quality, such as RSSI, SINR or SNR. This quality may be used to control the quantization of the beamformed signals, quantization of the compensated signals, and/or dithering noise. In addition to beamforming, channel estimation between transmitter and receiver antenna pairs may further increase the digital beamforming complexity. Digital architectures may also suffer performance degradations when there is in-band and adjacent channel interference. FIGS. 60Aand 60Billustrate interference in accordance with some aspects. As shown in the system 6000 in both figures, a base station (BS) 27302 may serve a UE 27304, providing data and control signals. Although only LOS communications are shown, the BS 27302 may also communicate with the UE 27304 through NLOS communications. A neighboring BS 27306, which may also be an access point, may generate interfering signals at the UE 27304. The interfering signals, like the serving BS 27302 communications, may be LOS or NLOS and may interfere with the signals from the serving BS 27302. Instead or in addition to interfering signals from the interfering BS 27306, one or more interfering UEs 27308 may generate interfering signals at the UE 27304. The interfering signals from the interfering UE 27308 may be directed to the serving BS 27302, the interfering BS 27306 or the UE 27304. Unlike digital beamforming, analog beamforming may be limited to directivity gain due to the single RF chain used. Analog beamforming may, however, in some cases be insufficient to mitigate omni-directional interference due to high side-lobes and wide beam width, and digital domain beamforming is not sufficient to mitigate interference since interference may block the desired signal when low-resolution ADCs (low dynamic range) are used. This is to say that interference from one or more directions may be so much larger than the desired signal that the interference may overwhelm the dynamic range of the ADCs, which may be adequate to discriminate the desired signal in other directions, when the antenna elements are set at or near the direction of the interference. This may be particularly prevalent when mmWave frequencies are used due to the rapid interference and signal quality changes for LOS and NLOS channels caused by UE movement. Increasing the dynamic range of the ADCs, however, may be power intensive and difficult to design. To mitigate this, aspects disclosed herein provide an architecture that may help null out interference before quantizing and may subsequently digitally invert the adjustment to permit the original signal to be digitally processed. This may enable a reduction of the ADC dynamic range and power consumption of the ADCs at the receiver when such interference is present. The signal may be sampled at the quantizer, thereby the received signal may be processed in the digital domain and the interference canceled in the analog domain. Parallel delta-sigma ADCs with a feedback loop may be used to enable a low power, fully digital mmWave receiver. FIG. 61illustrates a receiver architecture 27400 in accordance with some aspects. The receiver architecture 27400 may be incorporated in the parallel receive circuitry 382 shown in FIG. 3E, although the receiver architecture 27400 is not limited to such incorporation. The receiver architecture 27400 shown in FIG. 61may contain, for example, an RF front end 27410, combiners 27402, sets of low pass filters (LPFs) 27404, 27412, sets of gains 27406, 27422 quantizers 27408, decimators 27414, a filter 27416, DACs 27418 and a baseband processor 27420. RF signals may be received by antennas 27430 containing multiple antenna elements and provided to the RF front end 27410. The RF signals r_i [n], i=1,…,N_r may be outputs from the antenna 27430. The RF signals may be indicated as a uniform linear array from N_r antennas at the receiver architecture 6100. N_r may be selected dependent on a beamforming gain and power consumption at the receiver architecture 27400. The received signal can be written as follows: r(t)=x(t)+α_1 i_1 (t) a_r (θ_1 )+⋯+α_I i_I (t) a_r (θ_I )+n where x(t) is the desired signal vector, n is a noise vector, and i_i (t),i=1,…,I, are the interference signals, where I is total number of interference directions that are to be nulled out. The angular vector a_r (θ_i ),i=1,…I, may be given by: a_r (θ_i )=〖1/√(N_r ) [1,e^(j 2π/λ d cos⁡〖θ_i 〗 ),e^(j 2π/λ d2 cos⁡〖θ_i 〗 ),…,e^(j 2π/λ d (N_r-1)cos⁡〖θ_i 〗 ) ]〗^T, where θ_i is the angle of arrival and d is the inter-antenna distance between antennas 27430. Each of a plurality of antenna outputs r_i (t), i=1,…,N_r provided by the RF front end 27410 may be supplied to one of the combiners 27402. A modified signal from the decimator 27414, described in more detail below, may be combined with the antenna output from the RF front end 27410. This modified signal at least partially mitigates the interference prior to quantization of the received signal, and thereby permits a reduction in the dynamic range of the quantizer 27408. The combiner 27402 may be formed by an integrator in the analog domain and may form a portion of compensation circuitry. The combined signal may be supplied from the combiner 27402 to the first LPF 27404. The first LPF 27404 may shape the quantization noise in the combined signal to out-of-band. The signal from the antenna 27430 may be mixed to baseband prior to reaching the first LPF 27404, such as in the RF front end 27410. The low pass filtered signal from the first LPF 27404 may be supplied to a variable gain 27406. The gain output for the different antenna signals may be indicated as g_i [n], i=1,…,N_r. The gain 27406 may provide amplification or attenuation to the low pass filtered signal to adjust the input to the quantizer dynamic range. The gain 27406 may be optimized depending on the channel or channel quality (such as SNR or SINR), or in some aspects can be set to fixed gain for a low complexity receiver. The gain 27406, like the desired signal and interference, may vary over time. The signal from the gain 27406 may subsequently be provided to quantization circuitry comprising a b_1-bit quantizer 27408. The quantizer 27408 may provide a b-bit digital version of the signal. b may be selected dependent on a desired BER and filter characteristic. In some aspects, the quantizer resolution may be variable, dependent on, among others, whether high speed or high reliability is desired, such as the type of signal (e.g., control or data) or an operation mode of the quantizer 27408 (such as averaging or time-interleaved mode). The output of the quantizer 27408 with b_i [n], i=1,…,N_r bits may thus be, i.e., b_i [n]=Q_b (g_i [n]). The output from each of the quantizers 27408 may form B, a data matrix used for filtering the interference. In some aspects, the data matrix B may be filtered (or weighted) by a filter 27416 prior to being fed back to mitigate the interference. The filter 27416 used may be, e.g., dependent on the direction of arrival of the interference, as well as time-based. The filtered signal may be supplied to the DAC 27418, which may convert the d-bit digital signal to an analog output. Similar to the above, d may be selected dependent on a desired BER and filter characteristic. In some aspects, the DAC 27418 may use the same number of bits to convert the digital input to an analog signal as the quantizer 27408 uses to convert the analog input to a digital signal. In other aspects, the number of bits used by the quantizer 27408 and the DAC 27418 may be different. In some aspects, the resolution of the conversion may be variable, dependent on similar factors as used for quantization. The relative difference between the quantization resolution and the conversion resolution may change with the above factors. The analog output from the DAC 27418 may be supplied to the second gain 27422 c_i [n], i=1,…,N_r. The second gain 27422 may be optimized depending on the channel or SNR, or in some aspects can be set to fixed gain for a low complexity receiver. The second gain 27422, as above, may provide amplification or attenuation, and may vary over time. The modified signal from the DAC 27418 may then be subtracted from the signal from the RF front end 27410, as indicated above. The signal from the quantizer 27408 b_i [n], i=1,…,N_r may also be supplied to the second low pass filter 27412. The second low pass filter 27412 may be used to remove harmonics introduced by the quantizer 27408. In some aspects, the quantizer 27408 may oversample the input signal. In these aspects, the signal from the second low pass filter 27412 may subsequently be decimated at the decimator 27414 before being supplied to the baseband processor 27420 for further processing. The decimator 27414 may reduce the sampling of the digital data down to the Nyquist rate. Decimation may process the digital to down sample the signal to have a low pass characteristic. In some aspects, the quantizer 27408 may avoid oversampling, and the decimator 27414 may be eliminated. In some aspects, the baseband processor 27420 may invert the filter to essentially restore the signal to that of the original signal from the antennas 27430, within errors caused by quantization. This may permit the baseband processor 27420 to digitally process the original signal, such as through digital cross-correlation, without the original signal being supplied to the quantizer 27408. Instead, a compensated signal that compensates for the interference in the analog domain may be provided to the quantizer 27408, thereby reducing amplitude spikes associated with the interference and permitting the dynamic range of the quantizer to be reduced. In some aspects, means for receiving a plurality of beamformed signals from a plurality of beamforming antennas may be implemented by the receiver architecture 27400. In some aspects, as shown, the receiver architecture 27400 may further implement for each beamformed signal: means for reducing the dynamic range of a quantizer to which the beamformed signal is supplied by compensating the beamformed signal for interference from an interferer prior to the beamformed signal being provided to the quantizer and providing a compensated signal to the quantizer, e.g., by the feedback loop shown; means for quantizing the compensated signal, e.g., by quantizer 27408; means for digitally inverting compensation applied to the beamformed signal to regenerate a digital version of the beamformed signal and means for signal processing the digital version of the beamformed signal, e.g., by BB processor 27420. In some aspects, as shown, the receiver architecture 27400 may further implement one or more of: means for filtering the quantized output using a filter 27416 whose coefficients are dependent on a direction of the interferer to produce a filtered signal; means for converting the filtered signal to an analog signal, e.g., by the DAC 27418, and/or means for combining the analog signal with the beamformed signal to generate the compensated signal, e.g., by the combiner 27402. In some aspects, as shown, the receiver architecture 27400 may further implement means for shaping quantization noise in the compensated signal to out-of-band using a LPF 27404 to form a LPF signal; means for adjusting a gain of the LPF signal prior to quantizing the LPF signal to reduce the dynamic range of the quantizer 27408, e.g., using gain 27406, and/or means for eliminating harmonics introduced by the quantizer 27408 using a LPF 27416 to generate a LPF signal and means for down sampling the LPF signal to a Nyquist rate, e.g., using the decimator 27414. Turning to the mathematics of an exemplary architecture, design of the filter W, data matrix B and decimation operation are described below. In some aspects, a process to design the filter W may employ the direction of the interference(s), i.e., θ_i,i=1,…I. The direction of interference may be known through a previous calculation, and determined in any of a number of processes, such as by use of a digital process such as the MUSIC process. A lower triangular matrix L and a scaling vector α may be defined as follows: L=[■(1&0@1&1)] α=[■(2@3)] Then, a filter coefficient matrix F∈C^(2N_r×N_r ) may be determined as follows: 〖F=[█(F_1@F_2 )]=[■(L⊗a_r^T (θ_1 )@⋮@L⊗a_r^T (θ_I ) )]〗^+ [■(α⊗a_r^T (θ_1 )@⋮@α⊗a_r^T (θ_I ) )] where [∙]^+ is pseudoinverse operator and ⊗ represents a kronecker product. When the oversampling rate is denoted by K, where K≥2, W∈C^((K-1)N_r×N_r ) may be formed as follows: W=[█(F_1@F_2@F_2@⋮)] Higher K is better for BER, but worse for power consumption. Thus, the number of receiver antennas may be N_r, the direction of interferences may be θ_i,i=1,…I, and the oversampling ratio may beK≥2. The structure of the data matrix B∈C^((K-1) N_r×K-1) is presented next. The initial states of the memories may be set to zero, i.e., b[0]=0. For an oversampling rate K, K-1 samples may be used from each antenna output. The data vector b[i] may be denoted as: b[i]=[b_1 [n],b_2 [n],…,b_(N_r ) [n]]^T where i is (n modulo K), and b_m [n] is the n′th digital sample at the output of m′th quantizer, m=1,…,N_r. Then, the data matrix may be the following: B=[b^((1)),b^((2)),…,b^((K-1)) ]=[■(b[1]&b[2]&⋯&b[K-1]@0&b[1]&⋯&b[K-2]@0&0&⋯&b[K-3]@⋮&⋮&⋯&⋮@0&0&⋯&b[1] )] Thus, if mod(n,K)=0, then the DAC input may be b[n], assuming that the interference is larger than the signal such that signal part may be ignored. Otherwise, the DAC input may be 〖W^T b〗^((i)), where i=mod(n,K), and b[i]=[b_1 [n],b_2 [n],…,b_(N_r ) [n]]^T The decimation operation may be performed to down sample the signal, which may have been oversampled. K-1 samples out of every K samples may be used as the first samples of every K samples may have large interference. FIG. 62illustrates an oversampled signal in accordance with some aspects. As shown in FIG. 62, samples n at the decimator that satisfy (n modulo K)≠1 may be replaced with zero. Then, the remaining signal may be down sampled using a low pass filter, such as a comb filter. In some aspects, the multiplication 〖W^T b〗^((i)) may use O(N_r^2) real multiplication and summation bits per sample if b>1 bits quantizer. On the other hand, if a 1-bit quantizer is used, a real summation may be limited to only O(N_r^2). The gain control parameters of the first and second gains may be determined as: c[i]=[c_1 [n],c_2 [n],…,c_(N_r ) [n]]^T,i=mod(n,K) g[i]=[g_1 [n],g_2 [n],…,g_(N_r ) [n]]^T,i=mod(n,K) In some aspects, the gain control parameters can be chosen by simulation, or can be found while sampling using automatic gain control process. In other aspects, the gain control parameters may be set as above. FIGS. 63Aand 63Billustrate filter characteristics of the receiver in accordance with some aspects. As shown in FIG 63A, a receiver with N_r=8 antennas may be able to mitigate interference at θ=40° and θ=120° by up to -30 to-40 dB when only a 4-bit quantizer with K=4 is used. This increases the mitigation of interference to about -250dB when an infinite resolution quantizer is used, at the cost of excessive power loss, among others. Note that analog beamforming may not have flexibility to cancel interference for any given direction (i.e., array pattern of analog beamforming is designed to have a fixed pattern irrespective of interference direction). Instead, analog beamforming may only beamform to the desired direction. FIG. 64illustrates a beamforming pattern according to some aspects. In particular, FIG. 64illustrates analog beamforming for θ=95°. As can be seen, the analog beamforming may only be able to cancel interference by -18dB and -15dB at θ=40° and θ=120°, respectively. As above, analog beamforming may have an inflexible beam pattern. FIG. 65illustrates a BER performance according to some aspects. In particular, FIG. 65illustrates the BER performance of analog beamforming, digital beamforming and the architecture shown in FIG. 61. The different receiver architectures shown in FIG. 65may have N_r=8 antennas at the receiver in a LOS channel with a 110° desired signal direction and 90° interference direction. For simulation purposes the bandwidth may be 1 MHz, and the interference and desired signal communicate over the same band. A pulse shaping filter may be used. The pulse shaping filter may be a square root raised cosine filter with a filter length of eight symbols and a rolloff factor of 0.2. In the simulation, SIR=-30 dB and QPSK modulation are used. As shown in FIG. 65, the analog beamforming architecture may be completely blocked by the interference as analog beamforming can only reduce interference by -13dB. A fully digital receiver with a 4-bit ADC may also performs worse than the architecture of FIG. 61since a 4-bit ADC saturates under high interference. The architecture of FIG. 61, however, may perform the best due to interference nulling before quantization. FIG. 66illustrates a method 27900 of reducing quantizer dynamic range in a receiver in accordance with some aspects. The method 27900 may be performed by the structure shown in FIG. 61. At operation 27902, a plurality of beamformed signals may be received from a plurality of beamforming antennas. The beamforming antennas may scan across all angles and produce the beamforming signals at each angle. For each beamformed signal at each angle, the beamformed signal may be compensated at operation 27904 by a digitized and modified version of the beamformed signal. The modification may be based on the interferers and associated angles. The angle of any interferers may be previously determined and used during the modification. This may reduce the dynamic range of a quantizer to which the beamformed signal is supplied. The compensated signal may be further processed at operation 27906. The processing may include shaping quantization noise in the compensated signal to out-of-band using a low pass filter (LPF). The gain of the LPF signal may be adjusted prior to quantizing the LPF signal to reduce the dynamic range of the quantizer. The gain may be predetermined or may be variable and set dependent on the channel characteristics. The adjusted signal may then be quantized at operation 27908. The quantization resolution may be predetermined or may vary, dependent on signal type, channel, or other variables. The quantized signal may be modified and fed back to the beamformed signal at operation 27910. In the feedback loop, the quantized signal may be filtered using a filter whose coefficients are dependent on a direction of the interferer and the filtered signal converted to an analog signal. The analog signal may be supplied to a gain similar to the gain in the feedforward portion, although the gains may be independent of each other. In some aspects, the gains may be of different types (e.g., fixed or variable). The resolutions in quantizing the compensated signal and converting the filtered signal may be independent of each other, and at least one of the resolutions may be dependent on desired bit error rate (BER) or filter characteristic, for example. The quantized signal may further be processed at operation 27912. The processing of the quantized signal may include decimation; e.g., if the beamformed signal is oversampled during the quantizing, the quantized signal may be down sampled to the Nyquist rate after eliminating harmonics introduced by the quantizer using another LPF. The resulting signal, whether or not decimated, may be supplied to a baseband processor, where the compensation may be digitally inverted to regenerate a digital version of the beamformed signal. The resulting digital signal may be signal processed by the baseband processor. In communication systems, received RF signals may be converted to digital signals for processing at the UE, while digital data may be converted to RF signals for transmission from the UE. An ADC in the receiver chain may receive an RF signal from an antenna and convert the RF signal to a digital signal. A DAC in the transmitter chain may receive a digital signal and convert the digital signal to an RF signal for transmission from the antenna. A design tradeoff of ADC may be expressed by a Figure-of-Merit (FoM) that incorporates the ratio between power, ADC resolution and signal bandwidth: FOM =Power/(Dynamicrange · Bandwidth) (7) The upcoming standards that may use mmWave communications may have different requirements from earlier standards. For example, 5G baseband or 802.11ay (WiGig) may use a low-resolution (4b-7b) and high conversion rate ADC, while 802.11ax WiFi may use a moderate-high (10b-12b) resolution but low bandwidth baseband converter. Interleaving more channels (ADCs) may improve the FoM because, as the conversion speed of a single channel approaches the limits of the technology, the power-speed tradeoff becomes nonlinear. This may demand a disproportionately higher power for a desired increase in speed of a single ADC at these limits. Time-interleaving ADCs may retain the linearity of the trade-off and lead to high-speed ADCs having a FoM achievable by a lower rate single ADCs. However, while time-interleaved ADCs may be a desirable choice for low-resolution, high speed ADC architectures, the use of such time-interleaved ADCs may be unsuitable for architectures that are to use higher resolutions and lower bandwidths. Such architectures may use oversampling, noise shaping, and filtering to achieve the design goals. Even though a time-interleaved ADC with much higher sampling rate compared to the Nyquist Signal Bandwidth possesses the oversampling feature, incorporating oversampling and filtering (no noise shaping) may be limited to achieving a modest 3dB resolution improvement (in theory) for each doubling of the oversampling ratio and thus number of channels Nch. This may limit the adoption of time-interleaved ADC in multi-standard receivers, which may use several different types of dedicated ADCs for each standard, with a corresponding overhead of design time, complexity, and integration resource usage. Aspects disclosed herein may provide a reconfigurable ADC architecture (or ADC system – ADCS) flexible enough, for example, to meet the demands of receivers that are configured to receive communication signals in multiple standards. The ADCS may be reconfigured as desired from a Nch channel time-interleaved ADC to Nch parallel ADCs with a relative offset. This may permit the ADCS to achieve a higher resolution on a lower bandwidth by averaging the output of the channels instead of time-interleaving the channels. In some aspects, the resolution improvement offered by this architecture may be 6dB for each doubling of the number of channels Nch. FIG. 67illustrates an ADCS 28000 according to some aspects. The ADCS 28000 may be used in a receiver of a communication system, for example in a baseband or RF sub-system. The ADCS 28000 may be incorporated in the ADCs 394 shown in FIG. 3E, although the ADCS 28000 is not limited to such incorporation. The ADCS 28000 may thus be incorporated in a communication device, such as a UE, eNB, AP or another device. The ADCS 28000 may be used in environments in which any number of standard-based communications are employed, including legacy (e.g., 3G, 4G communications) and next generation standards (e.g., 5G communications), and the like. The ADCS 28000 may be configurable between different operating modes, which include a time-interleaved mode and an averaging mode. This may enable the ADCS 28000 to adapt to different standards/specifications with different speed vs. resolution trade-off set points. For example, averaging may increase accuracy at the cost of reducing the ADCS speed, and thus may be appropriate for lower speed signaling, such as control signaling. The ADCS 28000 may contain multiple Nch ADCs 28002 (also referred to as core ADCs) that each contain a sampling circuit 28004 for oversampling and decimation. The topology of the ADCs 28002 may be generic and can change based on the application (e.g., SAR, pipeline, Delta-sigma). The inputs of each core ADC 28002 may be connected with a signal and clock distribution circuit 28008 and a TU 28006. The output of each core ADC 28002 may be supplied to a processing circuit 28010. Each core ADC 28002 may have an Nq bit resolution, fsc max speed and correspondent Pcore-ADC@fsc power consumption. The core ADCs 28002 may be numbered from ADC 0 to ADC Nch-1. The sampling circuit 28004 of the core ADC 28002 may permit the core ADC 28002 to oversample and decimate the analog input signal Vin,n and Vin,p from the signal and clock distribution circuit 28008. The signal and clock distribution circuit 28008 may be provided with analog input signals Vin,n and Vin,p from the antenna 28030 (through a front end) to distribute among the core ADCs 28002. The analog input signals Vin,n and Vin,p may be received from a driver circuit 28020, which may be separate from the ADCS 28000. The signal and clock distribution circuit 28008 may also be provided with a master clock signal (MCK) from a local oscillator or other timing circuit (not shown). The MCK may be supplied to the timing circuitry (TU) 28006 associated with the core ADC 28002, which may generate local master clock signal (LMCK) and system clock (SCK) for distribution only to the associated core ADC 28002. The MCK may be frequency divided in the TU 28006 such that the MCK may have a frequency that is an integer multiple of the LMCK. The LMCK signal provided by each of the TUs 28006 may be the same. The TU 28006 may produce a SCK that is dependent on the operating mode of the ADCS 28000. The TUs 28006 may be linked together from the timing unit associated with core ADC 0 to core ADC Nch-1. The digital outputs from the different core ADCs 28002 may be supplied to a digital processing circuit 28010. The processing circuit 28010 may perform multiple operations, at least some of which may depend on the operating mode of the ADCS 28000. The processing circuit 28010 may individually weight and then add the digital outputs from at least some of the core ADCs 28002 in the time-interleaved mode. In some aspects, the inputs from the core ADCs 28002 may be weighted to have digitally preset weights that may be equal or different, the processing circuit 28010 acting as an equalizer. In some aspects, the processing circuit 28010 may instead provide a multiplexed buffer 28010 for at least some of the core ADCs 28002 in the averaging mode. In some other aspects, the processing circuit 28010 may write to a memory the output of some or all the core ADCs 28002. The ADCS 28000 may also employ a mode signal from a controller 28040 to determine the operating mode of the ADCS 28000. The mode signal may be supplied to the timing units 28006 as well as the core ADCs 28002. The mode may indicate the timing of the LMCK to be supplied to the core ADC 28002. The timing units 28006 may be connected together serially and, for example, used to trigger the LMCK at the appropriate time for each timing unit 28006. The timing unit 28006 may contain, for example, one or more latches triggered by an adjacent timing unit 28006. Each ADC 28002 may feature a specific offset as well as a sampling timing skew associated with the sampling circuit 28004. The mode signal may be a preset bit that sets the operating configuration. The controller 28040 in some aspects may be the processing circuit 28010 or in other aspects may be another processor. In some aspects, the mode signal may be a single bit that indicates in which of two modes the ADCS 28000 is to operate, and thus which ADC configuration to use. In some aspects, the mode signal may include one or more additional bits that indicate how many of the core ADCs 28002 to use. In some aspects, if a limited number of core ADCs 28002 are used, the additional bits in the mode signal may indicate which of the core ADCs 28002 to use. For example, the core ADCs 28002 may in some aspects be adjacent, and thus have adjacent ADC numbers. In this case, the mode signal in some aspects may also have an offset bit that indicates the first of the consecutive core ADCs 28002 to use. In some aspects, the mode signal may also have a bit for each of the core ADCs 28002 that indicates whether to use the core ADC 28002. In some aspects, the core ADCs 28002 used in the time-interleaved mode, for example, may be distributed uniformly (e.g., every other core ADC 28002), keeping the timing of the core ADCs 28002 the same so that the timing of the composite time-interleaved signal is uniform. This may be used, for example, in some aspects to reduce the number of core ADCs 28002 used, and thus power consumption. In some aspects, the core ADCs 28002 may have a fixed bit resolution independent of the mode. The core ADCs 28002 may have an 8-12 bit resolution, for example. In some aspects, the core ADCs 28002 may have a variable resolution that is dependent on the mode. In this case, the resolution for the core ADCs 28002 may have a greater number of bits (e.g., 8-11 bits) for parallel operation (averaging mode) and less for serial operation (time-interleaved mode) (e.g., 1-3 bits). In some aspects, means for adjusting an ADC configuration between an averaging mode ADC configuration for higher resolution, lower bandwidth operation and a time-interleaved mode ADC configuration for lower resolution, higher speed operation in which the outputs from the core ADCs are averaged may be implemented by the ADCS 28000. In some aspects, as shown, the ADCS 28000 may further implement means for averaging outputs from core ADCs 28002 in the averaging mode ADC configuration to produce an averaged ADC output and means for combining outputs from core ADCs 28002 in the time-interleaved mode ADC configuration to produce a time-interleaved ADC output, e.g., via processing circuit 28010. In some aspects, as shown, the receiver architecture 27400 may further implement means for providing a system clock signal and a local master clock signal to each core ADC 28002 based on a master clock signal supplied to the timing unit 28006 and means for adjusting the system clock signal dependent on the ADC configuration, e.g., via signal and clock distribution circuit 28008, TU 28006 and controller 28040. In some aspects, as shown, the receiver architecture 27400 may further implement one or more of: means for adjusting a resolution of the core ADCs 28002 dependent on the ADC configuration, e.g., via controller 28040 and ADCs 28002 and/or means for oversampling and decimating an input signal to each of the core ADCs 28002 prior to quantizing the input signal to produce a quantized signal, e.g., via TU 28006, controller 28040, and sampling circuit 28004. FIGS. 68Aand 68Billustrate different operation modes of an ADCS 28100 according to some aspects. As shown in FIG. 68A, the ADCS 28100 may operate in a time-interleaved mode. The time-interleaved mode may be signaled by the mode input to the timing units 28106 and the core ADCs 28102, e.g., by a single bit. The time-interleaved mode may enable the ADCS 28100 achieve a high bandwidth Nch·fsc/2 or conversion speed of Nch·fsc, and Nq (or lower) resolution analog-to-digital conversion. In the time-interleaved mode, the SCK may be supplied to the core ADCs 28102 in sequential order. For example, the SCK signal for ADC N+1 may occur immediately after the signal for ADC N, eventually repeating such that the SCK signal for core ADC 0 occurs immediately after the signal for core ADC Nch-1. Thus, in the time-interleaved mode, each channel may provide a converted sample at a global clock MCK rate. In the time-interleaved mode, the outputs from the core ADCs 28102 may be provided to the memory/bypass (processing circuit) 28110, which may operate as a buffer, such as a Parallel In Serial Out Shift Register (PISO), a memory or a bypass, and provide the core ADC outputs as an output of the ADCS 28100. As shown in FIG. 68B, the ADCS 28100 may also operate in an averaging mode. The averaging mode may be signaled by the mode input to the TUs 28106 and the core ADCs 28102 (labeling shown in FIG. 68A). In the averaging mode, each core ADC 28102 may have a specific offset. In the averaging mode, the ADCS 28100 may operate with the core ADCs 28102 in parallel, with the signal and clock distribution circuit 28108 supplying the signals as indicated in FIG. 67, and exploit offset and timing skew between the channels to achieve a higher than Nq resolution (up to Nq + 3.32log10(Nch)) over a Nyquist bandwidth equal to fsc/2 or conversion speed of fsc. As shown, the SCK for each core ADC may occur at the same time and with the same frequency. Thus, in the averaging mode, each channel may operate simultaneously at fsc = fMCK/Nch with local clocks (SCK, LMCK). The core ADC output may be provided to the processing circuit 28110, which may operate to weight the signals from the core ADCs 28102 to equalize the outputs and provide the core ADC outputs as an output of the ADCS 28100. In some aspects, the core ADC outputs may be averaged to produce the ADCS output. The processing digital circuit can work as a shift register, such as a Parallel In Serial Out Shift Register (PISO), a memory or a bypass in the TI mode, or as an adder or equalizer in the AVG mode, for example. The averaging mode of operation of Nch parallel channels with controlled relative offset allowed by the reconfigurability of the ADCS may be able to achieve better resolution than the equivalent oversampling-by-Nch with the time-interleaved architecture. The resolution improvement on a signal whose bandwidth is equal to the ADC Nyquist frequency fsc/2 for a Nch time-interleaved oversampling system may be: ∆〖SNDR〗_oversampling=10 〖log〗_10⁡〖(N_ch)〗 In some aspects, for a Nch parallel channels averaging system the resolution improvement can be up to: ∆〖SNDR〗_avg=20 log_10⁡〖(N_ch)〗 In some aspects, the system power may not change between the two configurations. The system power, when operating at full rate, may at first order be given by: Psys = Nch x Pcore-ADC@fsc Even in the presence of uncalibrated sources of errors such as skew, differential non-linearity (DNL) or integral nonlinearity (INL), the averaging technique may provide a resolution improvement that is similar to that of a calibrated oversampling core ADC with equal number of channels that is operating in time-interleaved mode. Unlike an oversampled core ADC, however, the ADCS may avoid constraining the input signal, for example, to have at least a minimum amplitude. Note that uncorrelated noise sources add on a root-sum-square (RSS) basis, while signal voltages add on a linear basis. Thus, averaging multiple core ADCs may increase the SNR. FIG. 69illustrates core ADC averaging according to some aspects. The LSB of the averaged conversion characteristic of M equal core ADCs with relative offset may be M times smaller than that of a single core ADC LSB. FIG. 69illustrates a simulation with two quantizers, one with a predetermined amount of offset that clearly shows the resolution has increased in comparison to that of a single channel. In addition, in some aspects, by averaging the output of multiple parallel core ADCs with relative offsets, it is possible to gain up to 1 bit of resolution every doubling of the number of channels Nch. In some aspects, the maximum resolution improvement that would result from the adoption of a Nch time-interleaved ADC configuration to oversample a signal whose bandwidth is equal to the Nyquist frequency of the core ADC is: ∆〖SNDR〗_(oversampling,max)=10 log_10⁡〖(OSR)=〗 10 log_10⁡〖(N_ch ) (α)〗 This is equivalent to 3dB (half bit) per each doubling of the oversampling ratio (OSR) and thus of the number of channels. Instead, in some aspects, the maximum resolution improvement that can be obtained by averaging Nch core ADCs with relative offset is: ∆〖SNDR〗_(avg(os),max)=20 log_10⁡(N_ch )=2∆〖SNDR〗_(oversampling,max) (β) ∆〖ENOB〗_(avg(os),max)≅3.32 log_10⁡(N_ch )≅2∆〖ENoB〗_(oversampling,max) (γ) Compared to equation (α), equation (β) highlights a better resolution improvement, thus showing that the averaging technique with offset between the channels may be a more efficient way to improve the resolution beyond the single quantizer limit and that the reconfigurable architecture may be more beneficial than the fixed (time-interleaved only) one. In fact, since the system power in some aspects may not change between the two configurations and the system power may be at first order: Psys = Nch x Pcore-ADC@fsc Moreover, the averaging architecture may be less sensitive to timing skew and DNL/INL mismatch, with respect to the time-interleaved architecture. In fact, even in the presence of non-calibrated sources of error, such as timing skew and DNL/INL between channels, averaging may still achieve a similar resolution improvement as oversampling. Calibration of the quantizers and system output may be applied. In some aspects, calibration can be applied prior to implementation in a work environment. In some other aspects, calibration may be applied concurrently with the circuit operation and running in the background. Calibration may be performed through a feedback loop involving the controller 28040 that, on the basis of the ADC output from the processing circuit 28010, may calculate the proper configuration bits to tune the ADCS 28000 to approach the desired operating point and performance. FIG. 70shows resolution improvement of an averaging system in accordance with some aspects. The simulation of the ADCS used ideal quantizers having a moderate resolution (e.g., 9 bit) in each channel. The core ADCs may have different offsets at 1GS/s and for a 180 MHz input signal (e.g., using IEEE 802.11ax estimated specification). The results show the variation of the SNDR of the LSB for different number of channels Nch =2, 5, 10. The results of FIG. 70show that a resolution improvement is present, independent of the number of channels. Moreover, as can be seen in FIG. 70, for offset values that are multiples of LSBcore/Nch, the improvement may be higher than that achievable by a simple oversampling factor equal to the number of averaged channels. As illustrated, the improvement may, for example, be equal to 6dB every doubling of Nch. Cadence model (using Verilog-A and schematic building blocks) simulation results of the averaging ADC operation (Verilog-A model) with Nch=10 channels featuring relative offsets that are multiple than LSB/Nch show 20dB resolution improvement: 10dB better than an equivalent oversampling by Nch would achieve. Other Monte Carlo statistical simulations of a 10 channel/9-bit core-ADC averaged configuration with engineered offsets equal to α·LSB9b/Nch (α integer) and in presence of uncalibrated sources of error (DNL/INL, 2ps skew between channels, gain mismatch), show a DNL/INL standard deviation of 0.1LSB, a gain mismatch of 1% between channels and a resolution improvement of up to 9/9.5 dB, thus equivalent to that of a calibrated oversampling technique. FIG. 71illustrates a method 28400 of providing a flexible ADC architecture in accordance with some aspects. The method 28400 may be performed by the controller 28040 in conjunction with the other circuits shown in FIG. 67. At operation 28402, an ADC configuration may be adjusted (or selected) between an averaging mode ADC configuration and a time-interleaved mode ADC configuration. The averaging mode may, for example, be used for higher resolution, lower bandwidth operation. The time-interleaved mode ADC configuration may, for example, be used for lower resolution, higher speed operation in which the outputs from the core ADCs are averaged. Independent of the mode selected, a system clock signal and a local master clock signal may be provided to each core ADC based on a master clock signal supplied to a timing unit. The system clock signal may be adjusted dependent on the ADC configuration. In some aspects, the system clock signal may be adjusted based on a mode signal that indicates the ADC configuration. The mode signal may, for example, comprise a single bit that indicates the ADC configuration or the single bit and at least one additional bit that indicate how many of the core ADCs to use. The resolution of the core ADCs may be adjusted dependent on the ADC configuration. During quantization, the analog inputs may be oversampled and decimated. At operation 28404, the outputs from core ADCs in the averaging mode ADC configuration may be averaged to produce an averaged ADC output. The averaged ADC output may then be further processed. The processing may comprise buffering the quantized signals from each of the core ADCs. At operation 28406, the outputs from core ADCs in the time-interleaved mode ADC configuration may be combined to produce a time-interleaved ADC output. As above, the time-interleaved mode ADC output may then be further processed. The quantized signals may be processed differently dependent on the ADC configuration. The processing may comprise equalizing the quantized signals from each of the core ADCs. The method used for beamforming and the beamforming location may have broad implications on both receiver and system performance. The choice of analog beamforming (either at RF or at IF) versus digital beamforming may ultimately represent a tradeoff in receiver linearity, blocker rejection, ADC dynamic range, and power consumption. Digital beamforming may have benefits for control plane latency and effective SNR in NLOS environments. While digital beamforming may provide flexibility in beam shaping, it may do so at the cost of a one-to-one correspondence between transmitter RF chain and antenna. In particular, the power consumption for digital beamforming may be in part due to the large number of ADCs and DACs, one of which may be used for each RF chain. In particular, the power consumption of the ADCs and DACs may increase linearly with sampling rate and exponentially with number of resolution bits per sample. The quantity and resolution of the ADCs may place significant power consumption into the data converters and the associated data links to the baseband processor. Moreover, the ADC dynamic range may be an issue, especially when one or more strong interferers are present. Although it may be desirable for the ADCs to have sufficient dynamic range to handle interferers, the ADC input may be devoid of spatial interference rejection. Hybrid beamforming, which may incorporate analog beamforming, may reduce or alleviate the issue of power consumption to some extent, but at the cost of masking individual antenna signals from the digital processing, as well as adding to control latency and NLOS deficits. Alternatively, the use of digital beamforming with low-resolution ADCs (such as 1-3 bit ADCs), rather than the high-resolution ADCs typically used, may reduce ADC and digital processing power consumption, but at the cost of throughput in high-SNR scenarios. In some aspects, ADC specifications used, in particular the dynamic range, may be reduced through analog summation while retaining individual antenna signals for digital processing. In particular, dynamic adjustment of the quantity of operating ADCs may be dependent on the signal conditions and system activity. In some aspects, analog summation may be used across elements for spatial interference rejection, but in a manner that is invertible in the digital domain for fast control plane operation. Thus, in some aspects the control plane performance may match that of digital beamforming and thus the control plane latency may be smaller than that for analog beamforming. Additionally, the use of analog phase shifters and in-phase/quadrature-phase (I/Q) imbalance compensation circuitry present in analog beamforming may be avoided, that is, in some aspects the architecture may avoid I/Q combining and rely only on switching signal polarity. Moreover, the spatial interference rejection and fewer ADCs used for analog beamforming may be achieved, as may the low control latency, high effective SNR, high non-line-of-sight throughput and MU-MIMO capability of digital beamforming. FIG. 72illustrates a receiver architecture 28500 in accordance with some aspects. The receiver architecture 28500 may be incorporated in the parallel receive circuitry 382 shown in FIG. 3E, although the receiver architecture 28500 is not limited to such incorporation. The receiver architecture 28500 may be disposed in a UE, an NB, an AP or another communication device. The communication device may have other circuitry, such as transmitter circuitry, not shown for convenience. The architecture 28500 may comprise receiver circuitry that includes an RF front end 28502, multipliers 28504, combiners 28506, variable gain control 28508, ADCs 28510 and a baseband processor 28520. Other elements, such as low pass filters, may be provided but are not shown for convenience. The RF front end 28502 output may provide outputs s_i [t], i=1,…,N from the antenna elements (not shown) of an antenna 28530 connected with the RF front end 28502. Each ADC 28510 may be associated with a different combiner 28506 and variable gain control 28508, along with a plurality of multipliers 28504. Each multiplier 28504 may be associated with a different output s_i [t], i=1,…,N from the RF front end 28502 and may have an individual signal weight w_ij, i,j=1,…,N that is used to weight the signal. In some aspects, the signal weights may take values of either -1 or 1. Although limiting the weights to these values may result in an easier computation, in some aspects, the weights may take other integer or non-integer real or complex values. Different weightings may be used as different ADCs 28510 may see different amounts of interference. The weightings may be adaptive, dependent on conditions of the desired and interferer signal (or other variables) to maximize or increase signal-to-interference-plus-noise (SINR) of the desired signal, or may be fixed and thus independent of the signal and channel conditions. Thus, for each antenna element, the analog output from a particular antenna element may be combined with the weighted analog outputs from each other antenna element at the combiner 28506. The combined output from the combiner 28506 may be supplied to the variable gain control 28508. The variable gain control 28508 may provide a gain g_i, i=1,…,N to adjust v_i [t], i=1,…,N, the input to the ADC 28510. The variable gain control 28508 may permit a reduction in the dynamic range of the ADC 28510 by providing an invertible analog compensation for potential interferers prior to submission to the ADC 28510. The dynamic range of the ADC 28510 may be selected by the baseband processor 28520 (or another processor) according to a desired array interference rejection and angle resolution. To resolve smaller angles, a larger array or greater ADC dynamic range may be used. The output from the ADC 28510 may be supplied to the baseband processor 28520, where the analog compensation provided by the combiner 28506 may be digitally inverted. This inversion may in some aspects be limited to the resolution of the ADC 28510. In some aspects, the analog summation may be implemented with current mode summation. In other aspects, other signal summation methods may be used. The method of summation used may meet a desired power and performance. As shown, in some aspects, the arrangement of FIG. 72may reduce or eliminate the use of analog phase shifters and I/Q imbalance compensation circuitry used for analog beamforming. In some aspects, means for receiving beamformed signals from a plurality of antenna elements of an antenna may be implemented by the receiver architecture 28500. In some aspects, as shown, the receiver architecture 7200 may further implement means for compensating for the interferer signal, prior to providing the beamformed signals to ADCs, e.g., via multipliers 28504 and combiners 28506, means for quantizing the compensated signals, e.g., via ADCs 28510, and means for reversing the compensating prior to processing the quantized signals, e.g., via the baseband processor 28520. In some aspects, as shown, the receiver architecture 28500 may further implement at least one of: means for determining a direction of at least one of the desired or interfering signal or channel sounding during processing of the quantized signals, e.g., via the baseband processor 28520. In some aspects, as shown, the means for compensating for the interferer signal may further comprise means for combining a weighted copy of each of the beamformed signals e.g., via combiners 28506. In some aspects, as shown, the receiver architecture 28500 may further implement at least one of: means for adjusting a variable gain of each compensated signal to normalize a power level of a signal supplied to a corresponding ADC of the ADCs 28510, e.g., via the variable gain control 28508; means for adjusting a number of the ADCs 28510 to use during a particular operation; and/or means for selecting a dynamic range of each ADC 28510 dependent on a desired array interference rejection and angle resolution, e.g., via the baseband processor 28520. In some aspects, the number of ADCs 28510 may be limited to a predetermined number or percent of the available ADCs 28510, e.g., not all of the ADCs 28510. The baseband processor 28520 may select the number of ADCs 28510 used. The baseband processor 28520 may, for example, enable all ADCs 28510 for control plane operations, desired and interferer direction finding, or channel sounding, among others. In some aspects, the baseband processor 28520 may limit the number of ADCs 28510 used to a subset of the available ADCs 28510, for example, in an active link. Mathematically, the operations described above may be described using vectors, shown below. In particular, vectors s (antenna output) and v (ADC input) are composed of elements si, and vi, respectively, W(weightings) is a weighting matrix composed of wij elements, and G is a Toeplitz matrix composed of gi elements (variable gain control). The array size N may be chosen dependent on a desired array gain, interference rejection, and power budget. The ADC input v can be expressed as a matrix transformation of s: v=sWG The original antenna signals can be calculated from v: s^'=vpinv(WG) where pinv is the pseudo inverse of the matrix. A quantized version of v may be available in the digital domain for use by the baseband processor to essentially invert the analog matrix transformation and permit processing of the original signal. In particular, the direction of the desired signal and the interferers can be found using s′. Various processes may be used to find the directions of the different signals. One example of such a process may be the MUSIC process. The use of analog summation before the ADCs permits the individual antenna element signals to be retained, while still providing spatial interference rejection to the ADCs. In some aspects, the matrix transformation may remain static. This is to say that the weightings, which may be stored in a memory of the communication device, may remain the same, independent of the interference. In other aspects, the weightings may be dynamic and be dependent on the interference. In this case, sampling of the signal from the RF front end may be performed periodically and used to adjust the matrix coefficients. In some aspects, the baseband processor may determine which ADC has the lowest SNR, push the interferer onto a single ADC if possible, and weight the signals from the antenna elements accordingly. With knowledge of the directions of the desired signal and the interfering signal(s), the baseband processor may select one or more paths to enable in order to increase or maximize SINR. FIG. 73shows a simulation of a spatial response in accordance with some aspects. The spatial response may be for a 4-element linear array and use Hadamard weighting. In some aspects, after determination of the maximized SINR path, the baseband processor may disable the ADCs of unused paths to save power. As shown in this simulation, the desired direction is 0°. FIG. 74shows a simulation of BER in accordance with some aspects. In particular, FIG. 27487 illustrates exemplary BER performance for the design shown in FIG. 72vs. analog and digital beamforming structures for an 8-element array, 4-bit ADCs, 20dB signal/interferer ratio, with 16-QAM modulation. The desired direction is 0°, similar to that shown in FIG. 73, and interference direction is 20°. As can be seen, the analog BER remains essentially constant, independent of the SNR per antenna, while the digital BER decreases steadily, eventually plateauing. The exemplary BER performance for the design shown in FIG. 72, however, matches the digital performance at low SNRs, and the BER rapidly decreases as the SNR increases in this example. In some aspects, a matrix other than the Hadamard matrix may be used. FIG. 75shows a simulation of interference rejection in accordance with some aspects. The simulations may be for an 8-element array and 4-bit ADCs with adaptive weight matrix W. FIG. 75shows a simulation of interference rejection vs. azimuth angle for Hadamard weightings and an optimized codebook also constrained to weights in the set {-1, +1}. Both codebooks provide interference rejection greater than 12dB at all angles. This may enable a reduction in the ADC quantization by two bits, thereby reducing the power consumption. FIG. 76illustrates a method 28900 of reducing quantizer dynamic range in a receiver in accordance with some aspects. The method 28900 may be performed by the RF front end 28502, multipliers 28504, combiners 28506, variable gain control 28508, ADCs 28510 and baseband processor 28520 shown in FIG. 72. At operation 28902, a plurality of beamformed signals may be received at the RF front end 28502 from a plurality of antenna elements of an antenna 28530. Each beamformed signal may include a desired signal and an interferer signal. The number of the ADCs 28510 to use may be adjusted dependent on channel conditions or signal type, among others. At operation 28904, the interferer signal may be compensated for prior to quantizing the beamformed signal. The compensation may comprise combining a weighted copy of each of the beamformed signals at combiners 28506. The weightings may be defined by an invertible analog summation weight matrix whose weightings are fixed or may depend on conditions of the desired and interferer signal to maximize a signal quality such as SINR of the desired signal. In some aspects, the analog summation weight matrix may comprise a Hadamard matrix. In some aspects, each compensated signal may be provided to a different ADC. In some aspects, some or all of the compensated signals may be provided to the same ADC or ADCs 28510. The compensated signals may then be quantized at the ADCs 28510 to form quantized signals at operation 28906. A variable gain of each compensated signal may be adjusted prior to quantization to normalize a power level of a signal supplied to a corresponding ADC of the ADCs 28510. Quantizing the compensated signals may include determining a direction of at least one of the desired and/or interfering signal or channel sounding. The quantized signals may be supplied to a baseband processor 28520. The baseband processor 28520 may digitally reverse the compensation at operation 28908. The baseband processor 28520 may subsequently further process digital versions of the beamformed signals. Some aspects of this disclosure relate generally to a loopback based time skew calibration for time interleaved analog-to-digital converter (ADC, collectively TI-ADC) that does not use external test equipment. The TI-ADC may be used in a radio-frequency transceiver. The frequencies at which modern telecommunication devices operate may create difficulties with related hardware components. The ADC used to handle signals in such devices may exceed the ability of a single ADC. To address this, it may be possible to utilize a number of ADC circuits in separate channels that may be interleaved and sequentially triggered, being controlled by a common clock. If the channel elements were all identical, then the components would all behave in the same way. However, real world components have some differences due to manufacturing processes, which in turn creates mismatches between the channels used in the TI-ADC and reduces the performance of the system, such as reducing the signal-to-noise ratio (SNR) and the spurious free dynamic range (SFDR). Different types of mismatches between the channels may appear, such as: 1) DC offset mismatch, 2) gain mismatch, 3) time skew mismatch, and 4) bandwidth mismatch. Some aspects of the present disclosure consider how to calibrate the time skew to deal with the time skew mismatch without using external Test Equipment (TE), for example, by utilizing a loopback scheme. FIG. 77is a block diagram of an example of a Time-Interleaved Analog to Digital Converter (TI-ADC) architecture 29000 that achieves a high-speed conversion using M parallel low speed ADC channels (three channels are shown for illustrative purposes, Channel A CH-A, Channel B CH-B, and Channel C CH-C). The TI-ADC may be the ADC circuitry 394 described above or it may comprise different configurations. An analog input 29010 may be provided to M different sample and hold circuits 29020A, 29020B, 29020C that may be sampled at three different phase times φ0, φ1, and φM-1, respectively, utilizing a common clock 29025. The sampled signals may be provided to analog-to-digital converters (ADCs) 29030A, 29030B, 29030C. The digital signals may then be combined with a multiplexer 29040 to produce a digital output signal 29050. FIG. 78is a timing diagram 29100 that illustrates how in some aspects all the channels may operate with a same sampling frequency FS (or its inverse TS, shown in the FIG.) with M uniformly spaced phases. Each phase’s φ sample and hold lasts for a time TS (or mTS for the mth phase), and the overall sample time for all the phases is nMTS. Thus, the sample for φ0 begins at time T0, the sample for φ1begins at time T1, and so on, with the cycle repeating at time Tn. The overall sampling frequency equals to MFS (which is 1/MTS). FIG. 79is a block diagram illustrating an example of a transceiver 29200 having a loopback design. A reference signal generator 29205 may produce a reference signal 29207 that may be, for example, a sinusoid or complex exponential signal, and that may be provided to an input of a single-sideband (SSB) generator 29210. The SSB generator 29210 may produce a quadrature output having I (in-phase) and Q (quadrature) components or sub-channels. These components may be provided to inputs of respective digital-to-analog converters (DACs) 29220I, 29220Q. The DAC 29220I, 29220Q outputs may be provided to respective inputs of an IQ modulator 29230 which provides the signal to a transmit path amplifier 29240 and then to a transmit (TX) path. In one aspect, amplifier 29240 may be an intermediate frequency (IF) amplifier. The signal provided at the input of the transmit path amplifier 29240 may be connected to an output of a corresponding receive path amplifier 29260 via a loopback connection 29250, which directs the transmitted signal, including the reference signal 29207, into the receiver. In an alternate configuration, the loopback connection 29250 may be connected to an output of the transmit path amplifier 29240 and an input of the receive path amplifier 29260. In these configurations, the loopback connection 29250 is immediately adjacent to the amplifiers 29240, 29260. However, other placements for the loopback connection 29250 may be possible. For example, the loopback connection 29250 may be applied prior to the IQ modulator 29230 and the IQ demodulator 29270 and separate loopback lines may be used in this configuration. The combined receive path and loopback signals may be provided to an IQ demodulator 29270 which breaks the signals down into the respective I and Q components. These signals may be provided to the inputs of respective sample and hold circuitry (example for Channel A shown) 29020AI, 29020AQ controlled by the clock 29025, as discussed with respect to FIG. 1, and then to the respective ADCs 29030AI, 29030AQ, and the resultant analog signals may be provided to phase estimators 29290I, 29290Q for each signal to estimate the phase of the reference signal 29207. From this estimated phase, the time skew for the I and Q sub-channels τ ̂_Im, τ ̂_Qm may be computed. Using the estimated time skew, the signal can be corrected by respective correction circuitry 29280I, 29280Q that adjusts the signals produced by the clock 29025. This may permit calibration without using an extra ADC by using loopback for generating a calibration signal. If the device already has a phase shifter loopback for IQ imbalance calibration, in some aspects, it may not use any additional hardware to implement the calibration. The following discussion provides, by way of example, an analysis that may be used in making the time skew determinations and corrections. In the case of one ADC, the reference signal generator 29205 of the digital transmitter may be configured such that its output may be a sinusoid signal (a single DAC 29220 (e.g., one of 29220I or 29220Q may be sufficient)). The output of the mth ADC channel may be: where: m: channel number nMTS: sampling interval of the entire ADC (collective ADC channels) mTS: sampling interval of one channel τm: time skew of the mth ADC channel s(t): analog signal input to the ADC In this case, s(t) for the reference signal (prior to splitting it into the channels) may be given by: s(t) = Asin(2πft + θ) where: f: sinusoid frequency θ: phase of the sinusoid A: unknown amplitude of the sinusoid After splitting the reference signal 29207 into the channels, s(t) is replaced by s(nMTS + mtS + τm), thus, the output of the mth ADC channel may be: where: The phases θ[m] may be estimated (which permits derivation of the timing skews τ ̂_m) by: where N samples per ADC channel are assumed. Applying linear detrending by subtracting 2πfTSm for the sake of simplicity, and using: Time-skew correction may be performed, for example, by digitally controlled delay lines that delay the signal at the input of each of the ADC channels, or by digital correction of the outputs of each of the ADC channels. In the case of two ADCs (for I and Q channels), a complex exponential reference signal may be used, of the form: sI(t) = AIcos(2πft + θ), sQ(t) = AQsin(2πft + θ) The procedure used may be as follows: For each of the ADC channels, the phase of the received sinusoid/cosine may be estimated using the same approach as in the one ADC case. All of the θ ̂_I [m] estimation may be located on one line, and the θ ̂_Q [m] estimation may be located on another line with an offset of π/2 radians to the θ ̂_I [m] line. To correct for this, subtract π/2 radians from θ ̂_I [m]. The results are denoted as θ ̂_I [m], θ ̂_Q [m]. Apply linear detrending by subtracting 2πfTSm from θ ̂_I [m], θ ̂_Q [m]. Calculate the average of all the phases. Subtract the average phase from all the phases. Convert the phase difference to skew by dividing by 2πf. Perform the time skew correction. FIG. 80is a flowchart that illustrates components of a method 8000 described above. The transceiver 29200 is one example that may constitute a means to perform a method for operating a loopback-based time skew calibration circuit for a time-interleaved analog-to-digital converter (ADC), but the means are not limited thereto. In operation S29310, the reference signal may be generated on the transmit side, and in operation S29320, this reference signal may be communicated to the receiver side. In operation S29330, an estimated skew time may be calculated with the phase estimator based on the reference signal. Finally, in operation S29340, the clock timing of the S/H circuit may be corrected to compensate for the estimated time skew. The time skew estimation and correction may be done in one shot, or may be done iteratively (depending on accuracy of the correction). With regard to a choice of frequency, in general, the higher the frequency, the better the quality of the estimate (since there may be a division by frequency when converting to skew). Put differently, for a given accuracy of measurement of the phase, dividing by a larger frequency will generally allow the time skew estimate to be more accurate. The measurements may be performed on multiple frequencies to improve accuracy of measurement. This method can, for example, be used during production of the device, at power up, periodically, or according to some predefined schedule or event. The high frequencies at which modern telecommunication devices operate may create difficulties with related hardware components. The ADC used to handle signals in such devices may exceed the ability of a single ADC. To address this, it may be possible to utilize a number of slower (i.e., longer cycle time) ADC circuits in separate channels that may be interleaved and sequentially triggered, being controlled by a common clock. If the channel elements were all identical, then the interleaved design would be simple, as the components would all behave in the same way. However, real world components have some differences due to manufacturing processes, which in turn creates mismatches between the channels used in the Time Interleaved (TI)-ADC and reduces the performance of the system, such as reducing the signal to noise ratio (SNR) and the spurious free dynamic range (SFDR). Four different types of mismatches between the channels may appear: 1) DC offset mismatch, 2) gain mismatch, 3) time skew mismatch, and 4) bandwidth mismatch. The present disclosure considers how to calibrate the gain to deal with the gain mismatch without using external Test Equipment (TE). When using a TI-ADC, it may be desirable to perform calibration across the multiple individual ADCs. Higher modulation orders (such as 64-QAM, 256-QAM, and 1024-QAM) may use an effective number of bits (ENoB) of 9 bits at a 2640 MHz sample rate. In these situations, the desired performance may make calibration of the individual ADCs in the TI-ADC channels (also referred to as “slices”) desirable, including gain calibration. In a general sense, according to various configurations, the TI-ADC may be operated in modes such as: a normal operation, in which gain variances in the ADC channels/slices may be corrected, and a calibration mode, in which a known signal may be provided in the ADC channels/slices and a gain correction value may be computed to apply at a later time. Various reference voltages may be used to determine the gain correction values, and these values may be saved in various ways. The system may utilize a temperature reference that allows for gain correction values that may vary across temperature. FIG. 81is a block diagram of an example TI-ADC 29400. The TI-ADC 29400 may be ADC circuitry 394 as described above, but could also comprise different circuitry as well. A switch 29410 may be provided that switches between a device input signal 29405 during normal operation, and a voltage reference 29415 source during a calibration operation. The voltage reference 29415 could be any form of stable voltage reference, such as a band gap reference, a reference derived from on-chip resistors, and external reference, including supply by a battery or the like. The voltage reference 29415 may have a precise or imprecise absolute value, and it may maintain its voltage so that whatever voltage value may be provided to one ADC 29435 during calibration may be accurately provided to the others as well. In either case, a switched signal (analog input) 29420 from the switch 29410 may be provided to a plurality of track and hold (T/H) circuits 29425 arranged in parallel via a linkage and operated in a cascaded manner. These circuits 29425 may be used to acquire the input signal 29405 at a particular time and hold the value steady for a part of the cycle to provide a stable input to the ADCs 29435. The T/H circuits 29425 could also be configured as sample and hold (S/H) circuits. In some aspects, a value may be collected and maintained at some controlled point in time. The term “track and hold,” or “T/H circuit 29425” herein, includes sample and hold or S/H circuitry as well. In one variation, the switch 29410 may be provided after the T/H circuits 29425. Although this may introduce some complexity in that the switch 29410 switches multiple channels, such a configuration allows an independent switching of each channel, and furthermore allows for calibrating out any kind of gain variations across the T/H circuits 29425. The timing is illustrated in FIG. 82, which is a block diagram of an example of a TI-ADC 29400 architecture that achieves a high-speed conversion using M parallel low speed ADC channels (three channels may be shown for illustrative purposes, Channel A CH-A, Channel B CH-B, and Channel C CH-C). The analog input 29420 may be provided to M different track or sample and hold circuits 29425A, 29425B, 29425C that may be sampled at three different phase times φ0, φ1, and φM-1, respectively, utilizing a common clock signal 29480. The sampled signals may be provided to analog-to-digital converters (ADCs) 29435A, 29435B, 29435C, which may be, e.g., flash ADCs, sigma-delta ADCs, dual slope converter ADCs, and successive approximation converter ADCs, to name a few. The architecture described herein may be independent of the particular type of ADC device used. Digital output signals 29440 (FIG. 81) from the cascaded ADCs 29435 may then be combined with a multiplexer 29450 to produce a single-stream digital output signal 29455 (FIG. 81). FIG. 83is a timing diagram 29600 that illustrates how in an exemplary aspect all the channels operate with a same sampling frequency FS (or its inverse TS, shown in the FIG.) with M uniformly spaced phases. Each phase’s φ sample and hold lasts for a time TS (or mTS for the mth phase), and the overall sample time for all the phases is nMTS. Thus, the sample for φ0 begins at time T0, the sample for φ0 begins at time T0, and so on, with the cycle repeating at time Tn. The overall sampling frequency equals to MFS (which is 1/MTS). In normal operation, a controller 29475 (FIG. 81) sets the switch 29410 to select the normal input signal 29405. The controller 29475 also generates time-interleaved control signals via a linkage 29480 to each of the T/H circuits 29425 that may be connected via a linkage 29430 to corresponding ADCs 29435. The controller 29475 starts ADC cycles, with a subsequent selection of an appropriate ADC digital output signal 29440. Returning to FIG. 81, following the multiplexer 29450, there may be a digital measure and correction (MC) unit 29460, which may operate in both the normal operation mode and the calibration mode. When operating in the normal operation mode, the MC unit 29460 may be used to apply, or support applying (e.g., by not adjusting when an analog adjustment is made prior to or within the ADC), corrective gain adjustment values to the output signal that may be dependent upon which ADC 29435 may be selected at the current time. It may then forward a gain-adjusted output signal 29495 to subsequent portions of the device. When operating in the calibration mode, the MC unit 29460 may provide measurement signal related data 29470 to the controller 29475. Conversion of measurement data to gain values may be done by either the MC unit 29460 or the controller 29475. The MC unit 29460 may be viewed as an extension of the controller 29475. This collected data 29470 could, for example, be a gain offset, which would result in a multiplier being applied to the output of the respective ADC 29435. The gain adjustment values could also be provided by a look-up table (LUT) and/or utilize some other piecewise linear correction model, possibly including interpolation. The voltage reference 29415 may be set to different values to permit a multi-point calibration, which may flush out non-linearities. The voltage reference 29415 may provide a series of outputs or waveforms that may then be measured, which permits a construction of a more complex LUT. The gain offset and/or LUT values may be stored in the memory 29490 for subsequent use during the normal operation mode. Linear interpolation may be utilized to estimate gain values for voltages between those actually supplied by the voltage reference 29415. In one configuration, a direct loopback/feedback of the output signal 29472 may be utilized as the voltage reference. This may permit a transmission of a complex exponential function using a DAC (not shown). Therefore, the system could transmit a calibration waveform and then capture it. That could allow a sophisticated calibration, such as the multipoint calibration discussed above. The controller 29475 thus may apply or support the application of (e.g., when the MC unit 29460 adjusts), a gain correction stored in a memory 29490 whose value depends on which ADC 29435 may be selected by the controller 29475. This correction could be in a simple form or a complex form. The complex form may include a linearity correction using, for example, stored polynomial coefficients. In an alternate implementation, correction for gain and offset could be achieved by directly setting analog or digital control signals 29482 input to the individual ADCs 29435. Thus, in some aspects, in the calibration (built-in self-test (BIST)) mode, the controller 29475 sets the switch 29410 to input the voltage reference 29415 to the ADCs 29435 and to monitor the resulting output. The controller 29475 may generate a table of correction values stored in the memory 29490 for later adjustment during normal operation. The memory 29490 could be a set of registers or a more sophisticated static RAM device that stores the gain values, LUTs, or other related data. The controller 29475 may also monitor a temperature reference 29485 (e.g., thermometer), and re-run the calibration cycle if the temperature is sensed to have changed by more than a threshold amount. In another configuration, the memory 29490 may store multiple sets of gain values at different temperatures so that subsequent operation at a particular temperature does not employ re-calibration. In one configuration, the system may perform a linear interpolation of values between temperatures to derive a gain value at a temperature that has not been measured. In a further configuration, if an accurate relationship between temperature and gain values may be determined mathematically, then an equation could be applied to a gain value determined for one temperature during calibration when operating the device at a different temperature. In a further configuration, the temperature could be ignored, and a background calibration may be performed continuously when not in a receive mode (which may be a majority of the time). In some aspects, the use of external test equipment may be avoided, and excess time during manufacturing may not be wasted. The gain calibration may be done at a device wakeup, periodically, or based on some other condition. An ongoing gain calibration may be particularly beneficial if the gain imperfection is time varying (e.g., due to a temperature variation). In one implementation, an algorithm may be implemented that looks at average values of a waveform over a period of time of the ADC output. This algorithm may presume that an I/Q imbalance has been calibrated, as has a local oscillator (LO) leakage of the transmitter, and a DC offset of the receive path. The transmit path may be used to transmit a complex exponential waveform—this provides a continuous wave (CW) signal (e.g., a single RF frequency) after the I/Q modulator. A loopback may be provided from the transmit side to the receive side, and a signal power output of each ADC slice may be calculated separately. Then, an average power of all of the slices may be computed for both I and Q. The signal power of each slice may be divided by the average, and the square root of this ratio computed, which yields a gain error that should be corrected. By way of example, if there are ten ADCs 29435, then the output values may be placed into, e.g., ten separate tables where each one is taking every tenth slice (offset in time). Then across each of the tables, an average power calculation is made. This provides an average power of a number of slices for a particular ADC 29435, and this provides a basis for the gain correction. In order to compute the signal power of each slice, first the process collects N samples from each slice. N may be chosen such that N samples form an integer number of cycles of a sinusoidal signal being measured. For each slice, the values may be squared, summed, and then divided by N. Alternately, for each slice, the signal may be demodulated by multiplying the received signal by e2πjft, where f is the signal frequency and t is a sampling time for the ADC 29435. The demodulated signal may be summed and divided by N, which computes the magnitude squared. The correction may be done in analog or in digital (after the ADC 29435). If the correction is done in the analog domain, a second round of calibration may be done to verify that the result is good, or to determine that additional modification is to occur. The analog correction could be provided by an analog control signal provided to the ADC 29435, using a closed loop system. This arrangement could be run for some period of time, adjusting the control input to the ADC 29435 until the measured power (the average power of that ADC 29435) is at the desired level. This may be sequentially performed to adjust the level for each ADC 29435. FIG. 84is a flowchart illustrating an example implementation of a process 29700 for applying the gain correction to the TI-ADC. The TI-ADC 29400 is one example that may constitute a means for operating a time-interleaved analog-to-digital converter (TI-ADC) with gain correction device, but the means are not limited thereto. In operation S29710, the TI-ADC may be set, e.g., by the controller 29475 to operate in a calibration mode, and a known signal may be applied to each of the ADC slices sequentially. In operation S29720, the output of the ADC slice may be measured by measure and correction unit 29460, and, in operation S29730, a gain correction may be stored in the memory 29490 for that ADC slice along with any other information relevant to the conditions under which it was collected. Once the gains for each ADC slice have been collected, in operation S29740, in a normal mode of operation, the saved gain adjustments may be applied by, e.g., the controller 29475, to the ADC that may be active in a particular slice of operation. Utilizing various implementations of devices described herein may prevent having to perform calibration at the time of manufacturing or using test equipment to be provided in the field, allowing more frequent calibrations to be performed and ultimately resulting in a more accurate and reliable operation of the device. Power amplifiers (PA) used for wireless transmissions typically have linear characteristics over a limited range of their transmission power capability. A true linear PA would produce an output signal (amplitude and phase) that is proportional only to the input signal and the gain of the PA (e.g., no amplitude or phase distortion that depends on the level of the input signal). A practical PA produces the wanted output signal (proportional to the input signal and the gain of the PA) and other non-wanted signal that may be produced due to PA non-linearity. These non-wanted signals are called intermodulation products (IM). These IM signals cause intermodulation distortion (IMD) that degrades the quality of the signal at the PA output. The non-linear behavior of the PA can be modeled and presented in few ways: a polynomial PA model, a look up table (LUT) that describes the PA input to output behavior, Volterra series for PA model with memory (in which a current PA output depends on a current PA input and also previous input signals). FIG. 85illustrates an example of a PA characteristic curve of AM/AM (input amplitude VS. output amplitude) and FIG. 86is an example of a PA characteristic curve of AM/PM (input amplitude VS. output phase variation) with the following applicable equations: It may be possible, however, to extend the linear range of the PA, producing linear amplitude and phase, by applying what is known as digital pre-distortion (DPD) prior to transmission. The DPD applies the PA a signal such that the PA output would (ideally) have only the wanted signal at its output with IMD. For example, if the PA is modeled using an AM/AM and AM/PM polynomials, the DPD followed by a PA would produce an equivalent AM/AM and AM/PM which may be close to an ideal PA. As can be seen by the dashed line in FIG. 85, the application of DPD can produce a linear gain right up to the saturation output power PSAT. In order to perform the calculation and correction by the DPD, a model of the PA may be provided. The better the model, the better the DPD correction may be applied. The PA characteristics depend on PVT-f (process, voltage, temperature and operation frequency), and the PA model may be updated in real-time or based on real-time information. In order to do this, a feedback and a sensing of the PA output may be used, as may be a feeding of the data to the digital domain. In a feedback-based design, information related to the amplifier characteristic may be fed back to the DPD so that the DPD can make the proper corrections to the signal. A phased array system, which may utilize many PAs with many antennas, allows a beam of radio waves to be electronically steered without physically moving the antennas. In these systems, it may be impractical or costly to provide a feedback signal for each amplifier. FIG. 87is a block diagram of an example of a gain model 30000 for a portion of a phased array transmitter. A radio frequency (RF) signal may be received at a phased array transmission power splitter 30010 which splits the signal into a plurality of channels CHANx that may each comprise independent components (e.g., amplifier, switch, antenna). These components may be not all identical due to manufacturing variances, and thus their performance varies (over PVT-f). FIG. 87breaks out a number of sources of variance, which may include a gain GTXn 30020 (which could be an actual gain or an attenuation if the gain factor is less than one) for the circuitry between the splitter 30010 and a PA, a gain GPAn 30022 of the PA itself to the applied signal power PTXn, a gain of the switch GSWn 30024 to the applied signal power PPAn, a gain of the antenna trace Gtracen 30026 to the applied signal power PSWn, and a gain of the antenna GANTn 30028 to the applied signal power Ptracen. Two issues might, for example, affect the IM at the output of each PA. The first is the specific characterization (for example: the AM/AM and AM/PM curves) and the second is the specific input power to each PA (for example: assuming that we have identical PA, but one of them may be handling very high input level at its input (compared to the other PAs)—this PA would produce the dominant IM). A third issue is that the loss after the PAs (lines and antenna gains) might also affect the total power and IM. Collectively, in each channel, the power may be represented by: P_chan= P_desired+ ∑_n▒〖IM〗_n where: Pdesired is the desired output signal, IM is the intermodulation distortion power for a given source, and n is the number of the source The phased array transmitter generates a single main beam that reaches the other side of the communication link. PTX represents this signal. For all the channels together, the transmitted power is: P_TX= ∑_K▒(P_(〖desired〗_K )+ ∑_n▒〖IM〗_(n_K ) ) or P_TX= ∑_K▒P_(〖chan〗_K ) The value PTX from the transmit power equation 30050 represents the total power output from the phased array antennas of the transmitter device, including the desired component Pdesired from the linear portion of the PA, and the undesired intermodulation components: P_IM= ∑_K▒∑_n▒〖IM〗_(n_K ) where PIM is the total undesired intermodulation component power. These values may be determined by an external transceiver (ET) that receives a transmitted signal by a transmitter portion of the present transceiver. Conversely, these values may be determined by the present phased array transceiver for a signal received from an external phased array transceiver (EPAT). The external transceiver does not have to be a phased array transceiver. It may be able to receive a signal from the present phased array transceiver and send back the non-linearity data. The external transceiver may be implemented as a phased array transceiver, a multi-sector transceiver, or an Omni directional transceiver, for example. FIG. 88is a block diagram of an example of a switchable transceiver portion 30100 that the transmitter model described above may represent. Here it can be seen that an RF transmission signal 30115 from other portions of the transceiver portion 30100 may be fed into the transmission power splitter 30110 (which may be an example of the transmission power splitter B4-110 modeled in FIG. 87) provides a split portion of the signal into a phase shifter 30130 that permits control of the phased array beam. This may be provided as an input to the PA 30140. The signal may be amplified by the PA 30140 and the output signal TXOUT passed through a switch(es) SW 30150, which, in FIG. 88is in a transmit position, connecting it to one of the antennas 30160 in a phased antenna array 30165. The total transmit power PTX from the equation 8750 above is shown being output from the antenna array 30165. The receive components in the transceiver portion 30100 may comprise, in each of the channels, a low noise amplifier 30170 that provides a signal to phase shifter 30180 that permits control of the phased array beam. The collective outputs may be combined by a receive power combiner 30120, and the combined RF received signal 30125 may be provided to other receiver components of the transceiver portion 30100. FIG. 88also shows the loopback signal containing non-linearity data 30190 for the transceiver portion 30100 being provided at an input of the antenna array 30165. FIG. 89is essentially a replica transceiver portion 30100’ of the transceiver portion 30100 shown in FIG. 88, but with the switches 30150 thrown in a receive configuration. When the switches 30150 are in the RXIN position, the transceiver is operating in a receive mode, and the signal received from the antenna 30160 is directed through the low noise amplifier 30170 to the receive power combiner 30120. When the switches 30150 are in the TXOUT position, the transceiver is operating in a transmit mode, and the signal from the TX power splitter 30110 is directed through the power amplifier 30140 to the antenna 30160. The description and operation of the components is not repeated here. FIGS. 90Aand 90Bare parts of a block diagram of an overall transceiver 30300 example that may contain a transceiver portion, such as the transceiver portion 30100 described above. Additionally, other components of the RF receiver 30310 portion are shown, including an RF amplifier 30312 that receives the combined signal from the receive power combiner 30120, for example as described above, and a demodulator 30314 that utilizes a signal produced by a local oscillator generator (e.g., RF synthesizer) 30340 that may be amplified or otherwise conditioned by component 30316. The demodulated signal may then be provided to an intermediate frequency (IF) amplifier 30332 before being provided to a triplexer and switch 30345 where it may be transmitted to other parts of the transceiver 30300 over a connection, for example, a coax cable 30350. A corresponding transmit portion of the transceiver 30300 may be provided as well. A signal to be transmitted may be provided over the connection 30350 and provided to an IF amplifier 30334 whose output may be provided to an RF transmitter 30320 portion. The RF transmitter 30320 portion may comprise an RF modulation mixer what utilizes a signal produced by the local oscillator generator 30340 and possibly amplified by an amplifier 30326, and the modulated RF signal may ben be provided to an RF amplifier 30322 before being sent to the transmission power splitter 30110, where the signal may ultimately be transmitted as described above, for example. FIG. 90Bis a block diagram illustrating another portion of the transceiver 30300. On the receive side, a received signal that has been demodulated down to the IF may be received via the connection 30350 and a triplexer and switch 30355. In an IF receiver 30360 portion, the IF signal may be provided to an IF amplifier 30362. Although not expressly illustrated in the drawings, the system may be designed to handle quadrature encoded signals, and the two paths shown in the IF receiver 30360 portion and an IF transmitter 30370 portion may represent an in-phase component I and a quadrature component Q of the signal, with separate paths provided for each. An IF demodulator 30364, may be provided to produce analog I/Q components of the baseband signal. This IF demodulator 30364 may receive a signal produced by, for example, a crystal oscillator 30384 and an IF synthesizer 30382. A divider 30380 may be fed by a signal coming from the frequency synthesizer 30382 and produces a reference signal to the RFEM, passed over the COAX cable. For example, if the absolute frequency accuracy is to be +/-20ppm (part per million), then an external quartz crystal (and internal crystal oscillator) can be used that has frequency accuracy of +/-20ppm. All frequency generation blocks may be fed by this frequency or a multiplication/division of this frequency. A low-pass filter 30366 and analog-to-digital converter (ADC) 30368 may be provided to supply a baseband (BB) signal to the BB processor 30390 for each of the I/Q components. The BB processor 30390 will be discussed in more detail below. On the transmit side, a baseband digital signal produced by the BB processor 30390 may be provided to the IF transmitter 30370 portion, which may include I/Q portions having a digital-to-analog converter 30378, a low-pass filter 30376, and IF modulator 30374. The I/Q signal may be provided to an IF amplifier 30372 and the IF signal may be sent over the connection 30350 via the triplexer and switch 30355. Although FIGS. 90Aand 90Bshow the connection 30350 separating units between portions of the IF stage, it may be also possible to separate the units between portions of the RF stage as well (or to not separate the units at all). In order to better describe the components of the BB processor 30390, FIG. 91is briefly discussed initially. FIG. 91is a block diagram showing the phased array transceiver 30300 that is in communication with an external phased array transceiver (EPAT) 30300’ (e.g., one combination would be a hand-held device and a 5G base-station or other types of base stations). Each of these transceivers 30300, 30300’ may operate similarly and may determine the respective power transmission from the power equation 30050, 30050’ characteristic of transmissions from the other respective transceiver (which may, for example, be true in a case in which it may be desirable to optimize the mobile device with DPD while the base station is using DPD or would rely on a different calibration of its DPD), and communicate respective non-linearity data 30190, 30190’ based on the received transmission. Although FIG. 91shows the external phased array transceiver 30300’ as being a phased array transceiver, there is no requirement that it be a phased array transceiver, e.g., it could just be a normal external transceiver (ET). The transceiver, e.g., transceiver 30300’, may be able to interpret the signal sent from the phased array transceiver 30300 and respond with the relevant non-linearity data 30190. Returning to FIG. 90B, the BB processor 30390 may comprise a modem 30392 in which the digital pre-distortion (DPD) processor 30394 may reside. The DPD may be used to apply a distortion that may be an inverse of the overall transmitter amplifier characteristic curve so that the overall transmitter amplifier may operate in a more linear manner up to the power saturation PSAT point. The control of the DPD 30394 may be provided by an internal non-linearity processor 30396, which may receive the non-linearity data 30190 sent by the ET 30300’. In one example configuration, the non-linearity data 30190 may be represented by polynomial coefficients describing the inverse curve of the power transmission characteristic curve PTX 30050. Given the nature of the sources of non-linearity, a polynomial of the fifth order has proven adequate to accurately reflect the power transmission characteristic curve PTX 30050 or its inverse in some aspects. In a further example, the non-linearity data 30190 may be represented by a look-up table (LUT) that maps the inverse characteristic. The internal non-linearity processor 30396 may process the received non-linearity data 30190 and transform it into control parameters that may be used to control the DPD 30394. The external non-linearity processor 30398 takes the power transmission characteristic curve PTX 30050’ of the EPAT 30300’ and determines the non-linearity data 30190’ that may be to be sent to the EPAT 30300’. Although FIG. 90Bshows this non-linearity data 30190’ being combined with other data and sent through the DPD 30394, it may not be necessary that this information be transmitted to the EPAT 30300’ using the DPD 30394, and the transmission could occur without using the DPD 30394. The following describes two exemplary aspects. The first is presented in FIG. 92, which is a flowchart illustrating an example of a process 30500 that may be used by the transceiver 30300, and shows a sequence in which the phased array transmitter transmits a signal (possibly using an initial DPD setting (which may be factory predefined)) that includes a level of IM that allows reception at the other side (may be a low constellation, due to low EVM) and that does not violate applicable regulations. After the other side has evaluated and sent back the non-linearity information, the DDP may be operated with close to optimal conditions and transmit higher output power and/or high data through-put (a higher constellation). In operation S30510, a transmission signal may be split into the transmission channels, such as those described above. Then, in operation S30520, the signals may then be transmitted from the antennas in each of the phased array antennas. In operation S30530, non-linearity data, such as that described above, may be received that contains an inverse of a characteristic curve for the summed outputs of the phased array antennas. In operation S30540, this non-linearity data may be translated into control signals for a digital pre-distortion processor, such as one described above, which modifies the output signal. Finally, in operation S30550, the DPD processor modified data may be transmitted by the transceiver. The second exemplary way is presented in FIG. 93showing a sequence, having similarities with that of FIG. 92, to generate a data base (e.g., a look-up table) that may allow setting correct (and close to optimal) DPD settings at the very beginning of a transmission. The similarities with FIG. 92are not repeated here. The data base can be gathered in operation S30638 over time from each operation (e.g., different receivers may be used—this does not affect the TX side to be linearized) and utilize feedback in operation S30635 received from the other side. This may improve the accuracy and span of use cases of the transmitter DPD. Operation conditions may include operation S30633: transmission frequency, active TX chains, output power level (from a power detector on the RFEM, or at an output of each chain), temperature sensor (in the RFEM), voltage sensor (in the RFEM), and the like. The operation of the LUT may optionally be combined with real-time feedback from the other side. Also, a predefined “hand shake” (e.g., a preamble or data sequence) may be utilized that would allow fast and accurate extraction of the DPD data. In operation S9340, the system may translate the non-linearity data and/or the operation conditions into DPD control data. Radio frequency receivers in modern communications devices may typically be configured to handle a significant range of input power levels. For this, a receiving amplifier may comprise a number of AGC gain settings that may amplify incoming signals of varying strength. Choosing a particular amplifying AGC gain setting to improve or maximize performance may be difficult. The large range of input power levels may be handled by the receiver by changing the level of amplification as a function of the input signal level. Low input level signals may use high amplification in order to provide a usable noise figure (NF) while high input signal levels may use a low level of amplification in order to prevent compression of the receiver. FIGS. 94Aand 94Bare parts of a block diagram of an example of an overall distributed phased array transceiver system 30700, although the concepts described herein are not limited to this particular type of transceiver. Such a transceiver system may relate to radio chain circuitry 372, as described above, but could also relate to different circuitry as well. Reception signals RXIN coming through the phased array antennas 30702 may be received by amplifiers 30703, and the amplified signal may be sent to a receive power combiner 30705. An RF amplifier 30712 may be provided that receives the combined signal from the receive power combiner 30120, for example as described above, and a demodulator 30714 that utilizes a signal produced by a local oscillator generator (e.g., RF synthesizer) 30740 that may be amplified or otherwise conditioned by component 30716. The demodulated signal may then be provided to an intermediate frequency (IF) amplifier 30732 before being provided to a triplexer and switch 30745 where it may be transmitted to other parts of the transceiver system 30700 over a connection 30750, for example, a coax cable. A corresponding transmit portion of the transceiver 30700 may be provided as well. A signal to be transmitted may be provided over the connection 30750 and provided to an IF amplifier 30734 whose output may be provided to an RF transmitter 30720 portion. The RF transmitter 30720 portion may comprise an RF modulation mixer what utilizes a signal produced by the local oscillator generator 30740 and possibly amplified by an amplifier 30726, and the modulated RF signal may be provided to an RF amplifier 30722 before being sent to the transmission power splitter 30706. The RF transmission signal may be fed into the transmission power splitter 30706, which provides a split portion of the signal into a 30704. The split portions of the signal may be provided into an input to the PAs 30707, where the signal may be amplified and the output signal TXOUT may be provided to the phased array antennas 30702. FIG. 307B is a block diagram illustrating another portion of the transceiver system 30700. On the receive side, a received signal that has been demodulated down to the IF may be received via the connection 30750 and a triplexer and switch 30755. In an IF receiver 30760 portion, the IF signal may be provided to an IF amplifier 30762. Although this is not expressly illustrated in the drawings, the system 30700 may be designed to handle quadrature encoded signals, and the two paths shown in the IF receiver 30760 portion and an IF transmitter 30770 portion may represent an in-phase component I and a quadrature component Q of the signal, with separate paths provided for each. An IF demodulator 30764, may be provided to produce analog I/Q components of the baseband signal. This IF demodulator 30764 may receive a signal produced by, for example, a crystal oscillator 30784 and an IF synthesizer 30782. A low-pass filter 30766 and analog-to-digital converter (ADC) 30768 may be provided to supply a baseband (BB) signal to the BB processor 30790 for each of the I/Q components, where the BB processor 30790 may comprise a modem 30792, which may be used to control the RF AGC gain settings. On the transmit side, a baseband digital signal produced by the BB processor 30790 may be provided to the IF transmitter 30770 portion, which may include I/Q portions having a digital-to-analog converter 30778, a low-pass filter 30776, and IF modulator 30774. The I/Q signal may be provided to an IF amplifier 30772 and the IF signal may be sent over the connection 30750 via the triplexer and switch 30755. Although FIGS. 307A and 307B show the connection 30750 separating units between portions of the IF AGC gain setting, it may also be possible to separate the units between portions of the RF AGC gain setting as well (or to not separate the units at all). A frequency divider DIV 30780 may be provided after the synthesizer 30782. FIG. 95is a block diagram of receiver 30800, which may be an example of or include an amplifier 30703 discussed above, or could be a combination of the amplifiers in the system, each having their own gain AGC gain setting(s). The amplifier may comprise or have associated with it a switch 30810 that determines a received signal, for example, an RXIN RF signal strength, and based on that determination, selects an appropriate gain setting using a control from the automatic gain control (AGC) gain setting 30820 in order to provide a relatively constant input signal for processing to the rest of the receiver circuitry. The switch 30810 may, for example, comprise a processor 30812, memory 30814, and logic (possibly residing as program instructions residing in the memory 30814 and/or hardware logic of the circuit) for determining which AGC gain setting 30820 should operate at a given power input level, and for performing power and EVM measurements and implementing the dithering operation mode described in more detail below. The switch 30810 may include any hardware or software mechanism that implements the AGC algorithm. Also, although for the sake of simplicity, the switch 30810 has been shown as a single element, the switch 30810 need not be a single device or operate on a single part of the signal (received RF signal, IF signal, baseband signal in the modem, etc.), but could be multiple devices that deal with a respective part of the signal. An improved AGC gain setting 30820 is one that produces a better signal quality measure (SQM) at a given power level. One SQM is the error vector magnitude (EVM), which, in a quadrature encoded signal, is a measure of how far points in a constellation map are from their ideal locations. The AGC gain settings 30820 illustrated in FIG. 95represent a logical construction of different levels of gain and not necessarily a physical construction of separate gain amplifiers. For example, physical gain elements may be chained together or activated in series to achieve a next level of gain, such that the AGC gain setting 2 could use elements from the AGC gain setting 1. However, there could also or additionally be separate physical AGC gain setting components to execute one or more of the AGC gain settings. FIG. 96is a graph 30900 that plots, for a given AGC gain setting of 30820, an EVM versus the received power RX PIN. As illustrated in FIG. 96, a high EVM may be due to (among other things) two causes of interest. The first cause may be a signal-to-noise ratio (SNR), where the noise is thermal noise generated by the receiver blocks. At low RX Pin, the thermal noise may be dominant and the AGC gain setting sets the RX gain to high levels of gain in order to minimize the RX NF (e.g., minimize the RX thermal noise). At these low level of RX Pin, the thermal noise may be more prominent relative to the signal, resulting in a lower SNR, thus higher EVM. The second cause may be an intermodulation distortion that results from non-linearities present in the receiver when handling high levels of input signal. As the signal at the input of the receiver is higher, it behaves in a more non-linear manner, creating a higher EVM, in order to lower the level of intermodulation distortion (IMD) in the receiver and improve the linearity to lower the gain of the receiver, thus degrade the NF (higher thermal noise). FIG. 96illustrates the effect of both the SNR and the IMD on the overall EVM, and shows a “sweet-spot” or operation range that serves to minimize the overall EVM. This curve may vary based on various curve-shifting factors, including a channel or operating frequency, including supply voltage, process variations due to manufacturing variations, and operating temperature of the device. The received power may be determined by a power level detector in the modem 30792 (FIG. 307B) or it could be determined by other power level detectors located along the receive chain, including anywhere from the antenna itself, the RF processing, the IF processing, and the baseband processing. FIG. 97is a graph 31000 similar to that shown in FIG. 96, but that includes the EVM vs. receive power curve for a number of the AGC gain settings, where the AGC gain settings have degree of overlap with each other. Although the EVM curves overlap for each received input power level, there may be an optimal AGC gain setting that minimizes the EVM for a particular received power level. In order for the system to maintain the best possible EVM, the system may switch between gain settings by selecting the appropriate switch at optimal threshold values (POPT_TH) as illustrated in FIG. 98. FIG. 98is a graph 31100 illustrating optimal threshold values POPT_TH for activating a particular AGC gain setting. In order to determine the optimum threshold values POPT_TH for a power input, the system may take measurements from the different AGC gain settings of the receiver (which may be tied to different measured temperatures) to provide optimum gain set-points that minimize EVM at all receive power points for the receiver AGC gain settings. As the curve shapes shift during operation, based on the curve-shifting factors described above, the optimal threshold values POPT_TH may shift as well, for example, in the graph 31100, from POPT_TH1_OLD to POPT_TH1. If the optimal threshold value POPT_TH has shifted, but the switchover threshold value has remained the same (e.g., remained at POPT_TH1_OLD), a sub-optimal switching will occur, introducing a higher EVM into the signal with the ultimate result being a degraded signal that may not support a desired throughput. FIG. 99is a flowchart illustrating an exemplary method 31200 that may be utilized to determine the optimal threshold values POPT_TH. The transceiver 30700 is one example that may constitute a means for operating a gain control device for a receiver, that may comprise in a dithering operation mode receiving a first input signal at a first signal power level, separately applying, using a switch, a first and second AGC gain setting to the input signal and respectively measuring a first and second signal quality measure (SQM) for the first and second AGC gain settings, and determining and storing an optimal threshold value representing a power level used to switch between using the first AGC gain setting and the second AGC gain setting based on the first and second SQMs, in a normal operation mode determining whether to use the first or second AGC gain setting for a second input signal at the first signal power level based on the optimal threshold value, but the means are not limited thereto. In operation S31210, an input signal may be received and its power may be determined. In operation S31220, a dithering operation may be initiated based on a pre-defined condition, such as the expiration of a time that may be invoked periodically, or according to some form of signal provided. Such a trigger might be a change of operation conditions, such as: frequency change by moving to a new channel, temperature or voltage change. The dithering operation allows different AGC gain settings to be used for a given receive power level, and the EVM may be measured, possibly along with a current operating temperature. The dithering operation may select an AGC gain setting on either side of the indicated AGC gain setting for a given power level, and this selection may, for example, occur randomly or according to some predefined pattern. Thus, the measurement of the EVM and/or the dithering operation does not have to occur with every received frame, but could be done less frequently, or even rarely, to minimize interference with normal operation. In operation S31230, the EVM, and optionally the temperature or other factors that may influence the shape and position of the curve, may be measured, and the value may be stored. EVM may be measured, for example, in the modem 30792, but may be measured at other places in the digital domain as well. In operation S31240, a determination may be made to determine the optimal threshold values POPT_TH. This may be done by comparing a current EVM value at a particular power level that has been the subject of a dithering operation (e.g., an AGC gain setting adjacent to one normally used at that power level), with a stored EVM value at that power level normally used. If the EVM value from the dithered operation is lower, then the threshold may be adjusted so that, in operation S31250, in subsequent normal (non-dithered) operation, the updated threshold value may be used. The amount of adjustment or the setting of the threshold may be a factor of the difference in EVM values. By way of example, and referring to FIG. 98, an input power at a power PD may be received. For the sake of the example, an original threshold POPT_TH1_OLD is to the right of PD, meaning that AGC gain setting #1 should be used. However, what may actually be measured in the dithered operation (which dithers to use AGC gain setting #2, even though AGC gain setting #1 would be indicated in normal operation) is what is shown in FIG. 98. As illustrated, the EVM value for the AGC gain setting #2 operation may be lower than that for the AGC gain setting #1 operation. Therefore, the system determines that it should move the threshold point POPT_TH1 to the left so that it occupies the point shown in FIG. 98. Thus, in a subsequent normal mode operation, AGC gain setting #2 will be used at power level PD instead of AGC gain setting #1. The difference in EVM values for the two different AGC gain settings may dictate how far to move the threshold point POPT_TH1. Additionally, some knowledge about the shape of the power vs. EVM or SQM curves may be utilized to more accurately determine the threshold point POPT_TH1. Measured values of AGC gain setting, gain, EVM, temperature, and other values or parameters associated with the measured values and thresholds may be stored in memory, such as in an LUT, for subsequent use. If the EVM at a current operating temperature or other parameter has been previously determined, then that value may be used in a normal (non-dithering) operation mode. If not, then an interpolation may be performed between two temperatures or other parameters that were previously captured. FIG. 100is a block schematic diagram of a radio frequency (RF) phased array system 31300 illustrating a configuration for a first method of operation. The system may incorporate parallel receive circuitry 382 and/or one or more of combined receive circuitry 384, as described above, or may incorporate other forms of receive circuitry. A plurality of antennas 31310 each have their signal processed by an RF phase shifter 31320 as well as a variable gain amplifier (VGA) 31330 that may be used to adjust each transmitted (or received) signal. These transmitted signals may be split by a splitter 31340 (or received signals may be combined by a combiner 31340). This may be a form of phased array systems. One of the system’s 31300 benefits may be simplicity, since only one mixer 31350 and baseband chain that include a sample or track and hold device 31360 and an analog to digital converter (ADC) 31370 may be used. The system 31300 may have one or more of the following characteristics: a) lack of scalability (adding several paths at RF frequencies forms a bandwidth bottleneck), b) added noise figure in the receiver (since noisy phase arrays and VGAs may be added nearer to the antenna), and c) added power consumption (two blocks that enable phase array systems operate at millimeter wave frequencies). FIG. 101is a block schematic diagram illustrating another topology of a phased array radio transceiver that may be referred to as a local oscillator (LO) phased array system 31400 (refer to FIG. 100for a description of the individual components). In this topology, the LO phased array system 31400 still relies on a VGA 31330 in the signal path, but the phase shifter 31320 may be transferred to the LO path. The benefit of this topology over an RF phased array system 31300 as shown in FIG. 100may be reduced noise. Another characteristic may be that several mixers 31350 and LO phase shifters 31320 may be used (one for each antenna 31310). Routing LO signals operating at millimeter wave frequencies may be difficult, which is why this approach may be considered to be non-scalable in some cases. LO phased array systems 31400, however, may be more promising with all-digital PLLs (ADPLLs), since the phase shifting can be accomplished digitally within the ADPLL loop. This eliminates use of RF phase shifters (which may be costly in terms of power consumption and introduce distortion and insertion loss in the signal path). Phase shifting within the ADPLL also mitigates LO distribution for large phased-array systems. FIG. 102is a block schematic diagram illustrating a third alternative to phased array radio transceiver design and may be referred to as a digital phased array system 31500. In this topology, the entire transceiver chain may be replicated for each antenna 31310, including the sample or track and hold device 31360 and ADCs 31370. The phased array combination may be performed in the digital domain. Its characteristics may include increased complexity (chip area) and power consumption. Its increased power consumption comes not only from the transceiver block, but also the digital backend where the phased array combination occurs. One main benefit, however, may be its ability to support multiple users simultaneously, with each user taking the advantage of the full antenna array gain. This support, however, may come at a cost of using a dedicated digital combination path for each user. In all the above phased-arraying strategies (phased array system 31300, LO phased array system 31400, and digital phased array system 31500), there may be a recombination point (combination node/combiner 31340) where the sum of all the phased-array receivers (or transmitters) may be combined with different amplitude weights and/or phase shifts. This combination node 31340 may be often a bottleneck in phased-array receivers in terms of performance and complexity. If a different size of phased-array is desired, this combination node 31340 may be redesigned, significantly increasing the design complexity. This aspect of phased-array design may be a major obstacle to the scalability of phased-arrays. In some aspects of this disclosure, a scalable phased array radio transceiver architecture (SPARTA) that scales well with size is provided. This may greatly aid in reusability of this architecture for multiple applications and products, reducing time-to-market. The proposed architecture may also be self-configurable, easing the programmability of the device. In addition to supporting conventional modes of operation, the SPARTA may also be capable of supporting new modes of operation that enable better phased array gain or low power consumption, as described below. FIG. 103is a block diagram of an example cell element 31600 of the SPARTA array. As this figure shows, the SPARTA array cell element 31600 may comprise a transmitter (TX) 31610, receiver (RX) 31620, local oscillator (LO) 31630, and digital block (DIG) 31640. A set of multiplexers and de-multiplexers 31650 may be tiled on the four edges of the SPARTA array cell element 31600 to allow communication with adjacent cells. This cell element 31600 is one example that may constitute a means for operating a phased array radio transceiver, that may comprise transmitting and receiving a signal with a plurality of tiled and interconnected transceiver cells, but the means are not limited to this process. There may be both analog and digital parallel buses 31660 that connect the SPARTA array cell 31600 to neighboring cells allowing tiling of the cells. Note that the TX 31610 and RX 31620 can have either single or multiple receivers and transmitters, allowing multiple RX and TX cells to share a single LO 31630 (to save power consumption). A crystal oscillator (XO) signal may be buffered between all cells. A loop back may be used to measure and calibrate out delay introduced by the XO buffers in each cell element 31600. Each cell element 31600 may also have control signals that connect it to neighboring cells as well as global control signals that may be static. The SPARTA array cell element 31600 may further comprise an I/O and phase combining unit 31670 that also includes analog and digital coefficient sets and pipeline elements. Location connection ports 31680, discussed below, may also be provided. FIG. 104is a block diagram illustrating a tiled SPARTA array of cells 31700. As the figure shows, the array 31700 of identical cells 10300 are shown. This means that the cells 31600 (die) may be copy exact. The communication between the cell elements 31600 comprises analog and digital buses 31660. The width of the buses 31660 may be equal to the number of simultaneous users that the phased-array system can support (discussed below). Each SPARTA array cell element 31600 may be connected to only adjacent cell elements. This can help provide the scalability of the proposed approach. In some aspects, this proposed architecture advantageously enables dicing of the wafer into different shapes for different applications. FIGS. 318 and 319 are pictorial diagrams of wafer dicing. FIG. 105illustrates a wafer 31800 with diced portions 31810 of the SPARTA cell elements 31600 for low-power applications, and FIG. 106illustrates a wafer 31900 with a diced portion 30910 of the SPARTA elements for high-performance applications. As FIG. 105shows, a different number of elements may be diced for varying system level requirements. In some low-power applications, only four SPARTA elements may be used, for example. In high performance systems, such as base stations, the entire wafer may be used, as shown in FIG. 106, for example. In other words, the same wafer can be filled with different form factors and product skews while having copy-exact wafers processed. The level of wafer integration to reduce packaging cost may be balanced with a yield resulting from a larger die area, resulting in a maximum array size for a maximum yield. FIG. 107is a pictorial illustration of a combined 32000 SPARTA array 32010 that may be wafer processed and combined 32000 with an antenna array 32020. With this processing step, an antenna array 32020 layer can simply be meshed to provide a full system solution. The proposed phased array system may also have a self-aware configurable structure, described as follows. Identification numbers (IDs) may be determined at power up by an ID assignment routine. This enables the system to know how many SPARTA array cell elements 31600 are used in the array 31700. The four sides of the chip may be referred to as north (N), south (S), west (W) and east (E). In one example identification scheme, illustrated by FIG. 104, the ID #1 may be assigned to the NW corner cell element 31600. The NW corner may be determined by location connection ports 31680 that can detect whether the port may be open or connected with another port. For example, if both the N and W ports are open, ID #1 may be assigned to that cell element 31600. That cell element 31600 then initiates a sequential numbering sequence, where the ID number may be incremented by one and passed to the east cell element 31600. If the current cell element 31600 has no E port connection and it received its ID number from the west cell element 31600 (e.g., cell #4), then it passes the ID number to the south cell element 31600 (illustrated by #5). If the current cell element 31600 has no E port connection and it received its ID number from the north cell element 31600, then it passes the ID number to the west cell element 31600 (if connected, otherwise it also passes the ID number to the south cell element 31600). A similar algorithm may be followed for the west boundary of the array 31700. This routine may be continued until a SE or SW corner cell element 31600 is reached. At that point, the ID numbering is complete, with each cell element 31600 having a unique identifier within the array. Also, when an ID number of a cell is assigned, the cell element 31600 may undergoes a local amplitude and phase calibration of both its transmit and receive amplitude and phase values. Other numbering schemes that produce unique identifiers within the cell element 31600 may be possible as well. The SPARTA array cell elements 31600 may support modes of operation such as: a) LO phased array operation mode, b) digital phased array operation mode, c) analog phased array operation mode, and d) hybrid operation mode. All may be implemented using the SPARTA array cell element 31600 that allows size scalable operation. FIG. 108is a block diagram showing a SPARTA array cell element 32100 (which may be an implementation of the SPARTA cell 31600) that may be used for digital phase array tiling. In the digital phased array operation, the entire transceiver element in the SPARTA cell 32100 may be used. In the receive mode, the received signal may be converted to a digital signal, then vector summed with the SPARTA cell element 32100 having the previous ID number. To maintain scalability, the summation between each stage may be pipelined. This may be provided in order to limit the loading on the data bus lines. Also, to support a total of k users, k bus lines may be used, one for each user. Since the number of bus lines may be fixed in hardware, the SPARTA cell element 32100 may be designed with the hardware to support the maximum of number of users that most systems would use to support in digital phased array operation. Also, since the data lines may be pipelined, an internal pipeline register of depth of ND may be maintained. The pipeline depth ND limits the maximum SPARTA array size, where the individual elements may be connected in the digital phased array mode. As the figure shows, k digital buses 32110 may be present in all directions (N, S, E, W). Digital multiplexers on both the transmitter (TX) 32120 and receiver (RX) 32130 blocks choose which cells 32100 to receive input from and which cells 32100 to output to. FIG. 109is a block diagram that illustrates LO phased array pipelining between adjacent cell elements 31600 in the LO phase combining mode. In the LO phased array combining mode of operation, each cell element 31600 receives its phase shift from a central control unit. In the receive path, the outputs of all mixer stages may be summed in the analog domain, bypassing the analog-to-digital converter (ADC). Only one ADC 31370 (FIG. 110) then takes the combined outputs and translate these into digital form. This combination may be performed through an analog bus 31660 that interfaces between the adjacent SPARTA cell elements 31600. This has the benefit of significant power reduction, since the ADC 31370 may be one of the largest power consuming blocks in a phased-array system. The LO phase shifting mode of operation, as discussed above, may be one way of LO phased array combining. The SPARTA architecture provides a novel scalability of this approach. In order to maintain scalability, the analog bus 31660 line may be “analog pipelined” through a sample and hold vector bus of pipeline depth NA. The pipeline depth NA may limit the maximum SPARTA array size, where the individual elements may be connected in analog phased array mode. The analog values between each cell may be summed by a switched-capacitor analog integrator 32210. The figure illustrates the integrator summing with the prior cell element 31600 and delay 10920 before being communicated over the bus 31660 connecting the cells. The entire SPARTA array 31700 with the LO phase shifting is illustrated in FIG. 110, which is a block diagram showing the SPARTA cell tiling using an LO phase array and illustrating active data converter ADC. FIG. 111is a block diagram that illustrates a SPARTA array 31700 in hybrid mode, where each row may be tiled in an LO phase shifting and sharing a single ADC 31370. Multi-user operation may be supported in the LO phased array mode of operation by using a hybrid mode of operation. In this hybrid mode of operation, the array 31700 may be divided hierarchically, where lower level cells may be combined in LO phased array mode and upper level cells may be combined in digital phased array mode. In some aspects, only one pair of data converters may be used per LO phased array cluster. In some aspects, no pairs of data converters may be used with some or all of the array clusters, and in some aspects, more than one pair of data converters may be used per LO phased array cluster. The configuration illustrated in FIG. 111offers at least two benefits. First, it provides a trade-off between power consumption and array gain efficiency which may be controlled through software. Second, it offers a method to maximize the array gain per user since the total number of SPARTA cell elements 10300 that may now be used is N=ND*NA. FIG. 112is a block diagram illustrating pipelining of the analog phased array combining between adjacent cell elements 31600 for the analog phased array combining operation mode. This mode of operation is similar to the LO phased array combining (and hybrid phased array combining) in that only one data converter per user is active, for example. The analog pipelining may be augmented with a weighted sum combining, as shown in FIG. 112, where a SPARTA cell 31600 is illustrated with analog phased array combining with a novel ability to pipeline the phased array combine in the analog domain. The function A1(s) 32510 and A2(s) 32520 may be general complex functions that are realizable in the analog domain. Different analog coefficient weights may be realized by digital combining of different analog components (such as resistors, capacitors or current sources). Along with the analog summer 32210 and delay 32220 described above, a pipelined vector summation operation may be realized. In this type of operation, in some aspects, only one data converter per user may be active, eliminating significant power consumption per phased array cell 31600. The exemplary modes of operation are summarized in Table 10 below. The maximum number of simultaneous users that the array can support in some aspects may be M users (dictated by the parallel analog and digital bus widths). The total maximum number of users may be N array elements (dictated by array size, and digital and analog pipeline depths). The “aperture” refers to the number of elements that may be taken into account when calculating the antenna array gain. Use of all ADCs for digital combining allows for multi-user/multi-beam operation, with digital pipelining for large arrays (for size scalability), but consumes greater power. Use of the entire array aperture per user with only one ADC per user by analog baseband combining with parallel analog pipelining stages (one per user) may save power. Use of LO phase shifting and a single ADC for a single user saves ADC power and uses analog pipelining to scale to large arrays. It provides an increased or maximum level of interference mitigation for the ADC. The hybrid configurations may use sub-sections of the entire array per user with LO combining and one ADC per user. Users Aperture Combining/ Beamforming Parallel Analog Coefficient Sets Data converters Parallel Digital Coefficient Sets 1 Full LO 1 1 None M Full Digital None N M M 1/M LO 1 M Up to M M Full Analog M M Up to M Table 10 Summary of SPARTA modes of operation Disclosed herein according to some aspects is a system that utilizes IL at a sub-harmonic frequency to enable high-speed phase modulation at a lower power than equivalent fundamental-frequency modulation. Such a technique may be particularly useful at mmWave frequencies to efficiently implement a large available fractional bandwidth (and therefore high throughput). Direct digital modulation may be achieved through capacitive digital-to-analog converters (DACs) modulating a free-running frequency of an injection-locked oscillator at a subharmonic of the carrier signal. The modulated signal may be then used to further injection-lock a mmWave oscillator operating at the carrier frequency. As opposed to direct fundamental frequency modulation, such sub-harmonic injection uses lower phase modulation range, thus enabling lesser injection strength and therefore lower power in some aspects. As opposed to a direct VCO modulation-based technique using fast start/stop oscillators, in some aspects the proposed technique: a) obviates VCO frequency mismatch among phased array elements; and b) removes limitations on the carrier frequency of being an integral multiple of the baseband sample-rate. Classic narrowband phased-array transceivers use RF/LO/baseband phase shifting for beamforming. When such a technique is scaled to higher fractional bandwidths and/or a large number of phased array elements (such as in massive MIMO), this technique results in significant inter-symbol-interference (ISI) and therefore signal-to-noise ratio (SNR) degradation. By using IL-based delay modulation, this architecture enables use of true-time delay-based beamforming. By directly delaying the modulated carrier on each phased array element, this technique eliminates any such degradation. Classic fundamental frequency LO distribution may be challenging at mmWave frequencies and contributes significantly to overall power consumption, especially when distributed to a multi-element array with a large silicon die size. Instead, by employing two successive sub-harmonic injections (with in-built modulation and beamforming), in some aspects this technique enables low frequency (and hence low-power) LO distribution. As a result, the architecture can scale very efficiently to a large number of array elements. The following various aspects may be incorporated into the systems described herein. With regard to the locking frequency, a first aspect may be utilizing IL at a sub-harmonic frequency, unlike systems that may utilize IL at the fundamental frequency. With regard to phase shift/modulation range, in one implementation, the phase modulation may be one-third of the output frequency, so only a ±60° range may be used for a full ±180° coverage. This eliminates an additional polarity inversion and saves power. This may be an improvement over a design that generates phase symbols up to ±90°. Generating the full ±180° coverage for phase modulation therefore uses additional signal polarity inversion. Since such a block operates at the carrier frequency, it may be a significant power overhead. With regard to injection strength, in the present design, according to some aspects, because of the reduced phase range, the injection strength and therefore the LO distribution power can be lower, in contrast to a design where a strong IL may be used to achieve the ±90° phase shift. With regard to LO distribution, in the present design, according to some aspects, if the output mmWave frequency is f0, by employing a two-stage sub-harmonic IL, the LO distribution may be reduced to f0/9, thereby significantly reducing power consumption and design complexity. This contrasts with a design in which the LO distribution is at the fundamental frequency, which has a significant power overhead for mmWave frequencies and/or a large number of phased array elements. With regard to beamforming, in the present design, according to some aspects, a capacitive DAC-based IL may be used for beam-forming, which constitutes true time delay beam forming. Such beamforming may be fundamentally free of ISI. This may be an improvement over a design that deploys phase shift in the base-band/LO or RF domain and utilizes narrow-band phase-shift based architectures which create ISI for a wideband and/or a multi-element phased array. In addition to being a true time delay-based architecture, in the present design, according to some aspects, since the phase-shift may be only a function of the cap-DAC setting, the baseband modulation signal has a significantly relaxed jitter specification. This relaxes the power overhead of distribution to a multi-element phased array. This may be an improvement over a design that uses a technique for rapidly starting and stopping an oscillator to enable true time delay beamforming and in which there may be a very stringent jitter specifications on baseband modulation signal distribution since this jitter directly translates to phase shift using a mmWave carrier, making it challenging to scale to a large number of phased array elements. The present design, according to some aspects, may be a frequency locked system, scalable to large number of elements and may have no limits on symbol rates. This may be an improvement over an architecture that is not frequency locked, which, in addition to scalability issues (due to frequency mismatch among phased array elements), also limits the baseband symbol rates to very specific values. FIG. 113is a schematic diagram illustrating components for an IL-based phase modulation circuit 32600, according to some aspects, which exploits phase shift characteristics of a locked oscillator. The modulation circuit 32600 may incorporate up-conversion circuitry 350, as described above, or may incorporate other forms of up-conversion circuitry. A data signal 32610 (illustrated by way of example in FIG. 115) may be provided to an oscillator tank circuit 32620 comprising a capacitive DAC 32625. This circuit 32600 is one example that may constitute a means for operating an injection-locked modulation circuit for a phased array transceiver, but the means are not limited to this process. FIG. 114is a graph 32700 that illustrates how, a center frequency of the oscillator 32620 may be changed with respect to the locking frequency fINJ 32630, the output phase and amplitude change, while the frequency 32635 is still locked to the locking injection frequency fINJ 32630. By utilizing a capacitive DAC 32625 in the oscillator 32620, one can generate multiple phase symbols within the phase shift range in a mostly or purely digital fashion. FIG. 115is a timing graph 32800 illustrating two symbols with phases φ1 and φ2 being generated by controlling the cap-DAC 32625 with baseband modulation bits as the data input 32610. In this circuit 32600, the injection frequency 32630 may be the third sub-harmonic of the desired center frequency f. This leads to significantly lower power consumption in the LO distribution network. In older designs, the IL phase shift range may be typically limited to ±90°, which is to be implemented with a strong injection at a high power cost. Furthermore, in the older designs, to ensure a full ±180° coverage of phase symbols, an additional phase inversion block (such as a Gilbert cell current commutator) may be typically used, leading to even higher power consumption. FIG. 116is a block diagram for an IL-based phase modulation circuit 32900 with a full 360° phase modulation using a cascaded sub-harmonic injection-locked architecture with respect to the carrier frequency fCARRIER 32940. FIG. 116shows how the phase shifting at the third sub-harmonic (fCARRIER/3) frequency 32635 of the carrier frequency fCARRIER 32940 uses only ±60° of phase shift, which, after tripling, translates to the full ±180° coverage at the fundamental frequency fCARRIER 32940. This sub-harmonic modulator may be in turn injection-locked to its third sub-harmonic fCARRIER/9 32930 in the cascaded design. This design eliminates a traditional (and typically band-limited) up-conversion mixer and in-phase/quadrature (I/Q)-based transmitter elements, thereby reducing power consumption. Another aspect of various designs disclosed herein is the ability to incorporate a true time delay based beam forming using the same architecture. For a phased array system, where each antenna may be fed by one of these injection-locked, phase modulated oscillators, the relative delay between the elements can also be tuned by using the same cap-DAC based phase shifting. FIG. 117is a combination graph 33000 that illustrates a true time delay based beam forming in which elements one 33010 and two 33020 may be being fed the same baseband data signals (“11”, “00”) 33030 at two different offsets (0, ΔT), leading to lagging or leading waveforms which emulate a true time delay based signaling. Conventional RF/LO/baseband phase shifting architectures cannot generate true time delays that may be used for beamforming with wide fractional bandwidths and multi-element phased arrays. FIG. 118is a schematic block diagram illustrating an example architecture of a four-element phased array transmitter 33100 that implements combining harmonic IL based phase modulation with true time delay beam-forming. A phase-locked loop (PLL) 33110 (i.e., third sub-harmonic fCARRIER/9 32930) at 1/9th the carrier frequency fCARRIER may be utilized in the central locking network thereby using a much lower power LO distribution network. Both the modulation and beam forming occur through the IL mechanism in the oscillator 32635 tuned at fCARRIER/3. This enables increasing or maximizing the phase shift range thus ensuring full ±180° phase symbol coverage as well as an extended beamforming range. Amplitude modulation can then be incorporated into the system by using polar architectures like digital PAs 33120 for power back-off efficiency improvements. The signal may then be output via a phased array antenna 33130. The architecture may be lower power than older architectures and less sensitive to baseband signal distribution jitter (which translates into a higher power for a larger number of elements). As a result, the proposed arrangement scales power-efficiently to an array with, for example, tens of elements. FIG. 119is a block diagram for an IL-based phase modulation circuit 11900 similar to the one shown in FIG. 116, showing an example of an injection-locked oscillator at operating at 1/3 of the carrier frequency fCARRIER, and in which the phase modulation and beam forming may be combined into single block without the use of I/Q mixers or phase shifters. A multiplier, illustrated as a tripler 33240 in the FIG., for frequency and phase multiplication may be provided. Although a value of three is used here, another integer N could be used both as fCARRIER/N for 33230 and 32635, and the multiplier ×N for the multiplier 33240. Beneficially, higher N values result in a lower frequency and a lower power distribution, as well as a relaxed injection locking. However, a disadvantage of higher N values may be a lower fractional bandwidth. With lower values of N, there may be a higher speed of modulations and higher fractional bandwidth, and also more efficient multiplication. However, this results in a higher frequency distribution. FIG. 120is a block diagram for an IL-based phase modulation circuit 33300 similar to the ones shown in FIG. 116and 332, showing an example of an injection-locked oscillator at operating at 1/2 of the carrier frequency fCARRIER, and in which the phase modulation and beam forming may be combined into single block without the use of I/Q mixers or phase shifters. A doubler 33340 for frequency and phase multiplication may be provided. Additionally, a Gilbert quad / polarity switch 33345 for and polarity flip and frequency and phase multiplication may be provided. By using fCARRIER/2 33335 instead of fCARRIER/3, and the Gilbert quad / polarity switch 33345, a wider fractional bandwidth may be achieved, and only ±60° of phase shift is used. Furthermore, there may be no distribution at fCARRIER, which saves power. Various systems and methods are disclosed for dealing with wireless baud-rate clock data recovery (CDR) that utilizes the independent I/Q streams, such as 16-QAM. FIG. 121is a pictorial diagram illustrating a constellation map 33400 for QPSK pulse-amplitude 2 (PAM2) modulation, and the respective I and Q values 33410 possible. FIG. 122is a pictorial diagram illustrating a constellation map 33500 for 16-QAM (PAM4) modulation, and the respective I and Q values 33510 possible. FIG. 123is a pictorial diagram of a design for a PAM2 modulation timing estimator 33600 along with a table 33650 that may be used to determine a timing adjustment (based on a calculation of ZK) and a circuit block diagram 33670 for determining the values. These circuits may incorporate baseband processing circuitry 392 as described above, or may incorporate some other form of baseband processing circuitry. In this diagram 33670, for PAM2 there are two data levels, plus one and minus one. From the input stream, a data value DK and an error EK may be determined. If the data is plus one, then the sign is plus one and the error is plus one. If the data is lower than plus one and greater than zero, the data is plus one and the error is minus one. A value ZK may be calculated using current data, previous data, current error, and previous error. If Z is positive, then the sampling phase isearly. If Z is negative, then the sampling phase is late. The sampling phase may be adjusted based on the calculated Z values. This is the baud rate CDR for PAM2. However, extending the concept to PAM4 (16-QAM) represents a novel approach, and a determination of applying baud rate CDR in this modulation context is illustrated in the following discussion. Referring to FIG. 124, which is a first estimator table 33700 of data and error values provided according to a first technique, the first estimator table 33700 shows a possible application to the multi-bit values associated with 16-QAM. Using the error values shown in the table, the CDR works, but in a sub-optimal way. FIG. 125is a graph 33800 illustrating use of the equation for Z and the first estimator table 33800. The PAM2 (QPSK) curve 33810 illustrates a correct locking point 33830 of the CDR as it transitions from 0.5 to -0.5, crossing over the 0 value at time 1. However, for the PAM4 (16-QAM) curve 33820, although it also shows a crossing of the correct locking point 33830 at time 1, there are also two false locking points 33840 during which a transition from a positive to a negative value occurs, but which should not serve as a locking point of the CDR. Since the table 33700 produces these false locking points, it may be not an acceptable solution. FIG. 126is a second estimator table 33900 illustrating a second exemplary technique, in which the error values are all minus one, except above the plus three values and below the minus three value. FIG. 127is a graph 34000 of the Z function using the second table 33900. First, for reference, the function for the first technique (PAM4 / 16-QAM) 33820 is re-plotted on this graph 34000, along with the correct locking point 33830 and the false locking points 33840. Next, the function of the second technique 34010 is plotted and may be based on values calculated with the second table 33900. As may be seen in the graph 34000, the function of the second technique 34010 has no false locking points 34020 at the places where they exist for the curve 33820 based on the first table 33700. Therefore, the second table 33900 values represent an effective CDR. The graph 34000 shown in FIG. 127does not include multi-path intersymbol interference (ISI) or noise, and these would have some bearing on the frequency of false locks, even using the second table 33900. Under certain circumstances, the second table values 33900 could be substituted with other values (e.g., EK +1, +1, -1, -1, +1, +1, -1, +1), and some determination could be empirically measured and/or made as to which set of values produces the best outcome under a particular set of circumstances. FIG. 128is a block schematic diagram of a typical baud rate CDR loop for wireline 34100, having some logic calculations 34110, a phase detector (MMPD) 34120, majority vote 34130 filtering, and a digital loop filter 34140 (second order filter) with an integration path on the top having an accumulator, and the proportional path on the bottom. An accumulator also follows the digital loop filter 34140, with a lookup table (LUT) and further processing. FIG. 129is a block schematic diagram of a wireless CDR loop 34200, having both an in-phase (I) and quadrature (Q) inputs. Additionally, this loop 34200 has a mode unit 34210 that may comprise portions of the CDR circuitry and that that receives the two data (I, Q) outputs from the majority voting blocks. FIG. 130is a table 34300 containing various mode values and adjustment indications that may be used by the mode unit 34210 to determine an adjustment of the sampling phase. In mode zero, if early and late are both zero, then there is no decision and the current sampling phase may be maintained. In mode one, if early is one, then the signal is early, and the sampling phase may be moved to a later point. In mode two, if late is one, then the signal is late, and the sampling phase may be moved to an earlier point. In mode three, similar to mode zero, if early and late are both one, then there may be no decision. In mode four, the Q output may be not used and only the I input may be used. Mode five is the same, except it only uses the Q input. In the case of mode six, if either I or Q is early, then the signal is early, and the sampling phase may be moved to a later point. If either I or Q is late, then the signal is late, and the sampling phase may be moved to an earlier point. Mode seven is similar but it is an “and” function as opposed to an “or” function. So both I and Q are early in order to move the sampling phase to a later point, and vice versa. Using this mode unit 34210 in combination with the mode table 34300, the probability of a false lock can be reduced. Recalling that the ISI and noise can create a false locking, one aim may be to reduce the probability of a false lock. Because the wireless communications have two independent data streams, a system can utilize both of these streams. Using both I and Q for the baud rate CDR significantly reduces the probability of false locks. More settings could be added to the table to deal with different situations, and there are many logic combinations that could be added to the table. For example, not I and Q, and so on. The mode may be selected according to various criteria, although modes that utilize both the I and Q channels tend to be more robust, and thus, modes six and seven tend to be favored. In a first example, when operating in QPSK modulation scheme, which may be very robust and not generally subject to false locking, QPSK training signals may be used to find the correct lock point first using any mode. Next, the mode may be set to mode six (I or Q) or mode seven (I and Q). Both of these modes are looking at both the I and Q streams—which may be more robust than looking at a single stream, and can reduce the probability of a false lock. In a second example, if the false lock points of the I and Q signals are different, then mode six or mode seven may be used to remove the false lock point of the combined graph in many cases. In a third example, if either I or Q has two levels, such as when using PAM2 modulation, then it may be possible to set the mode to mode four or five (but modes six and seven may work here too, for example). As noted above, in general, considering both channels produces better results, but this may be not always the case. In some instances, ignoring one of the channels will produce a better result. In a fourth example, the I channel does not have significant ISI, but the Q channel does, so mode four may be selected as providing the best results. The mode settings may be changed dynamically. In this instance, the modes may be represented by three bits, and these can be changed in real time, as various conditions may be detected. For example, if a transmitter sends training signals, but these are not received by the receiver, then the mode may be changed to see if the training signals can be received in a different mode. It may be also possible to do some form of dithering. For example, mode four could be chosen for some time period, and then we can switch to mode five for the next time. So mode four and mode five could be dithered, and the conditions may be detected and monitored to determine which mode may be better or best at a particular point in time and in response to changing conditions. This concept may be generalizable to 64-QAM or higher modulation mode for larger data bit values. For the higher modulation modes, a table may be created similar to the table 33900 of FIG. 126, with plus one provided for the error at the extremes, and minus one for other values. Some aspects of the present disclosure relate to the use of low-resolution ADCs for low power MIMO systems and provide a new near-optimal signal power estimator for AGC design in receivers with low-resolution analog to digital converters (ADCs), targeting low power low latency applications. The present disclosure provides a near maximum likelihood power estimation algorithm which reduces the effect of quantization noise and increases accuracy of the power estimation significantly when the received signal power is above the dynamic range of ADCs. Accurate power estimation reduces latency of MIMO communication systems and allows use of low-resolution ADCs for low power MIMO systems. This solution does not employ changes to the AGC feedback loop and does not use a high-resolution ADC for single-input-single-output (SISO) and MIMO systems, and it also does not use AGC circuitry at each antenna output of MIMO systems. Therefore, the proposed solution may be power efficient. Using an average power calculation with a low-resolution, ADC has a high estimation error which also increases latency (settling time). Therefore, the proposed solution herein has high accuracy and low latency. In order to reduce the total power dissipation at the ADCs, the systems and methods described herein may in accordance with some aspects: 1) utilize low-resolution ADCs at each antenna output and a single digital AGC feedback loop; 2) for each of the quantitation bins (in-phase/quadrature signal (I/Q) quantization bins together), calculate or simulate a probability of a received signal for some set of quantization bins and create look-up tables; and 3) count a total number of samples falling into some particular set of quantization bins, and determine the power level from the look-up table with respect to the counted number of samples. Some aspects of the present disclosure provide a power detection algorithm with any type of constellation and channel, and any number of ADC bits resolution by using properties of this optimal detection solution. The functionality of the AGC at the receiver may be to maintain a constant amplitude at the input of an ADC. In this disclosure, in accordance with some aspects, a receiver system with low-resolution ADC and a new power detector algorithm is proposed. FIG. 131Ais a block schematic diagram of an example AGC circuit 34400, which may be implemented at a receiver where an amplitude of the received signal varies during the operation of the receiver. The AGC circuit 34400 may incorporate digital baseband circuitry 310, as described above, or may comprise other forms of digital baseband circuitry. A signal may be received at an antenna 34410 and may be fed into an RF amplifier 34415. The signal may be provided to a mixer 34420 that, using a local oscillator, converts it from an RF to an intermediate frequency (IF) signal. The IF signal may be provided to a variable gain amplifier (VGA) 34425, and the output may be provided to a sample-and-hold (S/H) circuit 34430 where it can be digitized by a low-resolution ADC 34435. A portion of the digital signal may be provided as an input to a power determiner 34440. The output voltage may be combined 34445 with a reference voltage VREF and provided to a loop filter 34450. The loop filter 34450 utilizes an output as a control to the VGA 34425, thereby completing the control loop. FIG. 131Bis a flowchart of an example AGC process 34460 comprising receiving a plurality of quantized signals from a quadrature modulated signal S34465, assigning the quantized signals into regions of a constellation map made up of in-phase (I) / quadrature (Q) quantization bins according to their quantized power level S34470, determining a maximum likelihood estimator (MLE) based on the assigned quantized signals S34475, estimating a power based on the MLE S34480, and adjusting a variable gain amplifier for further received signals based on the estimated power S34485. The AGC circuit 34400 is one example that may constitute a means to perform a method for automatic gain control (AGC) of a radio-frequency (RF) receiver, but the means are not limited thereto. FIG. 132is a constellation graph 34500 for quadrature encoding that illustrates quantization bins for low-resolution ADCs with b=〖log〗_2⁡(2n) bits in each of the I/Q components of a receiver signal in a single antenna receiver system. The received signal after quantization can be written as follows: y_(q,i)=Q(h_i x_i+n),i=1,…,N, where N is the total number of samples. Here, x_n is a channel input signal and may be selected from a constellation of size M such as 16-QAM, 8PSK, 64-QAM, BPSK, etc., h_n is the channel gain, and n is additive white Gaussian noise (AWGN) with a zero mean and unit variance. In the above equation, Q(┤) is a quantizer and the threshold levels of the quantizer are denoted as t_j,j=-n,…-1,0,1,…,n, such that t_(-n)=-∞ and t_n=∞, and hence accordingly 〖Re{y〗_(q,n)}=(t_j+t_(j+1))/2 when 〖t_j1. In some demonstrative aspects, for example, transistors 376120, 376130, 376140 and/or 376150, may include FETs, metal oxide semiconductor FETs (MOSFET) transistors, bipolar junction transistors (BJTs), and/or any other type of transistor. The MOSFET transistors may include a negative MOSFET (NMOS) and/or a positive MOSFET (PMOS). For example, the BJT may include a Negative-Positive-Negative (NPN) transistors and/or a Positive-Negative-Positive (PNP) transistors. In some demonstrative aspects, for example, transistors 376120, 376130, 376140 and/or 376150, may include NMOS transistors, PMOS transistors and/or a combination of NMOS and/or PMOS transistors. Advantageously, the combination of NMOS and PMOS transistors may reduce the number of components in ABDSC 376100 such as, for example, DC block capacitors, reduce parasitics of the transistors under different biasing conditions and/or may improve the overall performance of ABDSC 376100. In some demonstrative aspects, ABDSC 376100 may include a resistor 376180, e.g., operably coupled to transistor 376120. For example, resistor 376180 may have 150Ω resistance, and/or any other suitable value configured, for example, at least for biasing the drain (D) of transistor (Q1) 376120. In some demonstrative aspects, ABDSC 376100 may include an active load 376180, e.g., resistor. For example, active load 376180may include, for example, a transistor configured to be in its triode region. In some demonstrative aspects, ABDSC 376100 may include a Direct Current (DC) voltage source 376160, for example, operably coupled to provide DC voltage to a gate (G) of transistor 376120. In some demonstrative aspects, ABDSC 376100 may include a DC voltage source 376170, for example, operably coupled to provide DC voltage, e.g., through resistor 376180, to a drain (D) of transistor 376120. In some demonstrative aspects, ABDSC 376100 may include and/or may be operably coupled to, controller circuitry 376107, which may be configured to controllably switch ABDSC 376100 between the splitter mode and the combiner mode, e.g., as described below. In some demonstrative aspects, controller circuitry 376107 may be configured to switch transistor (Q4) 376150 to an OFF state, for example at the splitter mode. For example, at the splitter mode, RF load/source 376101, e.g., transformer 376110 may provide an RF signal, e.g., provided from amplification circuitry 376105, to at least some transistors, e.g., transistor 376130. For example, a signal to be provided to one or more, e.g., each, antenna of the plurality of antennas 376200 may be provided from the drain (D) of transistor 376120. In some demonstrative aspects, controller circuitry 376105 may be configured to switch transistor 376120 to the OFF state, for example, at the combiner mode. For example, at the combiner mode, an RF signal from one or more, e.g., each, antenna of the plurality of antennas 376200 may be provided to the gate (G) of transistor 376140. For example, at the combiner mode, transistor 376150, e.g., of each antenna interface of the plurality of antenna interfaces 376115, may provide the antenna signal to RF load/source 376101, e.g., transformer 376110. For example, RF load/source 376101, e.g., transformer 376110, may combine the signals from the transistors 376150 of the plurality of antenna interfaces 376115 to provide the combined signal to amplification circuitry 376105. The following is one example of simulated parameters, which may be achieved, for example, by a 1:4 ABDSC, e.g., a 1:4 ABDSC 376100, at the combiner mode and at the splitter mode in accordance with some demonstrative aspects: CASCODE - Combiner IL @ 65 GHz Sii Isolation 1:1 -4.4@2.3mA -3.2@3mA -6.1 1:2 -4.5@2.3mA -6.1 -39 1:3 -4.6@2.3mA -6 -39 1:4 -4.7@2.3mA -3.6@3mA -6 -38 S11(common)<-10dB CASCODE - Splitter IL @ 65 GHz Sii Isolation 1:1 -5.5@2.3mA -4.7@3mA -6 1:2 -5.6@2.3mA -6 -40 1:3 -5.7@2.3mA -6 -40 1:4 -5.8@2.1mA -5.1@3mA -6.1 -39 S11(common)<-8dB Table T1 The following is one example of measured parameters, which may be achieved, for example, by a 1:6 ABDSC, e.g., a 1:6 ABDSC 376100, at the combiner mode and at the splitter mode in accordance with some demonstrative aspects: 50p:100p Q=12, k=0.7 CASCODE - Combiner IL @ 65 GHz Sii Isolation 1:1 -7.7@2.3mA -6.4@3mA -6.1 -40 1:2 -7.8@2.3mA -6.6@3mA -6.1 -40 1:3 -7.7@2.3mA -6.6@3mA -6.1 -40 1:4 -7.9@2.3mA -6.7@3mA -6.1 -40 1:6 -8@2.3mA -7@3mA -6.1 -40 S11(common)<-6.6dB CASCODE - Splitter IL @ 65 GHz S22 Isolation 1:1 -8.5@2.3mA -7.8@3mA -6 1:2 -8.6@2.3mA -8@3mA -6 -40 1:3 -8.7@2.3mA -8@3mA 6 -40 1:4 -8.8@2.3mA -8@3mA -6 -40 1:6 -9@2.3mA -8.3@3mA -6.1 -40 S11(common)<-6.6dB Table T2 In some demonstrative aspects, amplification circuitry 376105 may include at least one power amplifier (PA), for example, to amplify Tx signals, and/or at least one Low Noise Amplifier (LNA), to amplify Rx signals. In some demonstrative aspects, ABDSC 376100 may be operably coupled to receive the Tx signal from a bidirectional amplifier in amplification circuitry 376130, and/or to provide the combined Rx signal to a bidirectional amplifier in amplification circuitry 376150. For example, amplification circuitry 376105 may be configured to include one or more elements of and/or to perform one or more functionalities of bidirectional amplifier 372205 (FIG. 159), e.g., as described above. In other aspects, amplification circuitry 376150 may include one or more separate amplifiers, for example, a Tx amplifier and an Rx amplifier, e.g., instead of the bidirectional amplifier. In some demonstrative aspects, for example, amplification circuitry 376105 may be configured to amplify the combined Rx signal into an amplified Rx signal, and/or may be configured to generate the Tx signal by amplifying an upconverted Tx signal. In some demonstrative aspects, transceiver 376000 may include a mixer, for example, mixer 372225 (FIG. 159), which may be configured to upconvert an IF Tx signal into the upconverted Tx signal, and/or to downconvert the amplified Rx signal into an IF Rx signal. In some demonstrative aspects, transceiver 376000 may include IF circuitry, e.g., including one or more elements of IF sub-system 372170 (FIG. 159), to provide one or more IF signals to the mixer. For example, the IF circuitry may be configured to generate a first digital signal based on the IF Rx signal, and/or to generate the IF Tx signal based on a second digital signal. Reference is now made to FIG. 164, which schematically illustrates a circuit diagram of a common source topology of an ABDSC 377100, in accordance with some demonstrative aspects. In some demonstrative aspects, for example, ABDSC 377100 may be implemented as part of a transceiver, for example, as part of transceiver 376000 (FIG. 163), e.g., instead of ABDSC 376100 (FIG. 163). The ABDSCs described herein can be incorporated in one or more circuits (e.g., power combining and dividing circuitry 374) within the RF circuitry 325 (FIG. 3D) of mmWave communication circuitry 300 shown in FIG. 3A, although the ABDSCs are not limited to such. In some demonstrative aspects, ABDSC 377100 may be switchable between a combiner mode and a splitter mode, e.g., as described below. In some demonstrative aspects, ABDSC 377100 may include, for example, an RF load/source 377101, a transformer 377110 and a plurality of antenna interfaces 377115, e.g., as described below. In some exemplary aspects, the number of antenna interfaces 377115 may be, for example, analogues to the number of antenna ports and/or antennas. For example, for four antennas and/or antenna ports ABDSC 377100 may include four antenna interfaces 377115. For example, ABDSC 377100 may be referred as 1:4 ABDSC. For six antennas and/or antenna ports, ABDSC 377100 may include six antenna interfaces 377115. For example, ABDSC 377100 may be referred as 1:6 ABDSC. In other aspects, ABDSC 377100 may include any other number of antenna interfaces 377115, and/or ABDSC 377100 may include any other 1:X ABDSC, wherein X>1. In some demonstrative aspects, antenna interface 377115 of the plurality antenna interfaces 377115 may include, for example, a first transistor 377120 having a common source connection. For example, transistor 377120 may be activated at the splitter mode, and may be deactivated at the combiner mode, e.g., as described below. In some demonstrative aspects, antenna interface 377115 may include a second transistor 377130 having a common source connection. For example, transistor 377130 may be activated at the combiner mode, and may be deactivated at the splitter mode, e.g., as described below. In some demonstrative aspects, for example, transistors 377120 and 377130 may include FETs, MOSFET transistors, BJTs or the like. For example, the MOSFETs may include NMOS and/or PMOS transistors. For example, the BJT may include an NPN and/or a PNP transistors. In one example, transistors 377120 and 377130 may include NMOS transistors, PMOS transistors and/or a combination of NMOS and PMOS transistors. Advantageously, the combination of NMOS and PMOS transistors may reduce the number of components in ABDSC 377100 such as, for example, DC block capacitors, reduce parasitics of the transistors under different biasing conditions and may improve the overall performance of ABDSC 377100. In other aspects, transistors 377120 and/or 377130 may include any other types of transistors. In some demonstrative aspects, antenna interface 377115 may include a resistor 377180, which may be operably coupled to the drain (D) of transistor 377120. For example, resistor 377180 may have a 150Ω resistance, and/or any other suitable value, e.g., for biasing the drain (D) of transistor 377120. In some other aspects, antenna interface 377115 may include a load 377180, e.g., resistor 377180. For example, load 377180 may include an active load, e.g., a transistor configured to be in a triode region of the transistor. In some demonstrative aspects, antenna interface 377115 may include a high resistance component, such as, for example a resistor 377185, which may be operably coupled to the gate (G) of transistor 377120. For example, resistor 377185 may have a 2KΩ resistance, and/or any other suitable value, e.g., for biasing the gate (G) of transistor 377120. In some other aspects, resistor 377185 may be replaced by an active load, e.g., a transistor configured to be in its triode region, and/or any other active load. In some demonstrative aspects, antenna interface 377115 may include a resistor 377190, which may be operably coupled to the gate (G) of transistor 377130. For example, resistor 377190 may have a 2KΩ resistance, and/or any other suitable value, e.g., for biasing the gate (G) of transistor (Q1) 377130. In some other aspects, resistor 377190 may be replaced by an active load, e.g., a transistor configured to be in its triode region, and/or any other active load. In some demonstrative aspects, antenna interface 377115 may include a capacitor 377140, which may be operably coupled to the gate (G) of transistor 377120. For example, capacitor 377140 may include a low/moderate Q capacitor, such as, for example, a 100 femto Farad (fF) for the 60 GHz bands with a Q factor of 15, which may be configured, for example, to decouple transformer 377110 from a gate biasing voltage of transistor 377120. In other aspects, any other capacitance values and Q factors may be used. In other aspects, the capacitor may be redundant, when, for example, PMOS and/or NMOS transistors may be used together. In some demonstrative aspects, antenna interface 377115 may include a capacitor 377150, which may be operably coupled to the gate (G) of transistor 377130. For example, capacitor 377150 may include a low/moderate Q capacitor such as, for example, a 100 fF for the 60 GHz bands with a Q factor of 15, which may be configured, for example, to decouple the Drain bias of transistor 377120 from a gate biasing voltage of transistor 377130. In other aspects, any other capacitance values and Q factors may be used. In other aspects, the capacitor may be redundant, when, for example, PMOS and/or NMOS transistors may be used together. In some demonstrative aspects, transistors 377120 and/or 377130 may be configured to operate with double functionality. For example, at a first functionality mode, transistors 377120 and/or 377130 may function as an amplifier, and/or a second functionality mode, transistors 377120 and/or 377130 may function as a switch. For example, transistors 377120 and/or 377130 may be configured to switch a directionality of ABDSC 377100, for example, between a splitter direction and/or a combiner direction, e.g., as described below. In some demonstrative aspects, a DC voltage source 377160 may supply DC voltage to a gate (G) of transistor 377120. For example, DC voltage source 377170 may supply DC voltage, e.g., through resistor 377180, to the drain (D) of transistor 377120. In some demonstrative aspects, ABDSC 377100 may include and/or may be operably coupled to, controller circuitry 376107 (FIG. 163), which may be configured to controllably switch ABDSC 377100 between the splitter mode and the combiner mode, e.g., as described below. In some demonstrative aspects, controller circuitry 376107 (FIG. 163) may be configured to switch transistor 377130 to an Off state, for example, at the splitter mode. For example, at the splitter mode, RF load/source 377101, e.g., transformer 377110, may provide an RF signal, e.g., provided from amplification circuitry 376105, to at least some transistors, e.g., transistor 377120, of antenna interface 377115. For example, a signal to be provided to one or more, e.g., each, antenna of the plurality of antennas, e.g., antenna 376200 (FIG. 163), may be provided from the drain (D) of transistor 377120 of one or more, e.g., each, antenna interface of the plurality of antenna interfaces 377115. In some demonstrative aspects, controller circuitry 376107 (FIG. 163) may be configured to switch transistor 377120 to an Off state, for example, at the combiner mode. For example, at the combiner mode, an RF signal from one or more antennas, e.g., each antenna, of the plurality of antennas e.g., antennas 376200 (FIG. 163), may be provided to the gate (G) of transistor 377130, e.g., of one or more, e.g., each, antenna interface of the plurality of antenna interfaces 377115. For example, at the combiner mode, transistor 377130 of one or more antenna interfaces, e.g., each antenna interface, of the plurality of antenna interfaces 377115, may provide the antenna signal to RF load/source 377101, e.g., transformer 377110. For example, RF load/source 377101, e.g., transformer 377110, may combine the signals from the transistors 377130 of the one or more antenna interfaces 377115, and may provide the combined signal to amplification circuitry 376105 (FIG. 163). The following is one example of simulated parameters, which may be achieved, for example, by a 1:4 ABDSC, e.g., a 1:4 ABDSC 377100, at the combiner mode, and at the splitter mode in accordance with some demonstrative aspects: CS - Combiner IL @ 65 GHz Sii Isolation 1:1 -3.1@2.3mA -2.4@3mA -5.9 1:2 -3.5@2.3mA -5.9 -22 1:3 -5.9@2.3mA -6 -24 1:4 -7@2.3mA -6.6@3mA -6 -25 S11(common)<-10dB CS - Splitter IL @ 65 GHz Sii Isolation 1:1 -3.7@2.1mA -2.9@3mA -8.3 1:2 -4.3@2.1mA -8.1 -23 1:3 -4.9@2.1mA -8.4 -23 1:4 -5.5@2.1mA -5@3mA -8.5 -24 S11(common)<-7.5dB Table T3 The following is one example of simulated parameters, which may be achieved, for example, by a 1:6 ABDSC, e.g., a 1:6 ABDSC 377100, at the combiner mode, and at the splitter mode in accordance with some demonstrative aspects: 80p:160p Q=12, k=0.7 CS - Combiner IL @ 65 GHz Sii isolation 1:1 -3.7@3mA 1:2 -4.3@3mA -6 -34 1:3 -6.9@3mA -6 -25 1:4 -7.1@3mA -6 -26 1:6 -8.8@3mA -6 -28 S11(common)<-11dB CS - Splitter IL @ 65 GHz Sii isolation 1:1 -4.5@3mA -8.5 1:2 -5@3mA -8.7 -24 1:3 -5.7@3mA -8.7 -24 1:4 -5.6@3mA -8.6 -24 1:6 -7.1@3mA -8.8 -22 S11(common)<-8.9dB Table T4 Reference is now made to FIG. 165, which schematically illustrates a common gate topology of an ABDSC 378100, in accordance with some demonstrative aspects. In some demonstrative aspects, for example, ABDSC 378100 may be implemented as part of a transceiver, for example, as part of transceiver 376000 (FIG. 163), e.g., instead of ABDSC 376100 (FIG. 163). In some demonstrative aspects, ABDSC 378100 may be switchable between a combiner mode and a splitter mode, e.g., as described below. In some demonstrative aspects, ABDSC 378100 may include an RF load/source 378101, e.g., a transformer 378110, and a plurality of antenna interfaces 378115, e.g., as described below. In some demonstrative aspects, the number of antenna interfaces 378115 may be, for example, analogues to the number of antenna ports and/or antennas. For example, for four antennas and/or antenna ports ABDSC 378100 may include four antenna interfaces 378115. For example, ABDSC 378100 may be referred as a 1:4 ABDSC. For six antennas and/or antenna ports, a ABDSC 378100 may include six antenna interfaces 378115. For example, ABDSC 378100 may be referred as 1:6 ABDSC. In other aspects, ABDSC 378100 may include any other number of antenna interfaces 17115, and/or ABDSC 377100 may include any other 1:X ABDSC, wherein X>1. In some demonstrative aspects, an antenna interface 378115 of the plurality of antenna interfaces 378115 may include, for example, a transistor 378120 having a common gate connection. For example, transistor 378120 may receive, at the combiner mode, a drain voltage (Vd) at a drain of transistor 378120, a source voltage (Vs) at a source of transistor 378120, and a gate voltage (Vg) at a gate of transistor 378120, e.g., as described below. In some demonstrative aspects, transistor 378120 may receive, at the splitter mode, the source voltage (Vs) at the drain, the drain voltage (Vd) at the source, and the gate voltage (Vg) at the gate, e.g., as described below. In some demonstrative aspects, for example, transistor 378120 may include FET, MOSFET transistor, BJT and the like. For example, the MOSFET may include NMOS and/or PMOS transistor. Advantageously, the combination of NMOS and/or PMOS transistors may reduce the number of components in ABDSC 378100, reduce parasitics of the transistors under different biasing conditions and may improve the overall performance of ABDSC 378100. In some demonstrative aspects, an antenna interface 378115, e.g., each antenna interface 378115, of the plurality of antenna interfaces 378115 may include a resistor 378180, which may be operably coupled to transistor 378120. For example, resistor 378180 may have a 150Ω resistance, and/or any other suitable value, e.g., for biasing the drain (D) of transistor Q1 378120. In some other aspects, antenna interface 378115 may include an active load as a substituted for resistor 378120, for example, a transistor configured to be in a triode region. In some demonstrative aspects, at the combiner mode, an RF signal from one or more antennas, e.g., each antenna, of the plurality of antennas, e.g., antenna 376200, may be provided to the drain (D) of transistor 378120. In some demonstrative aspects, a source voltage (Vs) may be provided to the drain (D) of transistor 378120. For example, transistor 378120 may be configured to provide the RF signal to RF load/source 378101, e.g., transformer 378110. RF load/source 378101, e.g., transformer 378110 may combine the signals from one or more antennas, e.g., each antenna, of the plurality of antennas, e.g., antenna 376200 (FIG. 163), and may provide the combined signal to the amplification circuitry, e.g., amplification circuitry 376105 (FIG. 163). Reference is now made to FIG. 166, which schematically illustrates a common gate/common source (CS/CG) topology of an ABDSC 379100, in accordance with some demonstrative aspects. In some demonstrative aspects, for example, ABDSC 379100 may be implemented as part of a transceiver, for example, as part of transceiver 376000 (FIG.163), e.g., instead of ABDSC 376100 (FIG. 163). In some exemplary aspects, the number of antenna interfaces 379115 may be, for example, analogues to the number of antenna ports and/or antennas. For example, for four antennas and/or antenna ports ABDSC 379100 may include four antenna interfaces 379115. For example, ABDSC 379100 may be referred as 1:4 ABDSC. For six antennas and/or antenna ports, ABDSC 379100 may include six antenna interfaces 379115. For example, ABDSC 379100 may be referred as 1:6 ABDSC. In some demonstrative aspect, for example, ABDSC 379100 may include two transformers and/or RF load/sources and six antenna interfaces 19115. In this example, ABDSC 379100 may be referred as a 2:6 ABDSC. In other aspects, ABDSC 379100 may include any other number of antenna interfaces 379115, and/or ABDSC 379100 may include any other 1:X ABDSC, wherein X>1. In some demonstrative aspects, one or more antenna interfaces 379115, e.g., each antenna interface 379115, of the plurality of antenna interfaces 379115 may include a first transistor 379130 having the common gate connection to be activated at the combiner mode, configured to be deactivated at the splitter mode; and a second transistor 379120 having a common source connection, and configured to be activated at the splitter mode, and to be deactivated at the combiner mode, e.g., as described below. In some demonstrative aspect, for example, transistors 379120 and/or 379130 may include FETs, MOSFETs transistors, BJTs and the like. The MOSFETs may include NMOS and/or PMOS transistors. For example, the BJT may include NPN and/or PNP transistors. In one example, transistors 379120 and/or 379130 may include NMOS transistors, PMOS transistors and/or a combination of NMOS and PMOS transistors. Advantageously, the combination of NMOS and PMOS transistors may reduce the number of components in ABDSC 379100, reduce parasitics of the transistors under different biasing conditions and may improve the overall performance of antenna interface ABDSC 379100. In other aspects, transistors 379120 and/or 379130 may include any other types of transistors. In some demonstrative aspect, antenna interface 379115 may include a resistor 379180, which may be operably coupled to the drain (D) of transistor 379120. For example, resistor 379180 may have a 150Ω resistance, and/or any other suitable value, e.g., configured to bias the drain (D) of transistor (Q1) 379120. In some other aspects, antenna interface 379115 may include an active load as a substituted for resistor 379180, for example, a transistor configured to be in a triode region. In some demonstrative aspect, antenna interface 379115 may include a resistor 379185, which may be operably coupled to the gate (G) of transistor 379120. For example, resistor 379185 may have a 2KΩ resistance, and/or any other suitable value, e.g., configured to bias the gate (G) of transistor 379120. In some other aspects, antenna interface 379115 may include an active load as a substituted for resistor 379185, for example, a transistor configured to be in a triode region. In some demonstrative aspect, antenna interface 379115 may include a resistor 19190, which may be operably coupled to the gate (G) of transistor 379190. For example, resistor 19190 may include a 2KΩ resistance, and/or any other suitable value, which may be configured to bias the gate (D) of transistor 379130. In some other aspects, antenna interface 379115 may include an active load as a substituted for resistor 377180, for example, a transistor configured to be in a triode region. In some demonstrative aspect, antenna interface 379115 may include a capacitor 379140, which may be operably coupled to the gate (G) of transistor 379120. For example, capacitor 379140 may include a low/moderate Q capacitor of about 100 fF for the 60 GHz bands with a Q factor of 15, which may be configured, for example, to decouple transformer 379110 from a gate biasing voltage of transistor 379120. In some demonstrative aspect, for example, transistor 379120 may be implemented with a common source topology, and/or transistor 379130 may be implemented with a common gate topology. For example, a DC voltage source 379150 may supply DC voltage to a drain (D) of transistor 379130. For example, a DC voltage source 379155 may supply DC voltage to a source (S) of transistor 379120, if required. For example, a DC voltage source 379160 may supply DC voltage, e.g., through resistor 379190, to gate (G) of transistor 379130. For example, a DC voltage source 379165 may supply DC voltage, e.g., through resistor 379185, to gate (G) of transistor 379120. For example, a DC voltage source 379170 may supply DC voltage to the drain (D) of transistor (Q1) 379120, e.g., through resistor 379180. In some other aspects, resistors 379190 and 379185 may be substitute by an active load as a resistor 377180 and/or a current mirror. Resistor 379180 may be substitute by a transistor configured to be in a triode region of the transistor. In some demonstrative aspects, ABDSC 379100 may include and/or may be operably coupled to, controller circuitry 376107 (FIG. 163), which may be configured to controllably switch ABDSC 379100 between the splitter mode and the combiner mode, e.g., as described below. In some demonstrative aspects, controller circuitry, e.g., controller circuitry 376107 (FIG. 163), may be configured to switch transistor 379130 to an Off state, for example, at the splitter mode. For example, at the splitter mode, transformer 379110 may provide an RF signal, e.g., provided from amplification circuitry 376105 (FIG.163), to at least some transistors, e.g., to transistor 379120, of the plurality of antenna interfaces 379115. For example, a signal to be provided to one or more, e.g., each, antenna of the plurality of antennas, e.g., antenna 376200 (FIG. 163), may be provided from the drain (D) of transistor 379120 of one or more, e.g., each, antenna interface of the plurality of antenna interfaces 379115. In some demonstrative aspects, controller circuitry 376107 (FIG. 163) may be configured to switch transistor 379120 to an Off state, for example, at the combiner mode. For example, an RF signal from each antenna of the plurality of antennas, e.g., antenna 376200 (FIG. 163), for example, may be provided to the source (S) of transistor 379130 of one or more antenna interfaces, e.g., each, antenna interface, of the plurality of antenna interfaces 379115. For example, transistor 379130 of one or more, e.g., each, antenna interface of the plurality of antenna interfaces 379115 may provide the antenna signal to transformer 379110. For example, transformer 379110 may combine the signals from transistor 379130 of the one or more antenna interfaces 379115, and may provide the combined signal to amplification circuitry 376105 (FIG. 163). The following is one example of measured parameters, which may be achieved, for example, by a 1:4 ABDSC, e.g., a 1:4 ABDSC 379100, at the combiner mode, and at the splitter mode in accordance with some demonstrative aspects: CG/CS - Combiner IL @ 65 GHz Sii Isolation 1:1 -3.7 @ 2.8mA -4.8 @ 1.6mA -18 1:2 -4.6 @ 2.8mA -5.6 @ 1.6mA -18 -20 1:3 -5.1 @ 2.8mA -6 @ 1.6mA -19 -24 1:4 -5.6 @ 2.8mA -6.5 @ 1.6mA -20 -24 S11(common)<-8.3dB CG/CS - Splitter IL @ 65 GHz Sii Isolation 1:1 -2.6 @2.5mA -10 1:2 -3.4 @2.5mA -10 -22 1:3 -4.2 @2.5mA -10 -23 1:4 -5 @2.5mA -10 -23 S11(common)<-7dB Table T5 The following is one example of measured parameters, which may be achieved, for example, by a 1:6 ABDSC, e.g., a 1:6 ABDSC 379100, at the combiner mode, and at the splitter mode in accordance with some demonstrative aspects: 90p:140p Q=12, k=0.7 CG/CS - Combiner IL @ 65 GHz Sii Isolation 1:1 -4.5@2.6mA -17 1:2 -5@2.6mA -17 -23 1:3 -5.6@2.6mA -17 -23 1:4 -6@2.6mA -17 -24 1:6 -7@2.6mA -17 -25 S11(common)<-.8dB CG/CS - Splitter IL @ 65 GHz Sii isolation 1:1 -5.5@1.5mA -7.7 1:2 -6@1.5mA -7.8 -26 1:3 -6.4@1.5mA -7.9 -27 1:4 -6.8@1.5mA -7.9 -27 1:6 -7.7@1.5mA -8 -28 S11(common)<-7.1dB Table T6 Referring back to FIG. 4, in some demonstrative aspects, RF circuitry 425 may be configured according to a radio architecture, which may include at least one digital class E stack PA, which may be configured to amplify RF signals, e.g., as described below. In some demonstrative aspects, in some use cases, scenarios, and/or implementations, for example, to support high data-rates for millimeter wave (mm-Wave) 5G applications and/or any other implementations, there may be a technical need for realizing spectrally efficient polar constellations, e.g., Multi-level Amplitude-Phase Shift Keying (M-APSK), and/or Cartesian constellations e.g., Multi-Level Quadrature Amplitude Modulation (m-QAM), for example, with high speed, high amplitude, and/or phase resolution. In some demonstrative aspects, in order to realize high amplitude resolution, for example, in a mm-wave transmitter front-end, a mm-wave PA in a transmitter may be segmented into a plurality of segments, for example, binary scaled segments, e.g., as described below. In some demonstrative aspects, one or more of the amplifier segments, e.g., even each amplifier segment, may be digitally controlled, for example, to realize a desired amplitude resolution, e.g., as described below. In some demonstrative aspects, a switching power amplifier architecture, for example, Class-E/Class-F PA, or the like, having two transistors stacked in series, e.g., one transistor connected above the other transistor, may be used to mitigate a loss of series modulation control switches. For example, a stacked top transistor may be configured to also operate as a modulation control switch. For example, a gate voltage of the top transistor may be digitally controlled by a control signal, for example, such that a current of the top transistor may starve the bottom transistor to shut down, for example, to force a modulated output amplitude, e.g., a mm-wave modulated output amplitude, to be high or low, for example, according to digital control bits of the control signal. In some demonstrative aspects, an N-bit resolution digital power amplifier may be implemented, for example, by replicating and binary scaling N identical stacked transistor segments, e.g., as described below. In some demonstrative aspects, the N-bit resolution digital power amplifier may be configured, for example, to obviate a need for lossy series switches at the input of each of the amplifier segments. In some demonstrative aspects, the top stacked transistor may play a dual role of a power amplification stage as well as a modulation control switch, e.g., as described below. For example, by incorporating modulation switch parasitics into, for example, an mm-wave PA design network, larger switch sizes, for example, 25 µm to 250 µm, may be used to reduce switch ON resistance loss, for example, even without paying the penalty of large switch parasitic capacitances, for example, 20-200 femtoFarad (fF). In some demonstrative aspects, the N-bit digital PA may be included in radio chain circuitry 435 (FIG. 4), if desired. Reference is now made to FIG. 167, which schematically illustrates a block diagram of an architecture of a transmitter 380100, in accordance with some demonstrative aspects. In some demonstrative aspects, transmitter 380100 may be embedded for example, as part of an integrated circuit (IC). In to some demonstrative aspects, transmitter 380100 may include a millimeter wave transmitter to transmit a signal over a mmWave frequency band, e.g., as described below. In other aspects, transmitter 380100 may include any other type of transmitter to transmit a signal over any other frequency band. In some demonstrative aspects, transmitter 380100 may include an analog transmitter, a wideband transmitter, a digital transmitter, a digitally controlled transmitter, or the like. For example, one or more elements of transmitter 380100may be implemented as part of transmitter 371110 (FIG. 158). In some demonstrative aspects, transmitter 380100 may include a LO 380110, for example, a 60 GHz LO, or any other LO. In some demonstrative aspects, transmitter 380100 may include a baseband 380120 to generate phase data 380125. For example, baseband 380120 may be included as part of a phase data sub-system (not shown) that may generate phase data 380125. Phase data 380125 may include, for example, analog phase data and/or a digital phase data. In some demonstrative aspects, transmitter 380100 may include a phase modulator 380130 configured to generate an input signal 380135, for example, by modulating phase data 380125 according to an LO signal from LO generator 380110. In one example, input signal 380135 may include a 60 GHz RF signal, or any other signal of any other frequency band. In some demonstrative aspects, transmitter 380100 may include an amplitude data signal source 380140, for example, to generate a digital control signal 380145 representing amplitude data. In some demonstrative aspects, transmitter 380100 may include an N-bit digital PA 380150, which may be configured to amplify the input signal 380135, for example, based on control signal 380145, e.g., as described below. In some demonstrative aspects, transmitter 380100 may include or may be operably coupled to at least one antenna 380170, e.g., coupled to digital PA 380150 to transmit at least one signal based on the input signal 380135, e.g., as described below. In to some demonstrative aspects, transmitter 382100 may include one or more phase array antennas 380170, e.g., coupled to digital PA 382150, e.g., as described below. In some demonstrative aspects, N-bit digital PA 380150 may include a plurality of stacked gate controlled amplifiers 380155 operably coupled to a combiner 380159, e.g., as described below. In some demonstrative aspects, N-bit digital PA 380150 may include a combiner 380159, e.g., as described below. In some demonstrative aspects, digital PA 380150 may be configured to controllably amplify and modulate input signal 380135, for example, based on digital control signal 380145, e.g., as described below. In some demonstrative aspects, the plurality of stacked gate controlled amplifiers 380155 may be controllable by digital control signal 380145, for example, to provide a plurality of amplified modulated signals 380157, e.g., as described below. In some demonstrative aspects, a stacked gate control amplifier 380151 of the plurality of stacked gate controlled amplifiers 380155 may include a first input 380152 to receive input signal 380135, a second input 20153 to receive digital control signal 380145, and an output 380154 to provide an amplified modulated signal 380157, e.g., as described below. In some demonstrative aspects, combiner 380159 may be configured to combine the plurality of amplified modulated signals 380157 into a combiner output signal 380180, for example, having an output power level and a modulation, which are based on the digital control signal 380145, e.g., as described below. In some demonstrative aspects, stacked gate controlled amplifier 380152 may include a first transistor and a second transistor, e.g., as described below. In some demonstrative aspects, the first transistor of stacked gate controlled amplifier 380152 may be configured to provide the amplified modulated signal 380157, for example, by amplifying and modulating input signal 380135 at a gate of the second transistor of stacked gate controlled amplifier 380152, for example, based on the digital control signal 380145, e.g., as described below. In some demonstrative aspects, the first transistor of stacked gate controlled amplifier 380152 may be configured to digitally control an amplification of the second transistor of stacked gate controlled amplifier 380152, for example, based on the digital control signal 380145, e.g., as described below. In some demonstrative aspects, the second transistor of stacked gate controlled amplifier 380152 may be configured, for example, to switch stacked gate controlled amplifier 380152 between an On state and an Off state, for example, based on a bit value of the digital control signal 380145, e.g., as described below. In some demonstrative aspects, the first transistor of stacked gate controlled amplifier 380152 may include, for example, a first FET, and/or the second transistor of stacked gate controlled amplifier 380152 may include, for example, a second FET. In other aspects, the first and/or second transistors may include any other type of transistors. In some demonstrative aspects, the first transistor of stacked gate controlled amplifier 380152 may be configured to amplify the input signal 380135, for example, by a factor of two, for example, based on a bit of digital control signal 380145, e.g., as described below. In some demonstrative aspects, digital PA 380150 may be configured to modulate input signal 380135 based on digital control signal 20145, for example, according to a modulation scheme, for example, the modulation scheme described above with reference to FIGS. 12A, 12B, 12C, 13A and/or 13B, and/or any other modulation scheme. In some demonstrative aspects, the modulation scheme may include a QAM scheme, e.g., as described above with reference to FIGS. 12A, 12B, 12C, 13A and/or 13B. In some demonstrative aspects, the QAM scheme may include a 64 QAM scheme, e.g., as described below. In other aspects, the QAM scheme may include any other QAM scheme, for example, a 256 QAM scheme, or any other higher or lower degree of QAM. In one example, N-bit digital PA 20150 may include six segments, supporting high modulation speed of 64 QAM, or 128QAM. In other aspects, any other number of segments may be implemented. In some demonstrative aspects, digital control signal 380145 may include 6 bits, e.g., as described below. In other aspects, digital control signal 380145 may include any other number of bits, e.g., less than or greater than 6 bits. In some demonstrative aspects, the plurality of stacked gate controlled amplifiers 380155 may include six stacked gate controlled amplifiers, e.g., as describe below. In other aspects, the plurality of stacked gate controlled amplifiers 380155 may include any other count of stacked gate controlled amplifiers. In to some demonstrative aspects, phase modulator 380130 may provide input signal 380135 to digital PA 380155, for example, based on phase data 380125. Baseband 380120 may provide digital control signal 380145 to digital PA 380150, for example, based on phase data 380125, e.g., as described below. In some demonstrative aspects, baseband 380120 may provide N-bit digital signal 380125 to N-bit digital PA 380150. Baseband 380120 may provide phase data 380125 related digital signal to phase modulator 380130. Phase modulator 380130 may receive LO signal from LO 380110. LO 380110 may provide for example, a 60 GHz modulate signal to phase modulator 380130. Phase modulator 380130 may modulate phase data 380125 with the LO signal and may provide input signal 380135 to N-bit digital PA 380150. In some demonstrative aspects, the first inputs 380152 of the plurality of stacked gate controlled amplifiers 380155 may be connected to phase modulator 380130, second inputs 380153 of the plurality of stacked gate controlled amplifiers 380155 may be connected to amplitude data signal source 380140, and/or outputs 380154 of plurality of stacked gate controlled amplifiers 380155 may be connected to combiner 380159. Combiner 380159 may provide output signal 380180, for example, including a modulated RF signal, to one or more antennas 380170. In some example aspects, digital control signal 380135, e.g., the N-bit digital signal at the second inputs 380153 of the plurality of stacked gate controlled amplifiers 380155 may control an output power level and/or a modulation of output signal 380180 of combiner 380159, e.g., as described below. Reference is made to FIGS. 168Aand 168B, which schematically illustrate an electronic circuit of a stacked-gate control amplifier 381100, in accordance with some demonstrative aspects. For example, stacked-gate control amplifier 380150 (FIG. 167) may include one or more elements of stacked-gate control amplifier 381100. In some demonstrative aspects, stacked gate control amplifier 381100 may include a transistor (M1) 381110 to receive an input signal 381170. In one example, input signal may have an amplitude of about 1 volt, e.g., at a frequency of about 60 GHz. In other aspects, any other amplitude and/or frequency may be implemented. In some demonstrative aspects, stacked gate control amplifier 381100 may include a transistor (M2) 381120 to receive a digital control signal 381180. For example, digital control signal may sway between 1 Volt and 0 volt, or between any other range of voltages. In some demonstrative aspects, stacked gate control amplifier 381100 may include a capacitor 381130. For example, capacitor 381130 at the gate of transistor 381120 may introduce an optimum swing in order that amplify signals at transistors (M1) 381110 and (M2) 381120 in-phase. In some demonstrative aspects, stacked gate control amplifier 381100 may include a capacitor 381140 and/or a capacitor 381150, for example, configured as a capacitor divider network. In some demonstrative aspects, stacked gate control amplifier 381100 may include an inductor 381160, which may be configured by the control signal to clamp a current drawn from a supply voltage VDD, to shut transistor (M1) 381110, and/or to make an output amplitude at output 381190 low, e.g., 0 volts. In some demonstrative aspects, stacked gate controlled amplifier 381100 may include a transistor 381120 to provide an amplified modulated signal by amplifying and modulating input signal 381170 at a gate of transistor 381170, for example, based on digital control signal 381180, and/or a transistor 381120 to digitally control the amplification of transistor 381170, for example, based on the digital control signal 381180, as shown in FIG. 168B. In some demonstrative aspects, for example, as shown in FIG. 168A, transistor 381180 may be configured to switch stacked gate controlled amplifier 381100 between an On state and an Off state, for example, based on a bit value of the digital control signal 381170. For example, transistor 381180 may be configured to switch stacked gate controlled amplifier 381100 to the On state, for example, when a bit at the gate of transistor 381120 has a “high” value, and to switch stacked gate controlled amplifier 381100 to the Off state, for example, when the bit at the gate of transistor 381120 is “low”. In some demonstrative aspects, transistor (M1) 381110 and a transistor (M2) 381120 may include, for example, FETs, which may be connected to each other according to a cascode connection. In some demonstrative aspects, when a gate voltage of transistor (M2) 381120 may be at a digital high, e.g., 1 Volt, the 2-series stacked transistors, e.g., transistor (M1) 381110 and transistor (M2) 381120, may operate as a switching PA. For example, a capacitor divider network, e.g., formed by capacitors 381140 and 381150, may be configured to introduce an optimum swing in order that amplify signals at transistors (M1) 381110 and (M2) 381120 in-phase. In one example, a logic “one” bit level of digital control signal 381180 may cause an amplification by two of input signal 381170, e.g., by transistor (M2) 38120. A logic zero signal level of digital control signal 381180 may cause a zero-level signal at the output signal 381190. A 1Volt amplitude of input signal 381170 may cause to 2 Volt amplitude at output signal 381190. Referring to FIG. 168B, in some demonstrative aspects, during modulation, the gate (G) voltage of transistor (M2) 381120 may be digitally low, e.g., 0 volts, for example, to in turn stacked gate control amplifier 381100 to the OFF state. This may cause transistor (M2) 381120 to turn OFF, for example, irrespective of the signal swing at the gate (G) of transistor (M1) 381110. As transistor (M2) 381120 may shut down, it may clamp a current drawn from a supply voltage VDD through inductor 381160, which may result in shutting transistor (M1) 381110 and making the output amplitude at output 381190 low, e.g., 0 Volts. In some demonstrative aspects, a baseband processor, e.g., baseband sub-system 380145 (FIG. 167) may generate digital control signal 381180, e.g., in the form of an N-bit digital signal, for example, to control the output power level and/or modulation of the output signal of stacked gate control amplifier 381100. Reference is made to FIG. 169, which schematically illustrates a block diagram of a transmitter 382100 including a stacked-gate modulated digital PA 382110, in accordance with some demonstrative aspects. For example, stacked-gate modulated digital PA 382110 may include one or more elements of N-bit digital PA 380150 (FIG. 167). The power amplifiers described herein can be incorporated in one or more circuits (e.g., radio chain circuitry 372) within the RF circuitry 325 (FIG. 3D) of mmWave communication circuitry 300 shown in FIG. 3A, although the power amplifiers are not limited to such. In some demonstrative aspects, transmitter 382100 may include a processor 382120, which may include a baseband processor configured to provide a digital control signal 382125. For example, baseband processor 382120 may perform one or more operations and/or functionalities of amplitude data signal source 380140 (FIG. 167). In some demonstrative aspects, transmitter 382100 may include a modulator 382130. For example, modulator 382130 may perform one or more operations and/or functionalities of phase modulator 380130 (FIG. 167). In some demonstrative aspects, stacked-gate modulated digital PA 382110 may include a plurality of stacked-gate controlled amplifiers 382150 to generate an output signal 382145. In some demonstrative aspects, transmitter 382100 may include an antenna port 382140 to provide output signal 382145 to at least one antenna, e.g., a phased-array antenna or any other type of antenna. In some demonstrative aspects, processor 382120 may provide, for example, an N-bit digital signal to gates of transistors 382152 of the plurality of stacked-gate controlled amplifiers 382150, e.g., as described above. In some demonstrative aspects, for example, a bit ofthe N-bit digital signal 382125 may be provided to a gate of a transistor of a respective stacked-gate controlled amplifier of the plurality of stacked-gate controlled amplifiers 382150. In one example, the N-bit digital signal 382125 may include 6 bits. According to this example, a first bit, e.g., Bit 0, of the N-bit digital signal may be provided to a first stacked-gate controlled amplifier of the plurality of stacked-gate controlled amplifiers 382150; a second bit, e.g., Bit 1, of the N-bit digital signal may be provided to a second stacked-gate controlled amplifier of plurality of stacked-gate controlled amplifiers 382150; a third bit, e.g., Bit 2, of the N-bit digital signal may be provided to a third stacked-gate controlled amplifier of plurality of stacked-gate controlled amplifiers 382150; a fourth bit, e.g., Bit 3 of the N-bit digital signal may be provided to a fourth stacked-gate controlled amplifier of plurality of stacked-gate controlled amplifiers 382150; a fifth bit, e.g., Bit 4, of the N-bit digital signal may be provided to a fifth stacked-gate controlled amplifier of plurality of stacked-gate controlled amplifiers 382150; and/or a sixth bit, e.g., Bit 5, of the N-bit digital signal may be provided to a sixth stacked-gate controlled amplifier of plurality of stacked-gate controlled amplifiers 382150. In some demonstrative aspects, modulator 382130 may provide an RF modulated signal to transistors 382154 of the plurality of stacked-gate controlled amplifiers 382150. The plurality of stacked-gate controlled amplifiers 382150 may amplify the RF modulated signal according to a bit sequence of the N-bit digital signal. Stacked-gate modulated digital PA 382110 may output a Tx RF signal from plurality of stacked-gate control amplifiers 382150, for example, output signal 382145 e.g., the Tx RF signal, to antenna port 382140. Reference is made to FIGS. 170Aand 170B, which schematically illustrate a dynamic realization of a multi-level high speed eye diagram 383100, in accordance with some demonstrative aspects. In some demonstrative aspects, for example, modulator 382130 may modulate an IF signal according to a QAM scheme, for example, 16 QAM, 32 QAM, 64 QAM, and the like. For example, combined output signal 382145 may be shaped by the N-bit digital signal to match desired constellations points of the QAM modulation schemeas shown in FIG. 383, e.g., for 16 QAM, and in FIG. 383, e.g., for 64 QAM. Reference is made to FIGS. 171Aand 171B, which depict a performance improvement graph (FIG. 171A) and a power reduction graph (FIG. 171B) corresponding to an input series switch amplifier, in accordance with some demonstrative aspects. In some demonstrative aspects, as shown in FIG. 171Aand FIG. 171B, a stacked gate-controlled amplifier, e.g., stacked gate-controlled amplifier 382150 (FIG. 169), may achieve a 25% improvement in power reduction, and at least a 150% increase of a power-added efficiency (PAE), e.g., compared to a modulation control switch amplifier. Reference is made to FIGS. 172Aand 172B, which depict an amplitude resolution graph (FIG. 172A) and a power efficiency graph (FIG. 172B), corresponding to an N bit digital PA, e.g., digital PA 382150 (FIG. 169), in accordance with some demonstrative aspects. In one example, 6-bit amplitude resolution is close to linearity based on the bit setting (FIG. 172A). In one example, 50% of peak efficiency under 6 dB power back off may be achieved by the stacked gate digital amplifier, e.g., as shown in FIG. 172B. Reference is made to FIG. 173, which depicts a graph of a drain efficiency versus power saturation of a stacked gate-controlled amplifier and a driver amplifier before it, in accordance with some demonstrative aspects. In some demonstrative aspects, for example, the N bit digital PA with the driver amplifier before the stacked gate-controlled amplifier may have a reduced efficiency at 6-dB backoff (e.g., 39%) in comparison to FIG. 385 where the efficiency may be, for example, 50%. In one example, the driver amplifier power may remain substantially the same, for example, even when segments of the digital PA are switched off, thus allowing the whole system to maintain 50% of its peak efficiency at 6-dB backoff. In some demonstrative aspects, a plurality of driver amplifiers may be added before the stacked gate-controlled amplifier in order to receive, for example, 50% efficiency at the output stage of the stacked gate-controlled amplifier. In some demonstrative aspects, advantageously, the stacked gate-controlled amplifier architecture, e.g., stacked gate-controlled amplifier 381100 (FIG. 381) or stacked gate-controlled amplifier 380151 (FIG. 167), may provide a power gain of, for example, from -2dBm to 8dBm, of a PA chain, and/or a transmitter efficiency of, for example, up to 39% at a mm-waves bandwidth e.g., a 60 GHz bandwidth. Referring back to FIG. 4, in some demonstrative aspects, RF circuitry 425 may be configured according to a radio architecture, which may include at least one series Doherty combiner with sub-quarter wavelength balun, which may be configured to combine a plurality of RF signals into an RF signal, and to transmit the RF signal via one or more antennas, e.g., as described below. In some demonstrative aspects, the stacked gate-controlled amplifier, e.g., stacked gate-controlled amplifier 381100 (FIG. 381) and/or stacked gate-controlled amplifier 380151 (FIG. 167), may reuse the stacked top transistor, e.g., transistor 381120 (FIG. 381), for example, a stacked mm-wave switching amplifier, in design as a modulation control switch, thus improving the drain efficiency for example, up to 39% or more at power saturation 2.5dBm to 8dBm, of the N-bit digital PA. In some demonstrative aspects, in some use cases and/or scenarios it may be advantageous to implement radio architectures, which may share one or more circuits for transmit and receive paths, e.g., as described below. The receive and/or transmit paths may include, for example, one or more amplifiers, one or more splitters, one or more combiners, one or more mixers, and/or one or more other additional or alternative components, if desired. In some demonstrative aspects, a radio architecture may include at least one Doherty power amplifier, e.g., as described below. In some demonstrative aspects, implementing the Doherty power amplifier in the radio architecture may provide one or more benefits and/or solve one or more technical problems, for example, at least by increasing the efficiency of the power amplifier while occupying less die area. For example, the efficiency of the output power may increase by 9dB, or any other level. In some demonstrative aspects, the Doherty power amplifier may be configured to provide a high efficiency amplification of a RF signal, e.g., as described below. For example, the ability to provide a high efficiency amplification of the RF signal may allow, for example, at least a technical benefit of reduced power consumption. In some demonstrative aspects, the Doherty power amplifier may be configured to employ a sub-quarter-wavelength balun concept, for example, to provide efficient power combining, for example, even in a compact die-area, e.g., as described below. In some demonstrative aspects, the radio architecture may include, for example, at least one Doherty power amplifier circuit operably coupled to at least one mixer, e.g., as described below. In some demonstrative aspects, the Doherty power amplifier may be included as part of, and/or may perform one or more operations and/or functionalities of, radio chain circuitry, e.g., as part of sub-system 435 (FIG. 4), and/or any other sub-system and/or element, if desired. In some aspects, Doherty amplifiers and/or Doherty combiners described herein can be incorporated in one or more circuits (e.g., radio chain circuitry 372) within the RF circuitry 325 (FIG. 3D) of mmWave communication circuitry 300 shown in FIG. 3A, although the amplifiers and combiners are not limited to such. Reference is made to FIG. 174, which schematically illustrates a block diagram of a transmitter 27000, in accordance with some demonstrative aspects. For example, one or more elements and/or components of transmitter 387100 may be implemented as part of a transceiver, e.g., as described above with reference to FIGS. 1, 1A, and/or 371. In some demonstrative aspects, transmitter 387000 may be configured to transmit a Tx signal, e.g., as describe below. For example, transmitter 387000 may include an I/Q transmitter, e.g., as described below. In some demonstrative aspects, transmitter 387000 may include and/or may be coupled to at least one antenna 387180. For example, the at least one antenna 387180 may include a phased-array antenna, a dipole antenna, an array of antennas, or the like, e.g., as described below. In some demonstrative aspects, transmitter 387000 may include a Doherty power amplifier 387110, e.g., as described below. In some demonstrative aspects, Doherty power amplifier 387110 may include, for example, a two-stage Doherty power amplifier of a shunt-connected-load type, a two-stage Doherty power amplifier of a series-connected-load type, or any other type of a Doherty power amplifier, e.g., as described below. In some demonstrative aspects, Doherty power amplifier 387110 may include a two-stage Doherty power amplifier, which may include, at least one first stage amplifier 387113, and at least one second stage amplifier 387200, e.g., as described below. In some demonstrative aspects, for example, first stage amplifier 387113 may include a driver amplifier, which may be configured to provide a driver RF signal to the second stage of Doherty power amplifier 387110, e.g., as described below. In some demonstrative aspects, for example, second stage amplifier 387200 may include at least one main amplifier 387210 (also referred to as “carrier amplifier (CA)”), and at least one controllable peaking amplifier (PA) 387220, e.g., as described below. For example, main amplifier 387210 and controllable PA 387220 may be configured to amplify the driver RF signal, e.g., as described below. In some demonstrative aspects, Doherty power amplifier 387110 may include a Sub-Quarter-Wavelength (SQWL) balun 387230, e.g., including the first and second stages, e.g., as described below. For example, SQWL balun 387230 may be configured to combine signals of the first stage to the second stage, for example, to be used as a series load at outputs of main amplifier 387210 and controllable PA, at the second stage, e.g., as described below. In some demonstrative aspects, for example, Doherty power amplifier 387110 may be configured to operate at a shunt-connected-load configuration. For example, at the shunt-connected-load configuration, an amplifier load, denoted ZLP, may be applied to amplifier 387210 and/or controllable PA 387220. In some demonstrative aspects, for example, Doherty power amplifier 387110 may be configured to operate at a series-connected-load configuration. For example, at the series-connected-load configuration, an amplifier load, denoted ZLS, may be applied to amplifier 387210 and/or controllable PA 387220. In some demonstrative aspects, the following relation may be retained, e.g., for the shunt-connected-load type configuration: (6) wherein ZCL denotes the CA load, ZLP denotes the amplifier load, ZPL denotes the PA load, and ZT denotes the total load. In some demonstrative aspects, the CA load ZCL may be expressed, for example, as a series-connected-load type configuration, e.g., as follows: (7) In some demonstrative aspects, the following equation may be retained, e.g., for both the series-connected-load type configuration and the shunt-connected-load type configuration: (8) For example, in a case of: (9) wherein Z0 denotes a load impedance. In some demonstrative aspects, for example, the load impedance Zo may include, may represent, and/or may be based on, an antenna impedance, for example, an impedance of 50 Ohm. In other aspects, the load impedance Zo may include, may represent, and/or may be based on, any other additional or alternative impedance. In some demonstrative aspects, ZPL may be infinite, for example, when controllable PA 387220 is in an off-state, for example, at low RF input levels corresponding to output power levels of, e.g., 6dB below Power saturation (Psat), e.g., 6dB back-off. For example, in such a case, the carrier (Main) amplifier load, e.g., ZCL, may become 2Z0, e.g., considering a quarter-wave impedance transformer. In some demonstrative aspects, controllable PA 387220 may become active and the value of ZPL may decrease, for example, at high RF input levels corresponding to maximum output power (Psat). For example, at the power level at which ZPL is equal to Z0, ZCL may become Z0. Therefore, the carrier (Main) amplifier load, e.g., ZCL, may modulate, for example, between Z0 and 2Z0, for example, depending on the status of the controllable PA 387220, e.g., depending on whether the controllable PA 387220 is off and/or how long the controllable PA 387220 may be turned on. In some other demonstrative aspects, the status of the controllable PA 387220 may be controlled, for example, by the amount of input power levels. In some demonstrative aspects, SQWL balun 387230 may be configured to operate as a series connection load to controllable PA 387220 and main amplifier 387210, e.g., as described below. In some demonstrative aspects, two-stage Doherty amplifier 387110 may include a series load which may be implemented, for example, by SQWL balun 387230, e.g., as described below. In other aspects, two-stage Doherty amplifier 387110 may include any other additional or alternative load, which may be implemented by any other additional or alternative other baluns. In some demonstrative aspects, second stage amplifier 387200 may be controlled by a digital signal 387115, e.g., as described below. In some demonstrative aspects, transmitter 387000 may include a LO 387120 to generate a LO signal 387125, e.g., as described below. For example, LO signal 387125 may be a 60 GHz signal. In other aspects, the LO signal 387125 may include any other frequency. For example, LO 387120 may include a crystal oscillator, a variable frequency oscillator, a frequency synthesizer, or the like. In some demonstrative aspects, transmitter 387000 may include an In-phase (I) mixer 387130, which may be configured to generate an I signal 387135 based on LO signal 387125, and a Quadrature-phase (Q) mixer 387140, which may be configured to generate a Q signal 387125 based on LO signal 387125, e.g., as described below. In some demonstrative aspects, transmitter 387000 may include combiner circuitry 387150, which may be configured to combine I signal 387135 with Q signal 387125, for example, to provide driver amplified input signal 387155, e.g., as described below. In some demonstrative aspects, I mixer circuitry 387130 may be configured to generate the I signal 387135, for example, by mixing LO signal 387125 with an RF signal, e.g., an I RF signal 387132, which may be received, for example, from a phase modulator. In other aspects, I signal 387135 may be generated and/or provided to Doherty amplifier 387110 by any other circuitry and/or based on any other signal. In some demonstrative aspects, Q mixer circuitry 387140 may be configured to generate Q signal 387145, for example, by mixing the LO signal 387125 with an RF signal, e.g., a Q RF signal 387142, which may be, for example, received from the phase modulator. In other aspects, the Q signal may be generated and/or provided to Doherty amplifier 387110 by any other circuitry and/or based on any other signal. In some demonstrative aspects, combiner circuitry 387150 may be configured to combine I signal 387135 and Q signal 387145 into the driver amplified input signal 387155 For example, combiner 387150 may include a Wilkinson combiner, a 2 to 1 combiner, a 4 to 2 combiner, or the like. In other aspects, any other type of combiner may be used. In some demonstrative aspects, the one or more antennas 381780 may be operably coupled to two-stage Doherty amplifier 387110. In some demonstrative aspects, the at least one first stage amplifier 387113 may be configured to amplify the driver amplified input signal 387155, and may provide a driver RF signal 387157 at the first stage, e.g., as described below. In some demonstrative aspects, the at least one main amplifier of the second stage, e.g., CA 387210, may be configured to amplify driver RF signal 387157, and to provide a main amplifier signal 387215 at the second stage, e.g., as described below. In some demonstrative aspects, the at least one controllable PA 387220 may be configured to be turned to an On state, for example, based on a level of driver RF signal 387157. For example, at the On state, two-stage Doherty amplifier 387110 may amplify driver RF signal 387157, for example, to provide a peaking amplifier signal 387225, e.g., as described below. In some demonstrative aspects, SQWL balun 387230 may be configured to combine the main amplifier signal 387125 with peaking amplifier signal 387225, e.g., as described below. In some demonstrative aspects, SQWL balun 387230 may include, for example, a first transmission line 387232 to match an impedance between at least one output of the at least one driver amplifier, e.g., first stage amplifier 387113, at least one input of the at least one main amplifier 387210, and at least one input of the at least one controllable PA 387220, e.g., as described below. In some demonstrative aspects, SQWL balun 387230 may include, for example, a second transmission line 387235 to match an impedance between at least one output of the at least one main amplifier 387210 and at least one output of the at least one controllable PA 387220, e.g., as described below. In some demonstrative aspects, SQWL balun 387230 may include, for example, a third transmission line 387237, and a plurality of stubs. For example, third transmission line 387237 may have a first impedance, and a stub, e.g., each stub, of the plurality of stubs may have a second impedance, e.g., as described below. In some demonstrative aspects, a stub (also referred to as a “resonant stub”) may include, for example, a length of an element, for example, a transmission line or waveguide, which may be connected at one end. In some demonstrative aspects, the first impedance may be double the second impedance. For example, the third transmission line 387237 may have an impedance of 50 Ohm and/or a stub of the plurality of stubs may have an impedance of 25 Ohm, e.g., as described below. In other aspects, any other impedances may be used. In some demonstrative aspects, the plurality of stubs may, for example, operably couple at least one input of the at least one driver amplifier, e.g., first stage amplifier 387113, to third transmission line 387237, may operably couple the at least one output of the at least one driver amplifier, e.g., first stage amplifier 387113, to first transmission line 387232, may operably couple the at least one input of at least one main amplifier 387210 to first transmission line 387232, may operably couple at least one input of at least one controllable PA 387220 to first transmission line 387232, may to operably couple at least one output of at least one main amplifier 387210 to second transmission line 387235, and/or may operably couple at least one output of at least one controllable PA 387220 to second transmission line 387235, e.g., as described below. In some demonstrative aspects, a length of the stub may be based on, for example, one eighth of a wavelength of driver RF signal 387257, e.g., as described below. In some demonstrative aspects, second transmission line 387235 and the plurality of stubs may be configured to provide, for example, a serial load at the at least one output of main amplifier 387210, and at the at least one output of controllable PA 387220, e.g., as described below. In some demonstrative aspects, the at least one driver amplifier e.g., first stage amplifier 387113, may include a first matching network, which may include a first input operably coupled to a first stub of the plurality of stubs, and a second matching network having a second input operably coupled to a second stub of the plurality of stubs, e.g., as described below. In some demonstrative aspects, the first and second matching networks may be configured to match impedances of the first and second stubs with an impedance of the third transmission line, 387237 e.g., as described below. In some demonstrative aspects, the at least one driver amplifier e.g., first stage amplifier 387113, may include a first power amplifier, which may include a first input which may be operably coupled to a first output of the first matching network, and a first output which may be operably coupled to a third stub of the plurality of stubs, e.g., as described below. In some demonstrative aspects, the at least one driver amplifier, e.g., first stage amplifier 387113, may include a second power amplifier, which may include a second input, which may be operably coupled to a second output of the second matching network, and a second output which may be operably coupled to a fourth stub of the plurality of stubs, e.g., as described below. In some demonstrative aspects, the third and fourth stubs may be configured to match an impedance between the first and second of the first and second power amplifiers and the first transmission line, e.g., as described below. In some demonstrative aspects, the at least one main amplifier 387210 may include a first matching network and a second matching network, e.g., as described below. For example, the first matching network of main amplifier 387210 may include, for example, a first input operably coupled to a first stub of the plurality of stubs, and the second matching network of main amplifier 387210 may include a second input which may be operably coupled to a second stub of the plurality of stubs. For example, the first matching network and/or the second matching network of main amplifier 387210 may be configured to match impedances of the first and second stubs with an impedance of first transmission line 387232, e.g., as described below. In some demonstrative aspects, the at least one main amplifier 387210 may include a first power amplifier and/or a second power amplifier, e.g., as described below. For example, the first power amplifier of main amplifier 387210 may include a first input, which may be operably coupled to a first output of the first matching network of main amplifier 387210, and a first output, which may be operably coupled to a third stub of the plurality of stubs. For example, the second power amplifier of main amplifier 387210 may include a second input, which may be operably coupled to a second output of the second matching network, and a second output, which may be operably coupled to a fourth stub of the plurality of stubs. For example, the third and fourth stubs may be configured to match an impedance between the first and second outputs of the first and second power amplifiers of main amplifier 387210 and second transmission line 387235, e.g., as described below. In some demonstrative aspects, the at least one controllable PA 387220 may include a first matching network and a second matching network. For example, the first matching network of controllable PA 387220 may include a first input, which may be operably coupled to a first stub of the plurality of stubs, and the second matching network of controllable PA 387220 may include a second input, which may be operably coupled to a second stub of the plurality of stubs. For example, the first matching network of controllable PA 387220 may be configured to match impedances of the first and second stubs with an impedance of first transmission line 387232, e.g., as described below. In some demonstrative aspects, the at least one controllable PA 387220 may include a first power amplifier and a second power amplifier. For example, the first power amplifier of controllable PA 387220 may include a first input, which may be operably coupled to a first output the first matching network of controllable PA 387220, and a first output, which may be operably coupled to a third stub of the plurality of stubs. The first power amplifier of controllable PA 387220 may include a second input which may be operably coupled to a second output of the second matching network of controllable PA 387220, and a second output which may be operably coupled to a fourth stub of the plurality of stubs. In one example, the third and fourth stubs may be configured, for example, to match an impedance between the first and second outputs of the first and second power amplifiers of controllable PA 387220 and second transmission line 387235, e.g., as described below. Reference is made to FIG. 175, which schematically illustrates a block diagram of a two-stage Doherty amplifier, which may employ an SQWL balun 388000, in accordance with some demonstrative aspects. For example, two-stage Doherty amplifier with SQWL balun 388000 may be implemented to perform one or more operations and/or functionalities of two-stage Doherty amplifier 387100 (FIG. 174). In some demonstrative aspects, two-stage Doherty amplifier 388000 may include, for example, a first driver amplifier 388100 and a second driver amplifier 388110. For example, first driver amplifier 388100 and/or second driver amplifier 388110 may be configured to amplify an RF input signal 388350, and may provide a first driver RF signal 388360 and a second driver RF signal 388365 at a first stage. In some demonstrative aspects, two-stage Doherty amplifier 388000 may include, for example, a first main amplifier 388300 and a second main amplifier 3883100, which may be configured to amplify driver RF signal 388360, and to provide a main amplifier signal 388340 at a second stage. In some demonstrative aspects, two-stage Doherty amplifier 388000 may include, for example, a first controllable PA 388200 and a second controllable PA 388210. For example, first controllable PA 388200 and/or second controllable PA 388210 may be configured to be turned to an On state, for example, based on a level of driver RF signal 388360. For example, at the On state, two-stage Doherty amplifier 388000 may amplify driver RF signal 388360 to provide a PA signal 388240. In some demonstrative aspects, two-stage Doherty amplifier 388000 may include, for example, an SQWL balun 388400 which may be configured to combine main amplifier signal 388340 with PA signal 388240. In some demonstrative aspects, SQWL balun 388400 may include, for example, a first transmission line 388500 to match an impedance between the output of first driver amplifier 388100 to the input of first main amplifier 28300, the output of second driver amplifier 388110 to the input of second main amplifier 388310, and/or the input of first controllable PA 388200 to the input of second controllable PA 388210. In some demonstrative aspects, SQWL balun 388400 may include, for example, a second transmission line 388600 configured to match an impedance between an output of first main amplifier 388300 and an output of second main amplifier 388310. Second transmission line 388600 may configured to match an impedance between an output of first controllable PA 388200 and an output of a second controllable PA 388210. In some demonstrative aspects, SQWL balun 388400 may include, for example, a third transmission line 388700 having, for example, an impedance of 50 Ohm, and a plurality of stubs 388800. For example, at least one stub, e.g., each stub 388800, of the plurality of stubs 388800 may have, for example, an impedance of 25 Ohm. In some demonstrative aspects, the plurality of stubs 388800 may operably couple, for example, the input of first driver amplifier 388100 and the input of second driver amplifier 388110 to third transmission line 388700. In some demonstrative aspects, the plurality of stubs 388800 may operably couple, for example, the output of first driver amplifier 388100 and the output of the second driver amplifier 388100 to transmission line 388500. In some demonstrative aspects, the plurality of stubs 388800 may operably couple, for example, the input of first main amplifier 388300 and/or the input of the second main amplifier 388310 to first transmission line 388500. In some demonstrative aspects, the plurality of stubs 388800 may operably couple, for example, the input of first controllable PA 388200 and/or the input of second controllable PA 388210 to first transmission line 388500. In some demonstrative aspects, the plurality of stubs 388800 may operably couple, for example, the output of first main amplifier 388300 and/or the output of second main amplifier 388310 to second transmission line 388600. In some demonstrative aspects, the plurality of stubs 388800 may operably couple, for example, the output of the first controllable PA 388200 and/or the output of the second PA 388210 to second transmission line 388600. In some demonstrative aspects, a length of a stub 388800 may be based, for example, on one eighth of a wavelength of the driver RF signal 388360 and/or the RF driver signal 388365. In some demonstrative aspects, second transmission line 388600 and the plurality of stubs 388800 may be configured to provide, for example, a serial load at the first output of the first main amplifier 388300, at the output of the second main amplifier 388310, at the output first controllable PA 388200, and/or at the output of second controllable PA 388210. In some demonstrative aspects, first driver amplifier 388100 and/or second driver amplifier 388110 may include, for example, a first matching network 388130 and a second matching network 388135. For example, an input of the first matching network 388130 may be coupled to a first stub of the plurality of stubs 388800, and an input of second matching network 388135 may be coupled to a second stub of the plurality of stubs 388800. In some demonstrative aspects, the first and/or second matching networks, e.g., matching networks 388130 and/or 388135, may be configured to match impedances of the first and second stubs with an impedance of third transmission line 388700. In some demonstrative aspects, for example, first driver amplifier 388100 may include a first power amplifier 388120 having an input, which may be operably coupled to a first output of first matching network 388130. First driver amplifier 38100 may include a first output, which may be operably coupled to a stub of the plurality of stubs 388800. In some demonstrative aspects, first driver amplifier 388100 may include a second power amplifier 388125 having an input, which may be operably coupled to a second output of second matching network 388135. For example, first driver amplifier 388100 may include a second output, which may be operably coupled to a stub of the plurality of stubs 388800. In some demonstrative aspects, for example, second driver amplifier 388110 may include a first power amplifier having an input, which may be operably coupled to a first output of a first matching network of second driver amplifier 388110. Second driver amplifier 388110 may include a first output, which may be operably coupled to a stub of the plurality of stubs 388800. In some demonstrative aspects, second driver amplifier 388110 may include a second power amplifier, which may have an input operably coupled to a second output of a second matching network of second driver amplifier 388110. For example, second driver amplifier 388110 may have a second output, which may be operably coupled to a stub of the plurality of stubs 388800. In some demonstrative aspects, one or more of the stubs 388800 may be used as a 2-to-1 combiner to combine the outputs of the first and the second power amplifiers into a driver RF signal 388360 and/or a driver RF signal 388365. In some demonstrative aspects, first main amplifier 388300 may include a first matching network 388320 and a second matching network 388325. For example, first matching network 388320 may include, for example, a first input operably coupled to a stub of the plurality of stubs 388800, and second matching network 388325 may include a second input, which may be operably coupled to another stub of the plurality of stubs 388800. For example, first matching network 388320 and/or second matching network 388325 may be configured to match impedances of the stubs 388800 with an impedance of the first transmission line 388600. In some demonstrative aspects, first main amplifier 388300 may include a first power amplifier 388330 and/or a second power amplifier 388335. For example, first power amplifier 388330 may include a first input, which may be operably coupled to a first output of first matching network 388320, and a first output, which may be operably coupled to a stub of the plurality of stubs 388800. Second power amplifier 388335 may include a second input, which may be operably coupled to a second output of second matching network 388325, and a second output, which may be operably coupled to another stub of the plurality of stubs. For example, the stubs, which are operably coupled to transmission line 388600 and transmission line 388600, may be configured as a 4-to-1 combiner. In some demonstrative aspects, second main amplifier 388310 may include, for example, first and second matching networks, and first and second power amplifiers, which may be configured to operate, for example, as the first and second matching networks, and the first and second power amplifiers of first main amplifier 388300, e.g., as described above. In some demonstrative aspects, first controllable PA 388200 may include a first matching network 388220 and a second matching network 388225. For example, first matching network 388220 may include a first input, which may be operably coupled to a stub of the plurality of stubs 388800, and second matching network 388225 may include a second input, which may be operably coupled to another stub of the plurality of stubs 388800. For example, first matching network 388220 may be configured to match impedances of the stubs with an impedance of first transmission line 388500. In some demonstrative aspects, first controllable PA 388200 may include a first power amplifier 388230 and a second power amplifier 388235. For example, first power amplifier 388230 may include a first input, which may be operably coupled to a first output first matching network 388220, and a first output which may be operably coupled to a stub of the plurality of stubs 388800. Second power amplifier 388235 may include a second input, which may be operably coupled to a second output of second matching network 388225, and a second output which may be operably coupled to another stub of the plurality of stubs 388800. In one example, the stubs 388800 may be configured to match an impedance between the first output of first power amplifier 388230 and the second output of second power amplifier 388235, and the second transmission line 388600. In some demonstrative aspects, RF input signal 388350 may be split 4-ways, and may be fed to first driver amplifier 388130 and second driver amplifier 388110. For example, first driver amplifier 388130 and second driver amplifier 388310 may amplify the RF input signal 388350 and may provide four output RF signals. In one example, each pair of the four RF output signals may be combined at the top and bottom halves of the first stage, for example, by SQWL balun 388400, which may include, for example, first and/or second 2-to-1 power combiners, whose output impedances may be, for example, 50 Ω. The first and second 2-to-1 power combiners may amplify driver RF signal 388360 and/or may amplify driver RF signal 388365. For example, amplify driver RF signal 388360 and/or amplify driver RF signal 388365 may be split between the first main amplifier 388300, the second main amplifier 388310, the first controllable amplifier 388200 and/or the second controllable amplifier 388210 at the top and bottom halves of the second stage. For example, SQWL balun 388400 may include at least two 4-to-1 splitters whose input impedances may be configured to be, for example, 50 Ω, which may be used to split driver RF signal 388360 and/or amplify driver RF signal 388365 between the first main amplifier 388300, the second main amplifier 388310, the first controllable amplifier 388200 and/or the second controllable amplifier 388210. In one example, SQWL balun 388400 may include an 8-way power combiner, which may behave as a two-way parallel combiner between top and bottom halves of SQWL balun 388400. In some demonstrative aspects, SQWL balun 388400 may include a four-way series combiner, which may be configured to combine the output of the first PA 388200 and/or the output of second PA 388210 with the output of first main amplifier 388300 and/or the output of second main amplifier 388310. For example, the four-way series combiner may include second transmission line 388600 and plurality of stubs 388800. Referring back to FIG. 4, in some demonstrative aspects, RF circuitry 425 may be configured according to a radio architecture, which may be configured to operate in a TDD mode. In some demonstrative aspects, RF circuitry 425 may include a Tx chain, which some components and/or functionalities of the Tx chain may be configured to be reused in the Rx chain, e.g., as described below. In some demonstrative aspects, a radio architecture may include at least one I/Q generator, which may be configured, for example, to reuse one or more elements of a Tx chain during a Rx mode of the radio, e.g., as described below. In some demonstrative aspects, the I/Q generator may be configured, for example, to reuse one or more elements of a phase modulating chain of a polar transmitter, for example, during the Rx mode, e.g., as described below. In some demonstrative aspects, implementing the I/Q generator, which reuses elements of the Tx chain at the Rx mode, may provide one or more benefits and/or solve one or more technical problems. For example, reusing one or more elements of the phase modulating chain of the polar transmitter during the Rx mode may allow to reduce die area. For example, an injection locking based oscillator modulator, which may be used at a Tx mode, may be reused as an I or Q LO during the Rx mode, e.g., as described below. In some demonstrative aspects, mmWave transmitters and/or receivers, and/or any other type of transmitters and/or receivers, may operate in a time division duplex (TDD) mode. For example, in the TDD mode, a same frequency band and/or at least partially overlapping frequency bands may be used for both Tx and Rx. For example, the frequency band may be shared between the Tx mode and the Rx mode by assigning alternating time slots to transmit and receive operations, e.g., as described below. In some demonstrative aspects, a transceiver chip, e.g., a half-duplex transceiver, may be configured to operate at a TDD mode. For example, the transceiver chip may include large passive elements, which may require a large chip area. For example, a large chip area with a parasitic coupling between the passive elements may cause unwanted effects. In some demonstrative aspects, one or more of the large passive elements may be reused, for example, when the transceiver may operate at the Tx mode and/or the Rx mode. For example, one or more elements of a phase modulating chain of a polar Tx may be reused during the Rx mode of operation, e.g., as described below. In some demonstrative aspect, a phase modulating chain of a polar Tx may include, for example, one or more elements, which may be used as an injection locking based oscillator modulator, e.g., at the Tx mode, and may be reused, for example, as an I LO and/or a Q LO, e.g., at the Rx mode. For example, a single LO may be used in both Rx mode and Tx mode to perform LO phase shifting, which may be implemented, for example, at least for phased array applications. In some demonstrative aspects, the I/Q generator may be included as part of, and/or may perform one or more operations and/or functionalities of, an upconverter and/or a downconverter, e.g., as part of sub-system 415 (FIG. 4), and/or a radio chain, e.g., as part of sub-system 435 (FIG. 4), and/or any other sub-system and/or element, if desired. Reference is now made to FIG. 176, which schematically illustrates a block diagram of a transceiver 389100, in accordance with some demonstrative aspects. In one example, one or more elements of transceiver 389100 may be implemented as part of, and/or perform one or more functionalities of, transceiver 371100 (FIG. 158). As shown in FIG. 176, in some demonstrative aspects, transceiver 389100 may include a half-duplex transceiver. For example, transceiver 389100 may include a half-duplex transceiver, which may operate in a TDD mode. In some demonstrative aspects, transceiver 389100 may be configured to communicate over a 2.4 GHz band, a 5 GHz band, an mmWave band, a Sub-1 GHz (S1G) band, and/or any other band. In other aspects, transceiver 389100 may include any other type of transceiver to communicate over any other additional or alternative frequency band. In some demonstrative aspects, transceiver 389100 may include at least one antenna port 389180 to couple one or more antennas 389185, e.g., as described below. In some demonstrative aspects, transceiver 389100 may include and/or may be operably coupled through at least one antenna port 389180 to one or more of antennas 389185. In some demonstrative aspects, one or more of antennas 389185 may include an internal antenna, a dipole antenna, a phased-array antenna, a Yagi antenna, an antenna array, or the like. In some demonstrative aspects, transceiver 389100 may include a LNA 389170 which may be configured to generate a Rx signal 389175, for example, based on a signal 389182 received from one or more antenna ports 389180, e.g., as described below. In some demonstrative aspects, transceiver 389100 may include a PA 389160, which may be configured, for example, to amplify a Tx signal 389126 and to provide an amplified signal to one or more antennas 389185 through one or more antenna ports 389180. In some demonstrative aspects, transceiver 389100 may include an I/Q signal generator 389110 to generate one or more I and/or Q signals, e.g., as describe below. In some demonstrative aspects, I/Q generator 389110 may include a LO 389115 to generate a LO signal 389117, e.g., as described below. In some demonstrative aspects, I/Q generator 389110 may include a controllable phase modulation chain 389120, which may be configured to modulate a phase of LO signal 389117, for example, at the Tx mode and/or at the Rx mode, e.g., as described below. In some demonstrative aspects, I/Q generator 389110 may include a controllable phase modulation chain 389130, which may be configured to generate a Q-phase shifted signal 389136 based on LO signal 389117, for example, at the Rx mode, e.g., as described below. In some demonstrative aspects, I/Q generator 389110 may include mixer circuitry 389140, which may be configured to mix Rx signal 389175, e.g., from one or more antenna ports 389180, with one or more LO signals, for example, at the Rx mode, e.g., as described below. In some demonstrative aspects, LO 389115 may be configured to generate LO signal 389117 having a frequency, which may be a third of a carrier frequency, denoted fcarrier, e.g., (fcarrier/3). In one example, LO signal 389117 may have a frequency of 20 GHz, for example, when transceiver 389100 is configured for operating in a 60 GHz frequency band, e.g., as described below. In some demonstrative aspects, LO 389115 may include, for example, a crystal oscillator, a variable frequency oscillator, a frequency synthesizer, or the like. In some demonstrative aspects, controllable phase modulation chain 389120 may include a phase shifter 389122, which may be configured to generate, for example, a phase shifted signal 389123, e.g., as described below. In some demonstrative aspects, controllable phase modulation chain 389120 may include a tripler 389124, which may be configured to generate Tx signal 389126 by tripling phase shifted signal 389123, e.g., at the Tx mode, and to generate a phase shifted I signal 389128 by tripling phase shifted signal 389123, for example, at the Rx mode, e.g., as described below. In some demonstrative aspects, controllable phase modulation chain 389120 may be configured to generate, for example, Tx signal 389126 based on LO signal 389117, e.g., at the Tx mode, and to generate, for example, a phase shifted I signal 389128 based on LO signal 389117, for example, at the Rx mode, e.g., as described below. In some demonstrative aspects, phase shifter 389122 and/or tripler 389124 may be configured to generate Tx signal 389126, e.g., at the Tx mode, and may be reused to generate phased shifted I signal 389128, e.g., at the Rx mode, e.g., as described below. In some demonstrative aspects, phase shifter 389122 may be configured to shift a phase of LO signal 389117, for example, by a first phase shift, e.g., Δφ/3, wherein Δφ denotes a phase shift from a phase of LO signal 389117 wherein Δφ denotes a phase shift of an output of controllable phase modulation chain 29120, e.g., Tx signal 389126 and/or phase shifted I signal 389128, relative to a phase of LO signal 389117. In some demonstrative aspects, phase shifter 389122 may be configured to generate the phase shifted signal 389123, for example, based on LO signal 389117. In some demonstrative aspects, tripler 389124 may be configured to generate Tx signal 389126, e.g., at the Tx mode, for example, by tripling a phase and a frequency of phase modulated signal 389123. In some demonstrative aspects, tripler 389124 may be configured to generate phase shifted I signal 389128, e.g., at the Rx mode, for example, by tripling a phase and a frequency of phase shifted signal 389123. In some demonstrative aspects, I/Q generator 389110 may include a switch 389155, which may be configured to selectively connect controllable phase modulation chain 389120 to PA 389160 or disconnect controllable phase modulation chain 389120 from PA 389160. For example, switch 389155 may be controlled to connect controllable phase modulation chain 389120 to PA 389160, e.g., at the Tx mode, and/or to disconnect controllable phase modulation chain 389120 from PA 389160, e.g., at the Rx mode. For example, at the Tx mode, switch 389155 may apply Tx signal 389126 to PA 389160, and PA 389160 may amplify Tx signal 389126 to provide an amplified Tx signal to the one or more antennas 389185, e.g., to an element of a phase array antenna 389185, through antenna port 389180. In some demonstrative aspects, I/Q generator 389110 may include a switch 389150, which may be configured to selectively connect controllable phase modulation chain 389120 to mixer circuitry 389140 or disconnect controllable phase modulation chain 389120 from mixer circuitry 389140. For example, switch 389150 may be controlled to connect controllable phase modulation chain 389120 to mixer circuitry 389140, e.g., at the Rx mode, and/or to disconnect controllable phase modulation chain 389120 from mixer circuitry 389140, e.g., at the Tx mode. For example, at the Rx mode, switch 389150 may apply phase shifted I signal 389128 to mixer circuitry 389140, and mixer circuitry 389140 may downconvert Rx I signal 389175 into an IF signal, e.g., based on phase shifted I signal 389128. In some demonstrative aspects, for example, switch 389150 and/or switch 389155 may include a FET, a metal–oxide–semiconductor field-effect transistor (MOSFET), and/or any other switch. In some demonstrative aspects, switch 389155 and/or switch 389150 may be controlled, for example, by a controller 389200, for example, based on a mode of operation of transceiver 389100. For example, controller 389200 may include, or may be implemented as part of a baseband controller or any other control circuitry, sub-system and/or logic. For example, at the Tx mode, controller 389200 may control switch 389155 to operably connect between an output of tripler 389124 and an input of PA 380160, and/or the controller 389200 may control switch 389150 to operably disconnect the output of tripler 389124 from mixer circuitry 389140. For example, at the Rx mode, controller 389200 may control switch 389155 to operably disconnect the output of tripler 389124 from the input of PA 380160, and/or controller 389200 may control switch 389150 to operably connect the output of tripler 389124 to mixer circuitry 389140. In other aspects, any other switching configuration may be implemented to switchably connect between controllable phase modulation chain 389120 and PA 389160 and/or mixer 389140. In one example, one switch or more than two switches may be implemented to switchably provide signal 389126 to PA 380160 or to mixer 389140. In some demonstrative aspects, controllable phase modulation chain 389130 may include a phase shifter 389132, which may be configured to generate, for example, a phase shifted signal 389138, e.g., as described below. In some demonstrative aspects, controllable phase modulation chain 389130 may include a tripler 389134, which may be configured to triple phase shifted signal 389138 into a phase shifted Q signal 389136, e.g., as described below. In some demonstrative aspects, controllable phase modulation chain 389130 may be configured to generate, for example, at the Rx mode, phase shifted signal 389138 based on LO signal 389117, e.g., as described below. In some demonstrative aspects, for example, phase shifter 389132 and/or tripler 389134, may be configured to generate a phase shifted Q signal 389136, e.g., at the Rx mode, e.g., as described below. In some demonstrative aspects, phase shifter 389132 may be configured to shift a phase of LO signal 389117, for example, by a second phase shift, e.g., Δφ/3± 30o. In other demonstrative aspects, e.g., aspects which may not include tripler 389134 and/or tripler 389134, phase shifter 389132 may be configured to shift a phase of LO signal 389117, for example, by a second phase shift, e.g., Δφ± 90o. In some demonstrative aspects, phase shifter 389132 may be configured to generate phase shifted signal 389138, for example, based on LO signal 389117. In some demonstrative aspects, tripler 389124 may be configured to generate phase shifted Q signal 389136, e.g., at the Rx mode, for example, by tripling a phase and a frequency of phase shifted signal 389138. In some demonstrative aspects, phase shifter 389132 may be configured to shift the phase of the LO signal 389117, for example, by a second phase shift, e.g., at the Rx mode. For example, the second phase shift may include a 90-degree rotation of the first phase shift, for example, Δφ/3. For example, phase shifted Q signal 389136 may include, for example, the carrier frequency fcarrier with a phase shift of a 90-degree rotation, e.g., Δφ ± 90o, e.g., as described below. In some demonstrative aspects, for example, phase shifted I signal 389128 and/or phase shifted Q signal 389136 may include, for example, the carrier frequency fcarrier with a phase shift, e.g., the phase shift Δφ. In some demonstrative aspects, tripler 389134 may provide phase shifted Q signal 29136 to mixer circuitry 389140, e.g., as described below. In some demonstrative aspects, at the Rx mode, mixer circuitry 389140 may receive Rx signal 389175, for example, from LNA 389170, and may mix Rx signal 389175 with phase shifted I signal 389128, for example, into an I-phase signal 389143, e.g., as described below. In some demonstrative aspects, at the Rx mode, mixer circuitry 389140 may mix Rx signal 389175 with phase shifted Q signal 389136 into a Q-phase signal 389146, e.g., as described below. In some demonstrative aspects, mixer circuitry 389140 may include a mixer 389142 and/or a mixer 389145. For example, at the Rx mode, mixer 389142 may mix the Rx signal 389175 with phase shifted I signal 389128 into I-phase signal 389143, and/or mixer 29145 may mix the Rx signal 389175 with phase shifted Q signal 389136 into the Q-phase signal 389146 In some demonstrative aspects, I-phase signal 389143 and/or Q-phase signal 389146 may include, for example, baseband signals. In some demonstrative aspects, I-phase signal 389143 may be used as I-IF signal and/or Q-phase signal 389146 may be used as Q-IF signal, for example, to be provided to a baseband, e.g., IF and baseband processing circuitry within the transmit circuitry 315 and/or the receive circuitry 320 (FIG. 3A). Referring back to FIG. 4, in some demonstrative aspects, RF circuitry 425, which may be configured according to a radio architecture, which may include at least one outphasing power amplifier, which configured to amplify RF signals. In some demonstrative aspects, the at least one outphasing power amplifier may be implemented, for example, by Chireix sub-quarter wavelength balun, e.g., as described below. In some demonstrative aspects, implementing the outphasing power amplifier in the radio architecture may provide one or more benefits and/or solve one or more technical problems, for example, by increasing the efficiency of the power amplifier while occupying less die area and/or providing high-power levels, and/or providing any other additional or alternative technical benefits and/or advantages. In some demonstrative aspects, the outphasing power amplifier may be configured to provide a high efficiency amplification of a RF signal, e.g., as described below. For example, the ability to efficiently combine outputs of a plurality of power amplifiers may allow, for example, at least a technical benefit of achieving a high power level signal. In some demonstrative aspects, the outphasing power amplifier may be operably coupled to a sub-quarter-wavelength (SQWL) balun. For example, the SQWL balun may be configured to employ a Chireix combiner scheme, e.g., to allow at least efficient power combining and/or a high-power level, e.g., as described below. In some demonstrative aspects, the SQWL balun may be configured to employ a selective inductance bank, which may be digitally controlled and, for example, may consequently allow to increase the bandwidth of the Chireix combiner. In some demonstrative aspects, the outphasing power amplifier may be included as part of, and/or may perform one or more operations and/or functionalities of, radio chain circuitry, e.g., as part of sub-system 435 (FIG. 4), and/or any other sub-system and/or element, if desired. Reference is now made to FIG. 177, which schematically illustrates a block diagram of a transmitter 390000, in accordance with some demonstrative aspects. For example, one or more elements and/or components of transmitter 390000 may be implemented as part of a transceiver 371100, e.g., as described above with reference to FIG. 158. In some demonstrative aspects, transmitter 390000 may include a RF amplifier 390100. For example, RF amplifier 390100 may include a plurality of outphasing amplifiers, e.g., including a first outphasing amplifier 390200 and/or a second outphasing amplifier 390300, e.g., as described below. In some demonstrative aspects, outphasing amplifier 390200 and/or outphasing amplifier 390300 may be configured, for example, as constant envelope amplifiers, e.g., as described below. In some demonstrative aspects, for example, the first constant envelop amplifier, e.g., outphasing amplifier 390110, may be configured to operate with a different phase than the second constant envelop amplifier, e.g., outphasing amplifier 390120, e.g., as described below. In other aspects, outphasing amplifier 390200 and/or outphasing amplifier 390300 may have any other configuration and/or may operate according to any other parameters. In some demonstrative aspects, for example, an amplitude modulated signal Sin(t) = A(t)cos(ωt) may be re-written as a sum of two “constant amplitude” signals S1(t) and S2(t), e.g., wherein: (10) In one example, the angle θ=cos-1(A(t)) may represent an outphasing angle, which may be employed, for example, in a metric which shows the phase shift between first outphasing amplifier 390200 and second outphasing amplifier 390300. For example, if the first outphasing amplifier 390200 and the second outphasing amplifier 390300 have a gain of G, then the combined output may be determined, e.g., as follows: (11) In some demonstrative aspects, a modulated signal may be amplified through two constant envelope amplifiers with different phases, e.g., first outphasing amplifier 390200 and second outphasing amplifier 390300, e.g., as described below. Advantageously, having constant amplitude for any given input amplitude level in the constant envelope amplifiers may provide high efficiency, e.g., even for all the input power levels. In some demonstrative aspects, RF amplifier 390100 may include an SQWL for-way combiner balun 390400, e.g., as described below. In some demonstrative aspects, SQWL four-way combiner balun 390400 may include, for example, a Chireix combiner. In some demonstrative aspects, the SQWL four-way combiner balun 390400 may include, for example, a non-isolating combiner. In other aspects, the SQWL four-way combiner balun 390400 may include any other combiner. In some demonstrative aspects, SQWL four-way combiner balun 390400, may be configured as non-isolating combiner, for example, a Chireix combiner, to provide load pulling and to consequently increase the efficiency, e.g., as describe below. For example, in case of a non-isolating combiner, an impedance of first outphasing amplifier 390200 and second outphasing amplifier 390300 may be determined by Z1 = RL/2 + j*tan(θ)/2 and Z2 = RL/2 - j*tan(θ)/2. In some demonstrative aspects, a Chireix combiner may provide a technique to optimize the efficiency of a non-isolating combiner by adding a capacitance and an inductance at the output of each amplifier, e.g., first outphasing amplifier 390200 and second outphasing amplifier 390300, and resonating the re-active element j*tan(θ)/2 seen by each amplifier. In this example, each amplifier may see a pure real impedance of RL/2, e.g., as described below. In some demonstrative aspects, first outphasing amplifier 390200 may include first outphasing amplifier circuitry 390210, which may be configured to provide a first I signal, for example, based on a first input signal, and/or a first Q signal, for example, based on a second input signal, e.g., as described below. In some demonstrative aspects, second outphasing amplifier circuitry 390220 may be configured to provide a second I signal, for example, based on the first input signal, and/or a second Q signal, for example, based on the second input signal, e.g., as described below. In some demonstrative aspects, second outphasing amplifier 390300 may include third outphasing amplifier circuitry 390310, which may be configured to provide a third I signal, for example, based on a third input signal, and/or a third Q signal, for example, based on a fourth input signal, e.g., as described below. In some demonstrative aspects, second outphasing amplifier 390300 may include fourth outphasing amplifier circuitry 390320, which may be configured to provide a fourth I signal, for example, based on the third input signal, and a fourth Q signal, for example, based on the fourth input signal, e.g., as described below. In some demonstrative aspects, SQWL four-way combiner balun 390400 may include a first inductive stub to couple the first I signal and the second I signal to a first transmission line, a second inductive stub to couple the third I signal and the fourth I signal to the first transmission line, a first capacitive stub to couple the first Q signal and the second Q signal to the first transmission line, and/or a second capacitive stub to couple the third Q signal and the fourth Q signal to a second transmission line, e.g., as described below. In some demonstrative aspects, the first transmission line may be configured to provide a first RF signal, for example, based on a combination of the first I signal, the second I signal, the first Q signal, and/or the second Q signal, e.g., as described below. In some demonstrative aspects, the second transmission line may be configured to provide a second RF signal, for example, based on a combination of the third I signal, the fourth I signal, the third Q signal, and/or the fourth Q signal, e.g., as described below. In some demonstrative aspects, first outphasing amplifier circuitry 390210 may include a first amplifier which may be operably coupled to the first inductive stub, and/or a second amplifier, which may be operably coupled to the first capacitive stub, e.g., as described below. In some demonstrative aspects, the second outphasing amplifier circuitry 390220 may include a first amplifier, which may be operably coupled to the first inductive stub, and/or a second amplifier which may be coupled to the first capacitive stub, e.g., as described below. In some demonstrative aspects, the third outphasing amplifier circuitry 390310 may include a first amplifier, which may be operably coupled to the second inductive stub, and/or a second amplifier which may be operably coupled to the second capacitive stub, e.g., as described below. In some demonstrative aspects, the fourth outphasing amplifier 390320 circuitry may include a first amplifier 390325, which may be operably coupled to the second inductive stub and/or a second amplifier which may be operably coupled to the second capacitive stub, e.g., as described below. In some demonstrative aspects, for example, an outphasing amplifier, e.g., each outphasing amplifier, of the first outphasing amplifier 390215, the second outphasing amplifier 390225, the third outphasing amplifier 390315, and/or the fourth outphasing amplifier 390325, may include an I/Q generator to generate an initial I signal based on a LO I signal, and to generate an initial Q signal based on a LO Q signal, e.g., as describe below. For example, first outphasing amplifier 390215 may include an I/O generator 390127, second outphasing amplifier 390225 may include an I/O generator 390227, third outphasing amplifier 390315 may include an I/O generator 390317, and/or fourth outphasing amplifier 390325 may include an I/O generator 390337, e.g., as described below. In some demonstrative aspects, for example, an outphasing amplifier, e.g., each outphasing amplifier, of the first outphasing amplifier 390215, the second outphasing amplifier 390225, the third outphasing amplifier 390315, and/or the fourth outphasing amplifier 390325, may include phase modulator circuitry to generate a phase-modulated I signal by modulating the initial I signal based on a first input of the outphasing amplifier, and to generate a phase-modulated Q signal by modulating the initial Q signal based on a second input of the outphasing amplifier, e.g., as described below In some demonstrative aspects, for example, an outphasing amplifier, e.g., each outphasing amplifier, of the first outphasing amplifier 390215, the second outphasing amplifier 390225, the third outphasing amplifier 390315, and/or the fourth outphasing amplifier 390325, may include a first amplifier to output an amplified I signal by amplifying the phase-modulated I signal, and a second amplifier to output an amplified Q signal by amplifying the phase-modulated Q signal, e.g., as described below. In some demonstrative aspects, for example, the first inductive stub of SQWL four-way combiner balun 390400) may be configured to apply a predefined impedance, for example, a 25 Ohm impedance or any other impedance, to outputs of the first amplifiers of outphasing amplifiers 390215, 390225, 290315, and/or 390325, e.g., as described below. Some demonstrative aspects, for example, the first inductive stub of SQWL four-way combiner balun 390400 may be configured to apply a predefined impedance, for example, a 25 Ohm impedance or any other impedance, to outputs of the second amplifiers of outphasing amplifiers 390215, 390225, 390315, and/or 390325, e.g., as described below. In some demonstrative aspects, for example, the second inductive stub may be configured to apply, for example, a 25 Ohm impedance or any other impedance, to an output of the first amplifier of the outphasing amplifiers 390215, 390225, 390315, and/or 390325, e.g., as described below. In some demonstrative aspects, for example, the second capacitive stub may apply, for example, a 25 Ohm impedance or any other impedance, to an output of the second amplifier of the outphasing amplifiers 390215, 390225, 390315, and/or 390325, e.g., as described below. In some demonstrative aspects, RF amplifier 390100 may include a LO 390500 to generate the LO I signal and the LO Q signal. In some demonstrative aspects, transmitter 390000 may include or may be operably coupled to one or more antennas 390700, e.g., operably coupled to RF amplifier 390100. For example, the one or more antennas 390700 may include a phased-array antenna, a dipole antenna, an internal antenna, an array of antennas, or the like. In some demonstrative aspects, transmitter 390000 may include a signal processor 390600. For example, signal processor 390600 may be configured to generate the I and Q input signals. For example, the I and Q input signals may be applied to inputs of outphasing amplifiers 390215, 390225, 390315, and/or 390325. Reference is made to FIG. 178, which schematically illustrates a block diagram of a outphasing amplifier 391000, which employs an SQWL balun 391100 as a load, in accordance with some demonstrative aspects. For example, outphasing amplifier 391000 with SQWL balun 391100 may perform one or more operations and/or functionalities of RF amplifier 390100 (FIG. 177). In some demonstrative aspects, outphasing amplifier 391000 may include a first outphasing amplifier 391200, a second outphasing amplifier 391300, a third outphasing amplifier 391400, and/or a fourth outphasing amplifier 391500, e.g., as describe below. For example, outphasing amplifiers 391200, 391300, 391400 and/or 391500 may be configured to perform one or more operations of an RF power amplifier. In some demonstrative aspects, first outphasing amplifier circuitry 391200 may be configured to provide a first I signal 391212 based on a first input signal 391020, e.g., an input I signal, and to provide a first Q signal 391214 based on a second input signal 391010 e.g., an input Q signal. In some demonstrative aspects, second outphasing amplifier circuitry 391300 may be configured to provide a second I signal 391312, for example, based on the first input signal 391020, and to provide a second Q signal 391314, for example, based on the second input signal 391010. In some demonstrative aspects, third outphasing amplifier circuitry 391400 may provide a third I signal 391412, for example, based on a third input signal 391030, and to provide a third Q signal 391414, for example, based on a fourth input signal 391040. In some demonstrative aspects, fourth outphasing amplifier circuitry 391500 may provide a fourth I signal 391512, for example, based on the third input signal 391030, and to provide a fourth Q signal 391514, for example based on the fourth input signal 391040. In some demonstrative aspects, SQWL four-way combiner balun 391100 may include a first inductive stub 391110, which may couple first I signal 391212 and second I signal 391312 to a first transmission line 391120. In some demonstrative aspects, SQWL four-way combiner balun 391100 may include a second inductive stub 391130, which may couple the third I signal 391412 and the fourth I signal 391512 to first transmission line 391120. In some demonstrative aspects, SQWL four-way combiner balun 391100 may include a first capacitive stub 391140, which may couple first Q signal 391214 and second Q signal 391314 to first transmission line 391120. In some demonstrative aspects, SQWL four-way combiner balun 391100 may include a second capacitive stub 391150 to couple third Q signal 391414 and fourth Q signal 391514 to a second transmission line 391160. In some demonstrative aspects, first transmission line 391120 may provide a first RF signal 391050, for example, based on a combination of first I signal 391212, second I signal 391312, first Q signal 391214, and/or second Q signal 391314. In some demonstrative aspects, second transmission line 391160 may provide a second RF signal 391060, for example, based on a combination of third I signal 391412, fourth I signal 391512, third Q signal 391414, and/or fourth Q signal 391514. In some demonstrative aspects, first outphasing amplifier circuitry 391200 may include a first amplifier 391210, which may be operably coupled to first inductive stub 391110, and a second amplifier 391220, which may be operably coupled to first capacitive stub 391140. In some demonstrative aspects, second outphasing amplifier circuitry 391300 may include a first amplifier 391310, which may be operably coupled to first inductive stub 391110, and a second amplifier 391320, which may be operably coupled to first capacitive stub 391140. In some demonstrative aspects, the third outphasing amplifier circuitry 391400 may include a first amplifier 391410, which may be operably coupled to second inductive stub 391130, and a second amplifier 391420 which may be operably coupled to second capacitive stub 391150. In some demonstrative aspects, the fourth outphasing amplifier circuitry 391500 may include a first amplifier 391510, which may be operably coupled to second inductive stub 391130, and a second amplifier 391520, which may be operably coupled to the second capacitive stub 391150. In some demonstrative aspects, first outphasing amplifier 391200 may include a first matching network 391230, which may be configured to match impedance of the first amplifier 391210 to, for example, 50 Ohm; and a second matching network 391240, which may be configured to match impedance of the second amplifier 391220 to, for example, 50 Ohm. In other aspects, any other matching impedance may be used. In some demonstrative aspects, second outphasing amplifier 391300 may include a first matching network 391330, which may be configured to match impedance with the first amplifier 391310 to, for example, 50 Ohm; and a second matching network 391340, which may be configured to match impedance with the second amplifier 391320 to, for example, 50 Ohm. In other aspects, any other matching impedance may be used. In some demonstrative aspects, third outphasing amplifier 391400 may include a first matching network 391430, which may be configured to match impedance with the first amplifier 391410 to, for example, 50 Ohm; and a second matching network 391440, which may be configured to match impedance with the second amplifier 391420 to, for example, 50 Ohm. In other aspects, any other matching impedance may be used. In some demonstrative aspects, fourth outphasing amplifier 391500 may include a first matching network 391530, which may be configured to match impedance with the first amplifier 391510 to, for example, 50 Ohm; and a second matching network 391540 which may be configured to match impedance with the second amplifier 391520 to, for example, 50 Ohm. In other aspects, any other matching impedance may be used. In some demonstrative aspects, for example, an outphasing amplifier, e.g., each outphasing amplifier, of outphasing amplifiers 391200, 391300, 391400 and/or 391500, may include an I/Q generator. For example, outphasing amplifier 391200 may include an I/Q generator 391250, outphasing amplifier 391300 may include I/Q generator 391350, outphasing amplifier 391400 may include I/Q generator 391450.and/or outphasing amplifier 391500 nay include IQ generator 391550. In some demonstrative aspects, I/Q generator 391250 may be configured to generate an initial I signal e.g., initial I signal 391260, based on a LO I signal, e.g., LO I signal 391070, and to generate an initial Q signal, e.g., initial Q signal 391270, based on a LO Q signal e.g., LO Q signal 391080. In some demonstrative aspects, I/Q generator 391250 may be configured to generate an initial I signal e.g., initial I signal 391360, based on a LO I signal, e.g., LO I signal 391071, and to generate an initial Q signal, e.g., initial Q signal 391370, based on a LO Q signal e.g., LO Q signal 391081. In some demonstrative aspects, I/Q generator 391450 may be configured to generate an initial I signal e.g., initial I signal 391460, based on a LO I signal, e.g., LO I signal 391072, and to generate an initial Q signal, e.g., initial Q signal 391470, based on a LO Q signal e.g., LO Q signal 31082. In some demonstrative aspects, I/Q generator 391550 may be configured to generate an initial I signal e.g., initial I signal 391560, based on a LO I signal, e.g., LO I signal 391073, and to generate an initial Q signal, e.g., initial Q signal 391570, based on a LO Q signal e.g., LO Q signal 391083. In some demonstrative aspects, for example, an outphasing amplifier, e.g., each outphasing amplifier, of outphasing amplifiers 391200, 391300, 391400 and/or 391500, may include phase modulator circuitry to generate a phase-modulated I signal by modulating the initial I signal based on a first input of the outphasing amplifier, and/or to generate a phase-modulated Q signal by modulating the initial Q signal based on a second input of the outphasing amplifier, e.g., as described below. In some demonstrative aspects, for example, first outphasing amplifier 391200 may include first amplifier 391210, which may be configured to output I signal 391212 by amplifying a phase-modulated I signal 391282, and/or second amplifier 391220, which may be configured to output Q signal 391214 by amplifying a phase-modulated Q signal 391284. In some demonstrative aspects, for example, second outphasing amplifier 391300 may include first amplifier 391310, which may be configured to output I signal 391312 by amplifying a phase-modulated I signal 391382, and/or second amplifier 391320, which may be configured to output Q signal 391314 by amplifying a phase-modulated Q signal 391384. In some demonstrative aspects, for example, third outphasing amplifier 391400 may include first amplifier 391410, which may be configured to output I signal 391412 by amplifying a phase-modulated I signal 391482, and/or second amplifier 391420, which may be configured to output Q signal 391414 by amplifying a phase-modulated Q signal 391484. In some demonstrative aspects, for example, fourth outphasing amplifier 391500may include first amplifier 391510, which may be configured to output I signal 391512by amplifying a phase-modulated I signal 391582, and/or second amplifier 391520, which may be configured to output Q signal 391514by amplifying a phase-modulated Q signal 391584. In some demonstrative aspects, for example, first outphasing amplifier 391200 may include a phase modulator 391280, which may be configured to generate a phase-modulated I signal 391282 and/or a phase-modulated Q signal 391284, for example, by modulating internal I signal 391260 and/or internal Q signal 391270, e.g., with input I signal 391020 and/or input Q signal 391020. In some demonstrative aspects, for example, second outphasing amplifier 391300 may include a phase modulator 391380, which may be configured to generate a phase-modulated I signal 391382 and/or a phase-modulated Q signal 391384, for example, by modulating internal I signal 391360 and/or internal Q signal 391370, e.g., with input I signal 391020 and/or input Q signal 391020. In some demonstrative aspects, for example, third outphasing amplifier 391400 may include a phase modulator 391480, which may be configured to generate a phase-modulated I signal 391482 and/or a phase-modulated Q signal 391484, for example, by modulating internal I signal 391460 and/or internal Q signal 391470, e.g., with input I signal 391020 and/or input Q signal 391020. In some demonstrative aspects, for example, fourth outphasing amplifier 391500 may include a phase modulator 391580, which may be configured to generate a phase-modulated I signal 391582 and/or a phase-modulated Q signal 391584, for example, by modulating internal I signal 391560 and/or internal Q signal 391570, e.g., with input I signal 391020 and/or input Q signal 391020. In some demonstrative aspects, for example, an inductive stub, e.g., first inductive stub 391110 and/or second inductive stub 391130, may be configured to apply a 25 Ohm impedance to an output, e.g., each output, of the first amplifier of outphasing amplifiers 391200, 391300, 391400 and/or 391500. In some demonstrative aspects, a capacitive stub, e.g., first capacitive stub 391140 and/or second capacitive stub 391150, may be configured to apply a 25 Ohm impedance to an output, e.g., each output, of the second amplifier of outphasing amplifiers 391200, 391300, 391400 and/or 391500. In other aspects, first inductive stub 391110, second inductivestub 391130, first capacitive stub 391140, and/or second capacitive stub 391160 may be configured to provide any other impedance to one or more of the outputs of the first amplifier and/or second amplifier of one or more of outphasing amplifiers 391200, 391300, 391400 and/or 391500. In some demonstrative aspects, outphasing amplifier 391000 may include a LO splitter 391600 and/or a LO splitter 391650. For example, LO splitter 391600 and/or LO splitter 31650 may be configured to receive an LO signal from a LO, e.g., LO 390500 (FIG. 177). For example, LO splitter 391600 may split the LO signal into, for example, LO I signals 391070 and/or 391073, and/or into LO Q signals 391080 and/or 391083. For example, LO splitter 391650 may split the LO signal into, for example, LO I signals 391071 and/or 391072, and/or into LO Q signals 391081 and/or 391082. Referring back to FIG. 4, in some demonstrative aspects, RF circuitry 425 may be configured according to a radio architecture, which may include at least one phase shifter (also referred to as a “phase rotator”), which may be configured to shift and/or rotate a phase of a signal to a desired phase, for example, based on one or more predefined phase values, e.g., as described below. In some demonstrative aspects, the phase shifter may be implemented as a controllable phase shifter, e.g., a voltage controlled phase shifter, which may be configured to provide, for example, a low power and/or a high resolution, e.g., as described below. In some demonstrative aspects, the controllable phase shifter may be included as part of, and/or may perform one or more operations and/or functionalities of, radio chain circuitry, e.g., as part of sub-system 435 (FIG. 4), and/or any other sub-system and/or element, if desired. In some demonstrative aspects, the controllable phase shifter may be configured to shift, for example a phase of an In-phase (I) signal and/or a phase of a Quadrature-phase (Q) signal, e.g., as described below. In some demonstrative aspects, the controllable phase shifter may be calibrated, for example, according to a constellation map, for example, to provide a high level of accuracy and/or high regulation, for example, at a maximum gain of the controllable phase shifter, e.g., as described below. In some demonstrative aspects, the controllable phase shifter may be calibrated to correct an I/ Q gain and/or a phase imbalance, for example, with high precision. In some demonstrative aspects, the controllable phase shifter may include, for example, I phase shifting circuitry, which may be configured to provide a phase shifted I signal, for example, based on the I signal and the Q signal, e.g., as described below. In some demonstrative aspects, the I phase shifting circuitry may be configured to provide a first shifted I signal by shifting a phase of the I signal, for example, according to a first control signal, e.g., as described below. In some demonstrative aspects, the I phase shifting circuitry may be configured to provide a first shifted Q signal by shifting a phase of the Q signal, for example, according to a second control signal, e.g., as described below. In some demonstrative aspects, the I phase shifting circuitry may be configured to provide the phase shifted I signal, for example, by combining the first shifted I signal with the first shifted Q signal, e.g., as described below. In some demonstrative aspects, the controllable phase shifter may include, for example, Q phase shifting circuitry, which may be configured to provide a phase shifted Q signal, for example, based on the Q signal and the I signal, e.g., as described below. In some demonstrative aspects, the Q phase shifting circuitry may be configured to provide a second shifted I signal by shifting the phase of the I signal, for example, according to a third control signal, e.g., as described below. In some demonstrative aspects, the Q phase shifting circuitry may be configured to provide a second shifted Q signal by shifting the phase of the Q signal, for example, according to a fourth control signal, e.g., as described below. In some demonstrative aspects, the Q phase shifting circuitry may be configured to provide, the phase shifted Q signal, for example, by combining the second shifted I signal with the second shifted Q signal, e.g., as described below. In some demonstrative aspects, the I phase shifting circuitry and/or the Q phase shifting circuitry may include, for example, voltage controlled phase shifting circuitry, e.g., as described below. In some demonstrative aspects, the I phase shifting circuitry may include, for example, a first Voltage Digital to Analog Convertor (VDAC), which may be configured to convert the first control signal into an I control voltage, e.g., as described below. In some demonstrative aspects, the I phase shifting circuitry may be configured to shift the phase of the I signal, for example, according to the I control voltage, e.g., as described below. In some demonstrative aspects, the I phase shifting circuitry may include, for example, a second VDAC, which may be configured to convert the second control signal into a Q control voltage, e.g., as described below. In some demonstrative aspects, the I phase shifting circuitry may be configured to shift the phase of the Q signal, for example, according to the Q control voltage, e.g., as describe below. In some demonstrative aspects, the Q phase shifting circuitry may include, for example, a first VDAC to convert the third control signal into an I control voltage, e.g., as described below. In some demonstrative aspects, the Q phase shifting circuitry may be configured to shift, the phase of the I signal, for example, according to the I control voltage, e.g., as described below. In some demonstrative aspects, the Q phase shifting circuitry may include, for example, a second VDAC, which may be configured to convert the fourth control signal into a Q control voltage, e.g., as described below. In some demonstrative aspects, the Q phase shifting circuitry may be configured to shift the phase of the Q signal, for example, according to the Q control voltage, e.g., as described below. In some demonstrative aspects, the controllable phase shifter may be configured to provide, for example, the phased shifted I signal and/or the phase shifted Q signal to one or more Power Amplifiers (PAs) at a Transmit (Tx) path, and/or from one or more Low Noise Amplifiers (LNAs) at a Receive (Rx) path, e.g., as described below. In some demonstrative aspects, implementing the controllable phase shifter, e.g., as described herein, may provide one or more benefits and/or solve one or more technical problems, for example, by providing a highly linear phase shifter with power consumption, e.g., independent of resolution, and/or providing any other additional or alternative technical benefits and/or advantages. In some demonstrative aspects, the controllable phase shifter, may be configured to provide a high resolution, for example, even near low and/or high gain settings, e.g., as described below. Reference is made to FIG. 179, which schematically illustrates a block diagram of a transceiver 392000, in accordance with some demonstrative aspects. For example, one or more elements and/or components of transceiver 392000 may be implemented as part of a transceiver 371100, e.g., as described above with reference to FIG. 158. In some demonstrative aspects, transceiver 392000 may include, for example, a half-duplex transceiver, and/or a full-duplex transceiver, e.g., as described below. In some demonstrative aspects, transceiver 392000 may include a millimeter wave transceiver, which may be configured to operate over a 60 GHz frequency band. In other aspects, transceiver 392000 may include any other type of transceiver configured to operate on any other additional or alternative frequency band. In some demonstrative aspects, transceiver 392000 may be operably coupled to a plurality of Rx antennas 392100, and/or to a plurality of Tx antennas 392150, e.g., as described below. For example, Rx antennas 392100 and/or Tx antennas 392150 may include, for example, one or more antenna elements, one or more phased-array antennas, one or more dipole antennas, one or more internal antennas, and/or any other type of antenna. In some demonstrative aspects, transceiver 392000 may include, for example a local oscillator (LO) 392200, which may be configured, for example, to generate an LO signal 392205, e.g., as described below. In some demonstrative aspects, LO 392200 may include, for example a crystal oscillator, a Phase Lock Loop (PLL), an injection LO (ILO), and/or any other type of LO. In some demonstrative aspects, transceiver 392000 may include, for example, LO distribution network circuitry 392300, which may be configured to distribute phase-shifted LO signals, for example, to one or more transmitters and/or receiver components, circuits and/or sub-systems, e.g., as described below. In some demonstrative aspects, the phase-shifted LO signals may include, for example, a sine signal 392264 and/or a cosine signal 392274, e.g., as described below. In other aspects, any other additional or alternative LO signals may be used. In some demonstrative aspects, transceiver 392000 may include, for example, a receiver 392200, which may be configured to receive, for example, one or more Rx Radio Frequency (RF) signals, for example, from Rx antennas 392100, e.g., as described below. In some demonstrative aspects, receiver 392200 may include, for example, a plurality of LNAs 392210, which may be operably coupled to the plurality of Rx antennas 392100, e.g., respectively. For example, an LNA 392210, which may be operably coupled to an Rx antenna 392100, may be configured to provide an Rx signal 392220, for example, by amplifying an RF signal 392230 from the Rx antenna 392100, e.g., as described below. In some demonstrative aspects, receiver 392200 may include, for example, a plurality of mixers 392250, which may be operably coupled to the plurality of LNAs 392210, e.g., respectively. For example, a mixer 392250 coupled to an LNA 392210 may be configured to generate an I signal 392262 and/or a Q signal 392272, for example, according to the RF signal 392220 from the LNA 392210, e.g., as described below. In some demonstrative aspects, receiver 392200 may include, for example, a plurality of controllable phase shifters 392240, which may be operably coupled to the plurality of mixers 392250, e.g., respectively. For example, a controllable phase shifter 392240, which may be operably coupled to mixer 32250 may be configured to shift a phase of I signal 392262 and/or a phase of Q signal 392272 from the mixer 392250, e.g., as described below. In some demonstrative aspects, mixer 392250 may include, for example, a first mixer 392260, which may be operably coupled to a first input 392265 of the controllable phase-shifter 392240, e.g., as described below. In some demonstrative aspects, first mixer 392260 may be configured to generate I signal 392262 by mixing Rx signal 392220, for example, according to sine signal 392264, e.g., as described below. In some demonstrative aspects, mixer 392250 may include, for example, a second mixer 392270, which may be operably coupled to a second input 392275 of the controllable phase shifter 392240, e.g., as described below. In some demonstrative aspects, second mixer 392270 may be configured to generate Q signal 392272 by mixing Rx signal 39220, for example, according to cosine signal 392274, e.g., as described below. In some demonstrative aspects, the plurality of controllable phase shifters 392240 may be configured to controllably apply a plurality of respective phase shifts to the plurality of Rx antennas 392100, e.g., as described below. For example, phase shifters 392240 may be controlled to apply to the Rx antennas 392100 a respective plurality of phase shifts, which may be configured, for example, to generate and/or steer a beam, for example, according to an Rx beamforming scheme, e.g., as described below. In some demonstrative aspects, controllable phase shifter 392240 may be configured to shift a phase of I signal 392262, for example, according to a first control signal 392410, and to provide a phase shifted I signal 392280, e.g., as described below. In some demonstrative aspects, the controllable phase shifter 392240 may be configured to shift a phase of Q signal 392272, for example, according to a second control signal 392420, and to provide a phase shifted Q signal 392290, e.g., as described below. In some demonstrative aspects, transceiver 392000 may include a Q Rx combiner 392510, which may be operably coupled to the plurality of controllable phase shifters 392240. For example, Q Rx combiner 392510 may be configured to combine a plurality of phase shifted Q signals 392290 from the plurality of controllable phase shifters 392240, for example, into a Q Intermediate Frequency (IF) Rx signal 392295. In some demonstrative aspects, transceiver 392000 may include, for example, an I Rx combiner 392520, which may be operably coupled to the plurality of controllable phase shifters 392240. For example, I Rx combiner 392520 may be configured to combine a plurality of phase shifted I signals 392280 from the plurality of controllable phase shifters 392240, for example, into an I IF Rx signal 392285. In some demonstrative aspects, transceiver 392000 may include, for example, a baseband 392500, which may be operably coupled to I Rx combiner 392520 and Q Rx combiner 392510. For example, baseband 392500 may be configured to process IF signals, e.g., I IF Rx signal 392285 and/or Q IF Rx signal 392295, e.g., as described below. In some demonstrative aspects, transceiver 392000 may include, for example, a transmitter 392300, which may be operably coupled to baseband 392500, for example, to transmit one or more Tx signals via Tx antennas 392150, e.g., as described below. In some demonstrative aspects, baseband 392500 may be configured to generate one or more IF Tx signals, for example, an I IF Tx signal 392580 and/or a Q IF Tx signal 392590, which may be transmitted by transmitter 392300, e.g., as described below. In some demonstrative aspects, transmitter 392300 may be configured to transmit a plurality of Tx RF signals 392320 via the plurality of Tx antennas 392150, e.g., as described below. In some demonstrative aspects, transceiver 392000 may include, for example, an I Tx splitter 392530, which may be operably coupled to baseband 392500. For example, I Tx splitter 392530 may be configured to split I IF Tx signal 392580 into a plurality of Tx I signals 392285, for example, to be transmitted via the plurality of Tx antennas 392150, e.g., respectively. In some demonstrative aspects, transceiver 392000 may include, for example, a Q Tx splitter 392540, which may be operably coupled to baseband 392500. For example, Q Tx splitter 392540 may be configured to split Q IF Tx signal 392590, into a plurality of Tx Q signals 392295, for example, to be transmitted via the plurality of Tx antennas 392150, e.g., respectively. In some demonstrative aspects, transmitter 392300 may include, for example, a plurality of controllable phase shifters 392340, which may be operably coupled to Q Tx splitter 392540 and I Tx splitter 392530. For example, a controllable phase shifter 392340 may be configured to shift, for example, a phase of a Tx I signal 392285 from I Tx splitter 392530, and/or a phase of a Tx Q signal 392295 from Q Tx splitter 392540, e.g., as described below. In some demonstrative aspects, the plurality of controllable phase shifters 392240 may be configured to controllably apply a plurality of respective phase shifts to the plurality of Tx antennas 392150, e.g., as described below. For example, phase shifters 392340 may be controlled to apply to the Tx antennas 392150 a respective plurality of phase shifts, which may be configured, for example, to generate and/or steer a beam, for example, according to a Tx beamforming scheme, e.g., as described below. In some demonstrative aspects, transmitter 392300 may include, for example, a plurality of mixers 392350, which may be operably coupled to the plurality of controllable phase shifters 392340, e.g., respectively. For example, a mixer 392350 coupled to a controllable phase shifter 392340 may be configured to generate an RF signal 392330, for example, according to an I shifted signal 392360 and/or a Q shifted signal 32365 from the controllable phase shifter 392340, e.g., as described below. In some demonstrative aspects, the plurality of mixers 392350 may include, for example, a first mixer 392370, which may be operably coupled to a first output 392341 of controllable phase-shifter 392340, e.g., as described below. In some demonstrative aspects, first mixer 392370 may be configured to generate a first RF signal 392332 by mixing I shifted signal 392360, for example, according to sine signal 392264, e.g., as described below. In some demonstrative aspects, the plurality of mixers 392250 may include, for example, a second mixer 392380, which may be operably coupled to a second output 392342 of controllable phase shifter 392340, e.g., as described below. In some demonstrative aspect, second mixer 392380 may be configured to generate a second RF signal 392334 by mixing Q shifted signal 392365, for example, according to cosine signal 392274, e.g., as described below. In some demonstrative aspects, the first RF signal 392332 and the second RF signal 392334 from the controllable phase shifter 392340 may be combined, for example, into an RF signal 392330 to be transmitted via a respective Tx antenna 392150, e.g., as described below. In some demonstrative aspects, transmitter 392300 may include, for example, a plurality of PAs 392310, which may be operably coupled to the plurality of mixers 392380, e.g., respectively. For example, a PA 392310, which may be operably coupled to a mixer 392350, may be configured to amplify, for example, RF signal 392330 from the mixer 392350, into a Tx RF signal 392320, e.g., as describe below. In some demonstrative aspects, PA 392310 may be configured to provide the Tx RF signal 392320 to a Tx antenna 392150, e.g., as described below. In some demonstrative aspects, controllable phase-shifter 392240 and/or controllable phase-shifter 392340 may include, for example, I phase shifting circuitry 392242, which may be configured to provide phase shifted I signal 392280, for example, based on I signal 392262 and a Q signal 392272, e.g., as described below. In some demonstrative aspects, I phase shifting circuitry 392242 may be configured to provide a first shifted I signal, by shifting a phase of I signal 392262, for example, according to a first control signal, e.g., control signal 392410 e.g., as described below. In some demonstrative aspects, I phase shifting circuitry 392242 may be configured to provide a first shifted Q signal, by shifting a phase of Q signal 392272, for example, according to a second control signal, e.g., control signal 392420, e.g., as described below. In some demonstrative aspects, I phase shifting circuitry 392242 may be configured to provide phase shifted signal 392280, for example, by combining the first shifted I signal with the first shifted Q signal, e.g., as described below. In some demonstrative aspects, controllable phase-shifter 392240 and/or controllable phase-shifter 392340 may include, for example, Q phase shifting circuitry 392244, which may be configured to provide phase shifted Q signal 392290, for example, based on Q signal 392272, and I signal 392362, e.g., as described below. In some demonstrative aspects, Q phase shifting circuitry 392244 may be configured to provide a second shifted I signal by shifting the phase of I signal 392262, for example, according to a third control signal, e.g., a control signal 392430, e.g., as described below. In some demonstrative aspects, Q phase shifting circuitry 392244 may be configured to provide a second shifted Q signal, by shifting the phase of Q signal 392272, for example, according to a fourth control signal, e.g., a control signal 392440, e.g., as described below. In some demonstrative aspects, Q phase shifting circuitry 392244 may be configured to provide phase shifted Q signal 392290, by combining the second shifted I signal with the second shifted Q signal, e.g., as described below. In some demonstrative aspects, I phase shifting circuitry 392242 may include, for example, a first VDAC (not shown in FIG. 179), which may be configured to convert the first control signal into an I control voltage, e.g., as described below. In some demonstrative aspects, I phase shifting circuitry 392242 may be configured to shift the phase of I signal 392262, for example, according to the I control voltage, e.g., as described below. In some demonstrative aspects, I phase shifting circuitry 392242 may include, for example, a second VDAC (not shown in FIG. 179), which may be configured to convert control signal 392420 into a Q control voltage, e.g., as described below. In some demonstrative aspects, I phase shifting circuitry 392242 may be configured to shift the phase of Q signal 392272, for example, according to the Q control voltage, e.g., as described below. In some demonstrative aspects, I phase shifting circuitry 392242 may include, for example, a first plurality of transistors in a cascode gate arrangement (not shown in FIG. 179), which may be configured to generate the first shifted I signal, for example, according to the I control voltage, e.g., as described below. In some demonstrative aspects, I phase shifting circuitry 392242 may include, for example, a second plurality of transistors in a cascode gate arrangement (not shown in FIG. 179), which may be configured to generate the first shifted Q signal, for example, according to the Q control voltage, e.g., as described below. In some demonstrative aspects, Q phase shifting circuitry 392244 may include, for example, a first VDAC (not shown in FIG. 179), which may be configured to convert control signal 392430 into an I control voltage, e.g., as described below. In some demonstrative aspects, Q phase shifting circuitry 392244 may be configured to shift the phase of I signal 392262, for example, according to the I control voltage, e.g., as described below. In some demonstrative aspects, Q phase shifting circuitry 392244 may include, for example, a second VDAC (not shown in FIG. 179), which may be configured to convert control signal 392440 into a Q control voltage, e.g., as described below. In some demonstrative aspects, Q phase shifting circuitry 392244 may be configured to shift the phase of Q signal 392272, for example, according to the Q control voltage, e.g., as described below. In some demonstrative aspects, Q phase shifting circuitry 392244 may include, for example, a first plurality of transistors in a cascode gate arrangement (not shown in FIG. 179), which may be configured to generate the second shifted I signal, for example, according to the I control voltage, e.g., as described below. In some demonstrative aspects, Q phase shifting circuitry 392244 may include, for example, a second plurality of transistors in a cascode gate arrangement (not shown in FIG. 179), which may be configured to generate the second shifted Q signal, for example, according to the Q control voltage, e.g., as described below. In some demonstrative aspects, the first control signal, e.g., control signal 392410, may include, for example, a first digital signal, to apply first data to I phase shifting circuitry 392242, for example, based on a predefined constellation-point map, e.g., as described below. In some demonstrative aspects, the second control signal, e.g., control signal 392420, may include, for example, a second digital signal, to apply second data to I phase shifting circuitry 392242, for example, based on the predefined constellation-point map, e.g., as described below. In some demonstrative aspects, the third control signal, e.g., control signal 392430, may include, for example, a third digital signal, to apply third data to Q phase shifting circuitry 392244, for example, based on, the predefined constellation-point map, e.g., as described below. In some demonstrative aspects, the fourth control signal, e.g., control signal 392440 may include, for example, a fourth digital signal, to apply fourth data to the Q phase shifting circuitry 392244, for example, based on the predefined constellation-point map, e.g., as described below. In some demonstrative aspects, transceiver 392000 may include, for example, a calibration and control sub-system 392400, which may be operably coupled to one or more elements of transceiver 392000, for example, including baseband 392500, controllable phase shifters 392240, and/or controllable phase shifters 392340. For example, calibration and control sub-system 392400 may be configured, for example, to control and/or calibrate controllable phase-shifters 392240 and/or controllable phase-shifters 392340, for example, using one or more control signals, for example, control signal 392410, control signal 392420, control signal 392430, and/or control signal 392440, e.g., as described below. In some demonstrative aspects, calibration and control sub-system 392400 may be configured, for example, to calibrate one or more parameters of controllable phase-shifters 392240 and/or controllable phase-shifters 392340, e.g., as described below. In some demonstrative aspects, calibration and control sub-system 392400 may be configured to calibrate linearity and/or resolution of the plurality of controllable phase-shifters 392240 and/or the plurality of controllable phase-shifters 392340, for example, according to a predefined constellation-point map, e.g., as described below. In some demonstrative aspects, calibration and control sub-system 392400 may be configured to control and/or calibrate the plurality of controllable phase-shifters 392240 and/or the plurality of controllable phase-shifters 392340, for example, according to a Look Up Table (LUT) 392450, e.g., as described below. In some demonstrative aspects, LUT 392450 may be generated and/or updated by calibration and control sub-system 392400. In other aspects, LUT 392450 may not be generated by calibration and control sub-system 392400. For example, LUT 392450 may include, for example, a predefined LUT, which may be, for example, preconfigured at transceiver 392000, e.g., as described below. In some demonstrative aspects, LUT 392450 may include, for example, a plurality of pairs of voltage values corresponding to a respective plurality of constellation points, for example, according to the predetermined constellation-point map, e.g., as described below. In some demonstrative aspects, for example, a pair of voltage values of the plurality of pairs of voltage values may include, for example, a first I voltage value to be applied to a first control signal, e.g., control signal 392410, a first Q voltage value to be applied to a second control signal, e.g., control signal 392420, a second I voltage value to be applied to a third control signal, e.g., control signal 392430, and a second Q voltage value to be applied to a fourth control signal, e.g., control voltage 392440, e.g., as described below. Reference is made to FIG. 180, which schematically illustrates an electronic circuit plan of phase shifting circuitry 393000, in accordance with some demonstrative aspects. For example, one or more elements and/or components of phase shifting circuitry 393000 may be implemented as part of a controllable phase-shifter 392240 and/or as part of controllable phase-shifter 392340, e.g., as described above with reference to FIG. 179. The phase shifting circuitry described herein can be incorporated in one or more circuits (e.g., radio chain circuitry 372) within the RF circuitry 325 (FIG. 3D) of mmWave communication circuitry 300 shown in FIG. 3A, although the phase shifting circuitry is not limited to such. In one example, one or more elements and/or components of phase shifting circuitry 33000 may be implemented as part of Q phase shifting circuitry 392244 and/or as part of I phase shifting circuitry 392242, e.g., as described above with reference to FIG. 179. In some demonstrative aspects, phase shifting circuitry 393000 may be configured, for example, to provide a phase shifted signal, for example, a differential phase shifted signal 393010 including a positive phase shifted signal 393015 and a negative phase shifted signal 393020, for example, based on an I signal 393070, e.g., a differential I signal, and a Q signal 393080, e.g., a differential Q signal, e.g., as described below. For example, the phase shifted signal 393010 may include a phase shifted I signal, e.g., phase shifted I signal 392280 (FIG. 179). In some demonstrative aspects, phase shifting circuitry 393000 may be configured, for example, to provide a phase shifted signal, for example, a differential phase shifted signal 393090 including a positive phase shifted signal (not shown in FIG. 180) and a negative phase shifted signal (not shown in FIG. 180), for example, based on I signal 393070, e.g., a differential I signal, and Q signal 393080, e.g., a differential Q signal, e.g., as described below. For example, the phase shifted signal 393090 may include a phase shifted Q signal, e.g., phase shifted Q signal 392290 (FIG. 179). In some demonstrative aspects, as show in FIG. 180, phase shifting circuitry 393000 may include, for example, a first plurality of transistors 393600, e.g., in a cascode gate arrangement, which may be configured to generate a shifted I signal 393050, for example, according to an I control voltage 393510, e.g., as described below. In some demonstrative aspects, the first plurality of transistors 393600 may include, for example, one or more Field Effect Transistors (FETs), one or more bipolar-junction-transistor (BJT), and/or any other type of transistors. In some demonstrative aspects, phase shifting circuitry 393000 may include, for example, a first VDAC 393500, which may be coupled to the first plurality of transistors 393600. For example, first VDAC 393500 may be configured to convert a first control signal 393300, e.g., an I control signal, into I control voltage 393510, and to provide I control voltage 393510 to the first plurality of transistors 393600, e.g., as described below. In some demonstrative aspects, first control signal 393300 may include, for example, a first digital signal, e.g., control signal 392410 (FIG. 179), which may be configured to apply first data to phase shifting circuitry 393000, for example, based on, the predefined constellation-point map, e.g., as described below. In some demonstrative aspects,first VDAC 393500 may include, for example, a 5-bit VDAC, a 6- bit VDAC, and/or a VDAC of any other resolution. In some demonstrative aspects, phase shifting circuitry 393000 may include, for example, a first I sign switch 393610 and/or a second I sign switch 393620, which may be operably coupled to the first plurality of transistors 33600. For example, first I sign switch 393610 and/or second I sign switch 33620 may be configured to apply a positive I signal or a negative I signal to the first plurality of transistors 393600. For example, first I sign switch 393610 and/or second I sign switch 393620 may be configured to switch between applying the positive I signal to the first plurality of transistors 393600, for example, when a first I sign control signal 393030 is applied to first I sign switch 393610 and/or second I sign switch 393620, and applying a negative I signal to the first plurality of transistors 393600, for example, when a second I sign control signal 393040 is applied to the first I sign switch 393610 and/or to the second I sign switch 393620. In some demonstrative aspects, first I sign switch 393610 and/or second I sign switch 393620may include, for example, one or more FETs, one or more BJTs, and/or any other type of transistors and/or switch circuitry. In some demonstrative aspects, as show in FIG. 180, phase shifting circuitry 393000 may include, for example, a second plurality of transistors 393650, e.g., in a cascode gate arrangement, which may be configured to generate a shifted Q signal 393060, for example, according to a Q control voltage 393520, e.g., as described below. In some demonstrative aspects, the second plurality of transistors 393650 may include, for example, one or more FETs, one or more BJTs, and/or any other type of transistors. In some demonstrative aspects, phase shifting circuitry 393000 may include, for example, a second VDAC 393550, which may be coupled to the second plurality of transistors 393650. For example, second VDAC 393550 may be configured to convert a second control signal 393350, e.g., a Q control signal, into Q control voltage 393520, and to provide Q control voltage 393520 to the second plurality of transistors 393650, e.g., as described below. In some demonstrative aspects, second control signal 393350 may include, for example, a second digital signal, e.g., control signal 392420 (FIG. 179), which may be configured to apply second data to phase shifting circuitry 393000, for example, based on the predefined constellation-point map, e.g., as described below. In some demonstrative aspects, second VDAC 393550 may include, for example, a 5-bit VDAC, a 6-bit VDAC and/or a VDAC of any other resolution. In some demonstrative aspects, phase shifting circuitry 393000 may include, for example, a first Q sign switch 393630 and/or a second Q sign switch 393640, which may be operably coupled to second plurality of transistors 393650. For example, first Q sign switch 393630 and/or second Q sign switch 393640 may be configured to switch between applying a positive Q signal or a negative Q signal to, for example, second plurality of transistors 393650. For example, first Q sign switch 393630 and/or second Q sign switch 393640 may be configured to apply a positive Q signal or a negative Q signal to the second plurality of transistors 393650. For example, first Q sign switch 393630 and/or second Q sign switch 393640 may be configured to switch between applying the positive Q signal to the second plurality of transistors 393650, for example, when a first Q sign control signal 393035 is applied to first Q sign switch 393630 and/or second Q sign switch 393640, and applying a negative Q signal to the second plurality of transistors 393650, for example, when a second Q sign control signal 393045 is applied to the first Q sign switch 393630 and/or to the second Q sign switch 393640. In some demonstrative aspects, first Q sign switch 393630and/or a second Q sign switch 393640 may include, for example, one or more FETs, one or more BJTs, and/or any other type of transistors and/or a switch circuit. In some demonstrative aspects, phase shifting circuitry 393000 may include, for example, a combiner 393400, which may be operably coupled to the first plurality of transistors 393600 and the second plurality of transistors 393650. For example, combiner 393400 may be configured to combine, for example, shifted I signal 393050 and shifted Q signal 393060, e.g., as described below. For example, combiner 393400 may combine, for example, a positive shifted I signal 393100 with a positive shifted Q signal 393200, and may combine, for example, a negative shifted I signal 393110 with a negative shifted Q signal 393210. In some demonstrative aspects, phase shifting circuitry 393000 may be configured to provide the shifted I signal, e.g., positive shifted I signal 393100 and negative shifted I signal 393110, by shifting a phase of I signal 393070, for example, according to the first control signal 393300, e.g., as described below. In some demonstrative aspects, phase shifting circuitry 393000 may be configured to provide the shifted Q signal, e.g., positive shifted Q signal 393200 and negative shifted Q signal 393210, by shifting a phase of Q signal 393040, for example, according to a second control signal 393350, e.g., as described below. In some demonstrative aspects, phase shifting circuitry 393000 may be configured to provide the phase shifted signal 393010, for example, by combining shifted I signal 393050 with the shifted Q signal 393060. Reference is made to FIG. 181, which schematically illustrates a first quadrant 394000 of a constellation-point map, in accordance with some demonstrative aspects. In some demonstrative aspects, a controllable phase shifter, e.g., controllable phase shifter 392240 (FIG. 179) and/or controllable phase shifter 392340 (FIG. 179), may be configured to shift the phase of an I signal and/or the phase of a Q signal according to points in the consolation-point map of FIG. 181. In some demonstrative aspects, as shown in FIG. 181, the first quadrant 394000 of the constellation point map may include, for example, a plurality of constellation points defined by a plurality of I values, e.g., along a first axis (“I axis”), and a plurality of Q values, e.g., along a second axis (“Q axis”). For example, as shown in FIG. 181, the I axis and the Q axis may include values in the range between 0 and 1, which may represent a first quadrant of a constellation-point map. In some demonstrative aspects, for example, in a second quadrant of the constellation-point map, the I axis may include values in the range between 0 and -1, and the Q axis may include values in the range between 0 and 1; in a third quadrant of the constellation-point map, the I axis may include values in the range between 0 and -1 and the Q axis may include values in the range between 0 and -1; and in a fourth quadrant of the constellation-point map, the I axis may include values in the range between 0 and 1 and the Q axis may include values in the range between 0 and -1. Reference is made to FIG. 182, which schematically illustrates a graph 395000 depicting a gain variation of constellation points verses ideal phase shifted constellation points, in accordance with some demonstrative aspects. In some demonstrative aspects, a controllable phase shifter, e.g., controllable phase shifter 392240 (FIG. 179) and/or controllable phase shifter 392340 (FIG. 179), may be calibrated to correct an I/Q gain and/or phase imbalance, for example, with high precision, for example, according to a constellation–point map, e.g., the constellation point map of FIG. 181. In some demonstrative aspects, graph 395000 depicts calibrated phase shifted constellationpoints 395200 of a calibrated controllable phase shifter, e.g., controllable phase shifter 392240 (FIG. 179) and/or controllable phase shifter 392340, for example, relative to ideal points 395100 of an ideal constellation map. In some demonstrative aspects, as shown in FIG. 182, the calibrated phase shifted constellationpoints 395200 of the calibrated controllable phase shifter may be within +/- 0.5dB, and/or a similar mismatch from the ideal points 395100 of the ideal constellation map. Referring back to FIG. 4, in some demonstrative aspects, RF circuitry 425 may be configured according to a radio architecture, which may include at least one PA-LNA Interface, which may be configured to interface between a signal antenna to a PA or LNA, for example, by canceling a leakage ofa Tx signal from a PA, e.g., as described below. In some demonstrative aspects, a radio architecture may include a PA-LNA interface, e.g., as described below. In some demonstrative aspects, the PA-LNA interface may interface signals between at least one antenna and a PA and LNA, for example, Rx signals from the antenna to the LNA and/or Tx signals from the PA to the antenna, e.g., as described below. In some demonstrative aspects, the PA-LNA interface may be included as part of, and/or may perform one or more operations and/or functionalities of, radio chain circuitry, e.g., as part of sub-system 435 (FIG. 4), and/or any other sub-system and/or element, if desired. In some demonstrative aspects, implementing the PA-LNA interface in the radio architecture may provide one or more benefits and/or solve one or more technical problems, for example, by mitigating, reducing, and/or canceling a leakage of the Tx signal from the PA to LNA, and/or providing any other additional or alternative technical benefits and/or advantages. The term “cancel” as used herein with respect to leakage may include partially or entirely cancelling, reducing, lessening, attenuating, and/or mitigating the leakage and/or an impact of the leakage on one or more signals, inputs, outputs, elements and/or components. In some demonstrative aspects, the PA-LNA interface may be configured to provide a desired level of isolation, e.g., a high isolation, between a Tx path and an Rx path, for example, to ensure LNA reliability in a Tx mode, e.g., as described below. In some demonstrative aspects, the PA-LNA interface may be configured to maintain a reduced level of insertion loss, e.g., a low insertion loss, for example, to allow reducing, e.g., minimizing, degradation in Noise Figure (NF) power, e.g., at an Rx mode, and/or reducing, e.g., minimizing, degradation in output power, e.g., at a Tx mode, e.g., as described below. In some demonstrative aspects, the PA-LNA interface may be configured to cancel the leakage of the Tx signal by summing the leakage of the Tx signal with a cancelation signal at an input of the LNA, e.g., as described below. Reference is now made to FIG. 183, which schematically illustrates a block diagram of a transceiver 396000, in accordance with some demonstrative aspects. For example, one or more elements and/or components of transceiver 396000 may be implemented as part of a transceiver 371100, e.g., as described above with reference to FIG. 158. In some demonstrative aspects, transceiver 396000 may include, or may be operably coupled to, one or more antennas 396400, which may be, for example, operably coupled to an antenna terminal 396150, e.g., as described below. In some demonstrative aspects, the one or more antennas 396400 may include, for example, a phased-array antenna, a dipole antenna, an internal antenna, and/or any other additional or alternative type of antenna. In some demonstrative aspects, transceiver 396000 may include a PA-LNA interface 396100 configured to interface antenna terminal 396150 with a PA 396310 and an LNA 36310, e.g., as described below. In some demonstrative aspects, transceiver 396000 may include, for example, a receiver 396200, e.g., including Rx circuitry, including LNA 396210, and/or a transmitter 396300, e.g., including Tx circuitry, including PA 396310, e.g., as described below. In some demonstrative aspects, PA-LNA interface 396100 may be configured to provide a Tx signal 36010 from PA 396310 to antenna terminal 396150, for example, at a Tx mode, and to provide an Rx signal 396050 from antenna terminal 396150 to LNA 396140, for example, at an Rx mode, e.g., as described below. In some demonstrative aspects, transceiver 396000 may include a half-duplex transceiver, which may be configured to handle reception of Rx signal 396050 and transmission of Tx signal 398010 separately and/or during non-overlapping time periods, e.g., as described below. In some demonstrative aspects, transceiver 396000 may include a full-duplex transceiver, which may be configured to handle reception of Rx signal 396050 and transmission of Tx signal 396010 simultaneously and/or during overlapping time periods, e.g., as described below. In some demonstrative aspects, transmitter 396300 may include, for example, one or more elements and/or components of, and/or may perform one or more functionalities of, an outphasing transmitter, a Doherty transmitter, a digital transmitter, or the like. In some demonstrative aspects, transmitter 396300 may include, for example, a mixer 396320 to mix a LO signal 396020 with a data signal 396030, for example, a data of a required phase, to generate a phase modulated signal 396040. In some demonstrative aspects, transmitter 396300 may include PA 396310, which may be configured to amplify phase modulated signal 396040 to generate Tx signal 396010, e.g., as described below. In some demonstrative aspects, transmitter 396300 may include some or all the elements shown in FIG. 183and/or may include one or more additional or alternative elements to perform one or more additional or alternative functionalities. For example, transmitter 396300 may include one or more elements of, and/or perform one or more functionalities of, transmitter 380100 (FIG. 38). In some demonstrative aspects, receiver 396100 may be configured to downconvert an LNA input signal 396055, which may be provided by PA-LNA interface 396100 based Rx signal 396050 received at antenna port 396150, for example, at the Rx mode, e.g., as described below. In some demonstrative aspects, receiver 396200 may include LNA 396210, which may be configured, for example, to amplify LNA input signal 396055 and to provide an amplified Rx signal 396057 to a splitter 396220. For example, splitter 396220 may split amplified Rx signal 396057 into an I Rx signal 396058 and a Q Rx signal 396059. In some demonstrative aspects, splitter 396220 may include a Wilkinson splitter, a 1-to-2 splitter and/or any other type of splitter. In some demonstrative aspects, receiver 396200 may include for example, an I signal balanced mixer 396240 and/or a Q signal balanced mixer 396230, which may be, for example, operably coupled to quadrature hybrid circuitry 396250. For example, I signal balanced mixer 396240 may receive I Rx signal 396058 from splitter 396220, and an LO signal with a first phase, e.g., a phase of 0 degrees or any other phase, from quadrature hybrid circuitry 396250, and may generate a positive I signal and a negative I signal. In some demonstrative aspects, for example, Q signal balanced mixer 396230 may receive Q Rx signal 396059 from splitter 396220 and the LO signal with a second phase, e.g., a phase of 90 degrees or any other phase, from quadrature hybrid circuitry 396250, and may generate a positive Q signal and a negative Q signal. In some demonstrative aspects, receiver 396200 may include, for example, a driver amplifier 396260 and/or a driver amplifier 36250. For example, driver amplifier 396250 may be configured to output the negative Q signal and the positive Q signal to, for example, a baseband. For example, driver amplifier 396260 may be configured to output the negative I signal and the positive I signal to, for example, the baseband. In some demonstrative aspects, receiver 396200 may include some or all the elements shown in FIG. 183and/or may include one or more additional or alternative elements to perform one or more additional or alternative functionalities. In some demonstrative aspects, PA-LNA interface 396100 may be configured to apply, for example, a high impedance to an input of LNA 396310, for example, at the Tx mode, e.g., as described below. In some demonstrative aspects, PA-LNA interface 396100 may be configured to apply, for example, a high impedance at an output of PA 396310, for example, at the Rx mode. In some demonstrative aspects, PA-LNA interface 396100 may be configured to cancel, mitigate, attenuate, and/or reduce an impact of Tx signal 396010 on LNA 396210, for example, by cancelling, mitigating, attenuating, and/or reducing a leakage of Tx signal 396010 to LNA 396210, e.g., as described below. In some demonstrative aspects, PA-LNA interface 396100 may include a sensor 396130, which may be configured, for example, to provide a sensed signal 396060, which may be based on Tx signal 396010 from PA 396319, e.g., as described below. For example, sensor 396130 may include a capacitive sensor. In other aspects sensor 396130 may include an inductive sensor and/or any other type of sensor. In some demonstrative aspects, PA-LNA interface 396100 may include a phase rotator 396110 to provide a phase rotated signal 396070, for example, by rotating a phase of sensed signal 396060. In some demonstrative aspects, phase rotator 396110 may be configured to rotate the phase of sensed signal 396060, for example, by 180 degrees. In other aspects, any other phase rotation may be used. In some demonstrative aspects, PA-LNA interface 396100 may include a variable gain amplifier (VGA) 396120 configured to provide a Tx leakage cancelation signal 396080, for example, by amplifying phase rotated signal 396070, for example, based on an amplitude of Tx signal 396010. In some demonstrative aspects, PA-LNA interface 396100 may include a combiner 396140, which may be configured to combine, for example, a first combiner input signal 36085 with a second combiner input signal 396095, e.g., as described below. In some demonstrative aspects, the first combiner input signal 396085 may include Tx leakage cancellation signal 396080 and the second combiner input signal may include, for example a Tx leakage 396090 from Tx signal 396010 to the LNA 396210, e.g., as described below. In some demonstrative aspects, combiner 396140 may include a Wilkinson combiner. In other aspects, combiner 396140 may include any other type of 2-to-1 combiner. In some demonstrative aspects, phase rotator 396110 and/or VGA 396210 may be configured to provide Tx leakage cancelation signal 396080 having a phase and an amplitude, which may be configured to cancel, mitigate, attenuate, and/or reduce an impact of Tx leakage 396090. In some demonstrative aspects, phase rotator 396110 may be configured to provide phase rotated signal 396070, for example, by rotating the phase of sensed signal 396060, e.g., by 180 degrees, for example, such that a resulting phase of Tx leakage cancelation signal 396080 may be substantially opposite to a phase of the Tx leakage 396090. In some demonstrative aspects, VGA 396120 may be configured to provide Tx leakage cancelation signal 396080 by amplifying phase rotated signal 396070, for example, such that a resulting amplitude of Tx leakage cancelation signal 396080 may be substantially equal to an amplitude of the Tx leakage 396090. In some demonstrative aspects, a relationship between amplitudes of Tx leakage 396090 and amplitude and/or frequency levels of Tx signal 396010 may be determined and/or known apriority, for example, based on simulation. For example, Tx leakage 396090 may be characterized through simulation by observing second combiner input signal 396095 for various amplitude and/or frequency levels of Tx signal 396010. In some demonstrative aspects, a gain of VGA 396120 may be set to cancel Tx leakage 396090. For example, the gain of VGA 396120 may be set by a baseband controller (not shown in FIG. 183), for example, a baseband sub-system 110 (FIG. 1), for example, based on the amplitude and/or frequency level of Tx signal 396010. In one example, a plurality of gain values corresponding to a plurality of amplitude and/or frequency levels of Tx signal 396010 may be stored, for example, in a memory or a Look Up Table (LUT), and the gain of VGA 396120 may be set, for example, by the baseband controller, for example, based on a gain corresponding to an amplitude and/or frequency of Tx signal 396010. In other aspects, the gain of VGA 396120 may be set and/or controlled according to any additional or alternative parameter, e.g., corresponding to Tx signal 396010. In some demonstrative aspects, combiner 396140 may combine Rx signal 396050 with Tx leakage cancellation signal 396080, for example, in a case where Rx signal 396050 is to be received during a time period, which at least partially overlaps a time period for transmission of Tx signal 396010. In some demonstrative aspects, at the Rx mode, for example second combiner input signal 396095 may include a combination of Rx signal 396050 from the antenna terminal 396150 and the Tx leakage 396090 from Tx signal 396010 to the LNA 396130. In some demonstrative aspects, at the Rx mode, for example, combiner 396140 may be configured to provide to LNA 396210 the LNA input signal 396055, for example, based on a sum of first combiner input signal 396085 and second combiner input signal 396095. Referring back to FIG. 4, in some demonstrative aspects, RF circuitry 425 may be configured according to a radio architecture, which may include at least one Quadrature LO distribution network circuitry, which may be configured to distribute LO I and Q signals to components and/or sub-systems of RF circuitry 1000, for example, based on a LO signal, e.g., as described below. In some demonstrative aspects, a radio architecture may include a quadrature LO generator, which may be configured to generate, for example, I signals and/or Q signals based on a LO signal, e.g., as described below. In some demonstrative aspects, the quadrature LO generator may be configured to distribute the I signals and/or the Q signals to one or more elements, sub-systems, circuits and/or components of a transmitter and/or a receiver, e.g., as described below. In some demonstrative aspects, the quadrature LO generator may include a LO distribution network, which may be configured to generate and distribute the I and/or Q signals, for example, based on the LO signal, e.g., as described below. In some demonstrative aspects, the LO distribution network may be configured to generate the I and/or Q signals based on a multiplication factor, denoted X, which may be based, for example, on a ratio between a carrier frequency and a frequency of the LO signal, e.g., as described below. In some demonstrative aspects, for example, the carrier frequency may include a frequency of a carrier signal to carry one or more signals to be transmitted and/or received. In some demonstrative aspects, the LO distribution network may be configured to generate the I and/or Q signals based on a multiplication factor X=3, for example, if the LO signal has a frequency, which is a third of the carrier frequency, e.g., as described below. In some demonstrative aspects, for example, the carrier frequency may include, for example, a 60 GHz frequency, and the LO signal may have a 20 GHz frequency. According to these aspects, for example, the LO distribution network may be configured to generate the I and/or Q signals based on a multiplication factor X=3. In other aspects, the LO distribution network may be configured to generate the I and/or Q signals based on any other multiplication factor, any other carrier frequency, any other LO signal frequency, and/or any other combination thereof. In some demonstrative aspects, the LO distribution network may be configured to generate the I and/or Q signals, for example, by shifting a phase of the LO signal to provide phase shifted signals, and multiplying the phase and frequency of the phase shifted signals according to the multiplication factor X, e.g., as described below. In some demonstrative aspects, the LO distribution network may be configured to apply to the LO signal a phase shift, denoted , which may be configured, for example, in accordance with the multiplication factor X. e.g., as described below. In some demonstrative aspects, for example, the multiplication factor X and/or the phase shift  may be configured, for example, such that X*=90 degrees, for example, to generate the I and Q signals with a phase shift of 90 degrees (o), e.g., as described below. In some demonstrative aspects, for example, the LO distribution network may be configured to apply to the LO signal a phase shift of =30o to generate first and second shifted signals with a phase shift of 30o, and to triple the frequency and phase of the first and second shifted signals, for example, using frequency triplers, e.g., as described below. In other aspects, any other phase shift and/or multipliers may be used. In some demonstrative aspects, implementing the quadrature LO generator in the radio architecture may provide one or more benefits and/or solve one or more technical problems, for example, by achieving a reduced phase variation, e.g., even less than a 2 degree phase variation over the frequency band of 48-72 GHz, delivering almost equal amplitudes for I and Q signals at outputs of frequency triplers, consuming low power, and/or providing one or more other additional or alternative technical benefits and/or advantages. In some demonstrative aspects, the quadrature LO generator may be included as part of, and/or may perform one or more operations and/or functionalities of, up-conversion and/or down-conversion circuitry, sub-systems, and/or elements, e.g., as part of sub-system 415 (FIG. 4), synthesizer circuitry, e.g., as part of sub-system 420 (FIG. 4), and/or any other sub-system and/or element, if desired. Reference is now made to FIG. 184, which schematically illustrates a block diagram of a transceiver 397000, in accordance with some demonstrative aspects. For example, one or more elements and/or components of transceiver 397000 may be implemented as part of transceiver 371100 (FIG. 158). In some demonstrative aspects, transceiver 397000 may include, for example, a half-duplex transceiver, e.g., as described below. In some demonstrative aspects, transceiver 397000 may include a millimeter wave transceiver, which may be configured to operate over a 60 GHz frequency band. In other aspects, transceiver 397000 may include any other type of transceiver configured to operate on any other additional or alternative frequency band. In some demonstrative aspects, transceiver 397000 may include, for example a LO 397600 to generate a LO signal 397080, e.g., as described below. In some demonstrative aspects, LO 397600 may include, for example a crystal oscillator, a Phase Lock Loop (PLL), an injection LO (ILO), and/or any other type of LO. In some demonstrative aspects, LO 397600 may be configured, for example, to generate LO signal 397080 having a frequency, which is based on, e.g., a fraction of, a carrier frequency to be implemented by transceiver 397000, e.g., as described below. In some demonstrative aspects, LO 397600 may be configured to generate LO signal 397080 having a frequency, which is a third of the carrier frequency, e.g., as described below. In some demonstrative aspects, LO 397600 may include, for example, a 20 GHz LO, for example, to generate LO signal 397080 having a frequency in a 20 GHz frequency band, for example, a third of a 60 GHz carrier frequency band, e.g., as described below. In other aspects, LO 397600 may be configured to generate LO signal 397080 having any other frequency, which may be based on any other carrier frequency. In some demonstrative aspects, transceiver 397000 may include, for example, LO distribution network circuitry 397500, which may be configured to distribute, for example, phase-shifted LO signals, for example, to one or more transmitter and/or receiver components, circuits and/or sub-systems, e.g., as described below. In some demonstrative aspects, LO distribution network circuitry 397500 may be configured, for example, to distribute one or more Tx signals, e.g., a Tx I signal 397055 and/or a Tx Q signal 397070, for example, to an IQ transmitter 397300; and/or one or more Rx signals, e.g., an Rx I signal 397025 and/or an Rx Q signal 397040, for example, to an IQ receiver 397100, e.g., as described below. In some demonstrative aspects, LO distribution network circuitry 397500 may include at least one IQ generator to generate at least one respective pair of an I signal and a Q signal based on LO signal 397080 from LO 397600, e.g., as described below. In some demonstrative aspects, the at least one IQ generator may include, may be implemented as part of, and/or may perform one or more functionalities of, a quadrature LO generator, e.g., as described below. In some demonstrative aspects, LO distribution network circuitry 397500 may include, for example, a plurality of driver amplifiers, for example, driver amplifier 397530, a driver amplifier 397540, a driver amplifier 397550 and/or a driver amplifier 397560, which may be configured, for example, to drive LO signal 397080 to the at least one IQ generator. In other aspects, any other number and/or configuration of driver amplifiers and/or any other additional or alternative circuits or components may be implemented to distribute LO signal 397080 to the at least one IQ generator. In some demonstrative aspects, LO distribution network circuitry 397500 may include a first IQ generator, e.g., a Tx IQ generator 397510, which may be configured to generate a first I signal, e.g., a Tx I signal 397055, and a first Q signal, e.g., a Tx Q signal 397070, for example, based on LO signal 397080; and/or a second IQ generator, e.g., an Rx IQ generator 397520, which may be configured to generate a second I signal, e.g., an Rx I signal 397025, and a second Q signal, e.g., an Rx Q signal 397040, for example, based on LO signal 397080, e.g., as described below. In some demonstrative aspects, Tx IQ generator 397510 and/or Rx IQ generator 397520, may be implemented as part of, and/or may perform one or more functionalities of, a quadrature LO generator, e.g., as described below. In some demonstrative aspects, LO distribution network circuitry 397500 may include two IQ generators, for example, Tx IQ generator 397510 and Rx IQ generator 397520, e.g., as shown in FIG. 184. In other aspects, LO distribution network circuitry 397500 may include any other number of IQ generators, e.g., one IQ generator, e.g., a Tx IQ generator or an Rx IQ generator, or more than two IQ generators. In some demonstrative aspects, Tx IQ generator 397510 may be configured as a Tx IQ generator to generate Tx I signal 397055 and Tx Q signal 397070 to be upconverted into a Tx signal, which may be transmitted via one or more antennas 397325, e.g., as described below. In some demonstrative aspects, Rx IQ generator 397520 may be configured as a Rx IQ generator to generate Rx I signal 397025 and Rx Q signal 397040 to be downconverted into one or more IF signals, for example, based on an Rx signal, which may be received by one or more antennas, e.g., as described below. In some demonstrative aspects, an IQ generator of LO distribution network 397500, e.g., IQ generator 397510 and/or Rx IQ generator 397520, may include, for example, phase shifting circuitry to generate a first phase shifted signal and a second phase shifted signal based on LO signal 397080, e.g., which may have a first frequency, for example, such that a phase of the second phase shifted signal may be shifted by a phase shift, e.g., 30o or by any other phase shift, from a phase of the first phase shifted signal, e.g., as described below. In some demonstrative aspects, Tx IQ generator 397510 may include, for example, phase shifting circuitry 397512 to generate a first phase shifted signal 397052 and a second phase shifted signal 397072, for example, based on LO signal 397080, which may have a first frequency, e.g., a 20 GHz frequency. For example, a phase of the second phase shifted signal 397072 may be shifted by 30o from a phase of first phase shifted signal 397052, e.g., as described below. For example, first phase shifted signal 397052 and/or second phase shifted signal 397072 may have a frequency of 20 GHz, e.g., when LO signal 397080 has a frequency of 20 GHz. In some demonstrative aspects, first phase shifted signal 397052 may include, for example, a differential signal including a plurality of signals (not shown in FIG. 184). For example, the differential signal may include, for example, a first I phase shifted signal and a second I phase shifted signal, e.g., as described below. In some demonstrative aspects, second phase shifted signal 397072 may include, for example, a differential signal including a plurality of signals (not shown in FIG. 184). For example, the differential signal may include, for example, a first Q phase shifted signal and a second Q phase shifted signal, e.g., as described below. In some demonstrative aspects, Rx IQ generator 397520 may include, for example, phase shifting circuitry 397522 to generate a third phase shifted signal 397022 and a fourth phase shifted signal 397042, for example, based on LO signal 397080, which may have the first frequency. For example, a phase of the fourth phase shifted signal 397042 may be shifted by a phase shift, e.g., 30o or any other phase shift, from a phase of third phase shifted signal 397022, e.g., as described below. For example, third phase shifted signal 397022 and/or fourth phase shifted signal 397042 may have a frequency of 20 GHz, e.g., when LO signal 397080 has a frequency of 20 GHz. In some demonstrative aspects, the first frequency may be a third of a carrier frequency. For example, LO signal 397080, first phase shifted signal 397052, second phase shifted signal 397072, third phase shifted signal 397022, and/or fourth phase shifted signal 397042 may have a frequency of 20 GHz, for example, when the carrier frequency includes a 60 GHz frequency. In other aspects, LO signal 397080, first phase shifted signal 397052, second phase shifted signal 397072, third phase shifted signal 397022, and/or fourth phase shifted signal 397042 may have any other frequency, and/or any other fraction of the carrier frequency. In some demonstrative aspects, third phase shifted signal 397022 may include, for example, a differential signal including a plurality of signals (not shown in FIG. 184). For example, the differential signal may include, for example, a first I phase shifted signal and a second I phase shifted signal, e.g., as described below. In some demonstrative aspects, fourth phase shifted signal 397042 may include, for example, a differential signal including a plurality of signals (not shown in FIG. 184). For example, the differential signal may include, for example, a first Q phase shifted signal and a second Q phase shifted signal, e.g., as described below. In some demonstrative aspects, the IQ generator of LO distribution network 397500, e.g., Tx IQ generator 397510 and/or Rx IQ generator 397520, may include, for example, first tripler circuitry to generate an I signal having a second frequency, by tripling the phase of the first phase shifted signal generated by the IQ generator, and by tripling a frequency of the first phase shifted signal generated by the IQ generator, e.g., as described below. In some demonstrative aspects, Tx IQ generator 397510 may include, for example, first tripler circuitry 397514 to generate Tx I signal 397055 having a second frequency, for example, by tripling the phase of first phase shifted signal 397052 and tripling a frequency of first phase shifted signal 397052, e.g., as described below. In some demonstrative aspects, Tx IQ generator 397510 may be configured to generate Tx I signal 397055, which may have a frequency equal to the carrier frequency, for example, 60 GHz. For example, Tx I signal 397055 may have a frequency of 60 GHz, when first phase shifted signal 397052 has a frequency of 20 GHz. In other aspects, Tx I signal 397055 may have any other carrier frequency, for example, based on a multiple of a frequency of first phase shifted signal 397052, which in turn may be a fraction of any other carrier frequency. In some demonstrative aspects, Rx IQ generator 397520 may include, for example, first tripler circuitry 397524 to generate Rx I signal 397025 having a second frequency, for example, by tripling the phase of third phase shifted signal 397022 and tripling a frequency of third phase shifted signal 397022, e.g., as described below. For example, Rx I signal 397025 may have a frequency of 60 GHz, when first phase shifted signal 397052 has a frequency of 20 GHz. In other aspects, Rx I signal 397025 may have any other carrier frequency, for example, based on a multiple of a frequency of third phase shifted signal 397022, which in turn may be a fraction of any other carrier frequency. In some demonstrative aspects, the IQ generator of LO distribution network circuitry 397500, e.g., Tx IQ generator 397510 and/or Rx IQ generator 397520, may include, for example, second tripler circuitry to generate a Q signal having the second frequency, for example, by tripling the phase of the second phase shifted signal and tripling a frequency of the second phase shifted signal, e.g., as described below. In some demonstrative aspects, Tx IQ generator 397510 may include, for example, second tripler circuitry 397516 to generate Tx Q signal 397070 having a second frequency, for example, by tripling the phase of second phase shifted signal 397072 and tripling a frequency of second phase shifted signal 397072, e.g., as described below. For example, Tx Q signal 397070 may have a frequency of 60 GHz, when second phase shifted signal 397072 has a frequency of 20 GHz. In other aspects, Tx Q signal 397070 may have any other carrier frequency, for example, based on a multiple of a frequency of second phase shifted signal 397072, which in turn may be a fraction of any other carrier frequency. In some demonstrative aspects, Rx IQ generator 397520 may include, for example, second tripler circuitry 397526 to generate Rx Q signal 397040 having a second frequency, for example, by tripling the phase of fourth phase shifted signal 397042 and tripling a frequency of fourth phase shifted signal 397042, e.g., as described below. For example, Rx Q signal 397040 may have a frequency of 60 GHz, when fourth phase shifted signal 397042 has a frequency of 20 GHz. In other aspects, Rx Q signal 397040 may have any other carrier frequency, for example, based on a multiple of a frequency of fourth phase shifted signal 397042, which in turn may be a fraction of any other carrier frequency. In some demonstrative aspects, the first tripler circuitry of the IQ generator, e.g., first tripler circuitry 397514 of Tx IQ generator 397510 and/or first tripler circuitry 397524 of Rx IQ generator 397520, may include first imbalance and amplitude circuitry (not shown in FIG. 184) to balance an amplitude of a first I phase shifted signal generated by the phase shifting circuitry of the IQ generator, e.g., a positive I phase shifted signal, for example, according to a second Q phase shifted signal, of the IQ generator, e.g., a negative Q phase shifted signal; and/or to balance an amplitude of a second I phase shifted signal, e.g., a negative I phase shifted signal, for example, according to a first Q phase shifted signal, e.g., a positive Q phase shifted signal, e.g., as described below. In some demonstrative aspects, the second tripler circuitry of the IQ generator, e.g., second tripler circuitry 397516 of Tx IQ generator 397510 and/or second tripler circuitry 397526 of Rx IQ generator 397520, may include second imbalance and amplitude circuitry (not shown in FIG. 184) to balance an amplitude of the first Q phase shifted signal generated by the phase shifting circuitry of the IQ generator, e.g., the positive Q phase shifted signal, for example, according to the second I phase shifted signal, e.g., the negative I phase shifted signal; and/or to balance an amplitude of the second Q phase shifted signal e.g., the negative Q phase shifted signal, for example, according to the first I phase shifted signal, e.g., the negative I phase shifted signal, e.g., as described below. In some demonstrative aspects, phase shifting circuitry 397512 and/or phase shifting circuitry 397522 may include passive phase shifting circuitry (not shown in FIG. 184), e.g., as described below. In some demonstrative aspects, the phase shifting circuitry of the IQ generator, e.g., phase shifting circuitry 397512 of Tx IQ generator 397510, and/or phase shifting circuitry 397522 of Rx IQ generator 3957520, may include first injection LO (ILO) circuitry (not shown in FIG. 184) to generate the first phase shifted signal of the IQ generator, and/or second ILO circuitry (not shown in FIG. 184) to generate the second phase shifted signal of the IQ generator, e.g., as described below. In some demonstrative aspects, IQ receiver 397100 may be configured to utilize Rx I signal 397025 and/or an Rx Q signal 397040, for example, to generate an I IF signal and/or a Q IF signal, for example, based on one or more Rx signals from one or more antennas, e.g., as described below. For example, IQ generator 397100 may include and/or may be operably coupled to, for example, one or more antennas, e.g., including antennas 397130 and/or 397140. In some demonstrative aspects, antennas 397130 and/or 397140 may include, for example, at least one phased-array antenna, dipole antenna, and/or any other type of antenna. In some demonstrative aspects, IQ receiver 397100 may include one or more Low Noise Amplifiers (LNAs), e.g., including an LNA 397110 and/or an LNA 397120, which may be configured to generate at least one amplified Rx signal, e.g., an amplified Rx signal 397015 and/or an amplified Rx signal 397030, for example, based on an Rx signal, e.g., an Rx signal 397010 and/or an Rx signal 397011. In some demonstrative aspects, IQ receiver 397100 may include an RF mixer 397200, which may be configured to downconvert amplified Rx signal 397015 into a downconverted I signal 397020, for example, based on Rx I signal 397025; and/or to downconvert amplified Rx signal 397030 into a downconverted Q signal 397035, for example, based on Rx Q signal 397040, e.g., as described below. In some demonstrative aspects, Rx mixer 397200 may include, for example, a first mixer, e.g., an I mixer 397210, which may be configured to downconvert amplified Rx signal 397015 into downconverted I signal 397020, for example, based on Rx I signal 397025. In some demonstrative aspects, Rx mixer 397200 may include, for example, a second mixer, e.g., a Q mixer 397220, which may be configured to downconvert amplified Rx signal 397030 into downconverted Q signal 397035, for example, based on Rx Q signal 397040. In some demonstrative aspects, IQ transmitter 397300 may be configured to generate an amplified Tx signal 397325 to be transmitted, for example, via one or more antennas 397310, e.g., as described below. In some demonstrative aspects, IQ transmitter 397300 may include and/or may be coupled to the one or more antennas 397310. In some demonstrative aspects, antennas 397310 may include, for example, at least one phased array antenna, dipole antenna and/or any other type of antenna. In some demonstrative aspects, IQ transmitter 397300 may include a Tx mixer 397400, which may be configured to upconvert an IF I signal 397045 into an upconverted I signal 397050, for example, based on the Tx I signal 397055, e.g., as described below. In some demonstrative aspects, Tx mixer 397400 may be configured to upconvert an IF Q signal 397060 into an upconverted Q signal 397065, for example, based on Tx Q signal 397070, e.g., as described below. In some demonstrative aspects, Tx mixer 397400 may include, for example, a first mixer, e.g., an I mixer 397420, which may be configured to upconvert the IF I signal 397045 into upconverted I signal 397050, for example, based on Tx I signal 397055 In some demonstrative aspects, Tx mixer 397400 may include, for example, a second mixer, e.g., a Q mixer 397410, which may be configured to upconvert IF Q signal 397060 into upconverted Q signal 397065, for example, based on a Tx Q signal 397070. In some demonstrative aspects, IQ transmitter 397300 may include, for example, a combiner 397330, which may be configured to combine upconverted I signal 397050 and upconverted Q signal 397065 into a Tx signal 397075. In some demonstrative aspects, IQ transmitter 397300 may include a PA 397320, which may be configured to amplify Tx signal 397075 into amplified Tx signal 397325. For example, amplified Tx signal 397325 may be transmitted via one or more antennas 397310. Reference is made to FIG. 185, which schematically illustrates a quadrature LO generator 398000, in accordance with some demonstrative aspects. In some demonstrative aspects, one or more components of quadrature LO generator 398000 may be implemented, for example, as part of a LO distribution network, e.g., LO distribution network 397500 (FIG. 184), for example, to provide I and Q signals, for example, to a transmitter, e.g., IQ transmitter 397300 (FIG. 184), and/or a receiver, e.g., IQ receiver 397100 (FIG. 184). In some aspects, the quadrature LO generators described herein can be incorporated in one or more circuits (e.g., up-conversion circuitry 350) within the transmit circuitry 315 (FIG. 3B) of mmWave communication circuitry 300 shown in FIG. 3A, although the LO generators are not limited to such. In some demonstrative aspects, one or more components, sub-systems, and/or circuits of quadrature LO generator 398000 may be implemented, for example, as part of a Tx IQ generator, e.g., Tx IQ generator 397510 (FIG. 184), and/or as part of an Rx IQ generator, e.g., Rx IQ generator 397520 (FIG. 184). In some demonstrative aspects, quadrature LO generator 398000 may be configured to generate the I and Q signals, for example, based on a LO signal 398010 and/or LO signal 398020, which may be provided by a LO 398100, e.g., as described below. In some demonstrative aspects, quadrature LO generator 398000 may include an ILO 398200, which may be configured to generate, for example, a first I shifted signal 398030 and/or a second I shifted signal 398040, for example, based on a LO signal 398010 and/or LO signal 398020, e.g., as described below. In some demonstrative aspects, ILO 398200 may include, for example, a controllable resonance sub-system 398205, e.g., in the form of an Inductor(L)-Capacitor (LC) block, and a plurality of transistors, e.g., including transistors 398230, 398240, 398250 and/or 398260. For example, LO 398100 may provide first LO signal 398010 to transistor 398250, and/or second LO signal 398020 to transistor 398260. In some demonstrative aspects, transistors 398230, 398240, 398250 and/or 398260 may include FETs, BJTs, and/or any other type of transistors. In some demonstrative aspects, LO signal 398020 may be out phased from LO signal 398010. For example, LO signal 398010 may have a 20 GHz frequency and a phase of +30o, and/or LO signal 398020 may have a frequency of 20 GHz and a phase of -30o. In other aspects, other frequencies and/or other phase shifts may be used. In some demonstrative aspects, transistor 398230 and transistor 398240 may be configured to cause controllable resonance sub-system 398205 to be in resonance at a deigned frequency, for example, 20 GHz. For example, controllable resonance sub-system 398205 may generate first I shifted signal 398030 and/or second I shifted signal 398040 based on LO signal 398010 and/or LO signal 398020, respectively. For example, second I shifted signal 398040 may be out of phase from first I shifted signal 398030. In some demonstrative aspects, controllable resonance sub-system 398205 may controllably generate first I shifted signal 398030 and/or second I shifted signal 398040, for example, according to a control signal 398050, e.g., as described below. In some demonstrative aspects, control signal 398050 may be provided, for example, by a controller 398800, for example, a baseband controller and/or any other controller. In some demonstrative aspects, control signal 398050 may, for example, control controllable resonance sub-system 398205 to shift the phase of first I shifted signal 398030 and/or second I shifted signal 398040. For example, control signal 398050 may have, for example, 7 bit Capacitors-Digital-to-Analog-Convertor (CAPDAC) control and/or any other control data. In some demonstrative aspects, quadrature LO generator 398000 may include an ILO 398300, which may be configured to generate, for example, a first Q shifted signal 398060 and/or a second Q shifted signal 398070, for example, based on LO signal 398010 and/or LO signal 398020, e.g., as described below. In some demonstrative aspects, ILO 398300 may include, for example, a controllable resonance sub-system 398305, e.g., in the form of a LC block, and a plurality of transistors, e.g., including transistors 398330, 398340, 398350 and/or 398360. For example, LO 398100 may provide first LO signal 398010 to transistor 398350, and/or second LO signal 398020 to transistor 398360. In some demonstrative aspects, transistors 398330, 398340, 398350 and/or 398360 may include FETs, BJTs, and/or any other type of transistors. In some demonstrative aspects, transistor 398330 and transistor 398340 may be configured to cause controllable resonance sub-system 398305 to be in resonance at a deigned frequency, for example, 20 GHz. For example, controllable resonance sub-system 398305 may generate first Q shifted signal 398060 and/or second Q shifted signal 398070 based on LO signal 398010 and/or LO signal 398020, respectively. For example, second Q shifted signal 398070 may be out of phase from first Q shifted signal 398060. In some demonstrative aspects, controllable resonance sub-system 398305 may controllably generate first Q shifted signal 398060 and/or second Q shifted signal 398070, for example, according to a control signal 398080, e.g., as described below. In some demonstrative aspects, control signal 38080 may be provided, for example, by controller 398800, for example, a baseband controller and/or any other controller. In some demonstrative aspects, control signal 398080 may, for example, control controllable resonance sub-system 398305 to shift the phase of first Q shifted signal 38060 and/or second Q shifted signal 398070. For example, control signal 398080 may have, for example, 7 bit CAPDAC control and/or any other control data. In some demonstrative aspects, implementing a 20 GHz ILO with a controllable resonance sub-system, e.g., resonance sub-system 398205 and/or resonance sub-system 398305, e.g., the LC block, which may be controlled, for example, according to 7-bit CAPDAC control and/or any other control scheme, may provide additional and/or improved control on phase shift tuning, for example, compared to a passive phase shifter. Additionally or alternatively, the active nature of the ILOs 398200 and/or 398300 may guarantee more gain, for example, compared to the passive phase shifter. In some demonstrative aspects, quadrature LO generator 398000 may include a tripler 398400, which may be configured to triple a phase and/or frequency of first I shifted signal 398030 and/or second I shifted signal 398040, e.g., as described below. For example, tripler 398400 may receive first I shifted signal 398030, for example, through a series load 398270 and capacitor 398280, and may triple the phase and/or the frequency of first I shifted signal 398030. For example, tripler 398400 may receive second I shifted signal 398040, for example, through a series load 398275 and capacitor 398285, and may triple a phase and/or frequency of second I shifted signal 398040. In some demonstrative aspects, tripler 398400 may include, for example, a transistor 398430 and a transistor 398450, which may be coupled to a current source 398470, e.g., in a common source arrangement. For example, current source 398470 may provide a predefined current, for example, 1.2 milliampere (mA), or any other current, to sources of transistors 398430 and 398450, if desired. In some demonstrative aspects, a transistor 398440 may be configured to provide first I shifted signal 398030 at a drain of transistor 398430. In some demonstrative aspects, a transistor 398460 may be configured to provide second I shifted signal 398040 at a drain of transistor 398450. In some demonstrative aspects, tripler 398400 may include, for example, a capacitor 398420 and/or a transformer 398410. For example, capacitor 398420 may be configured to be in resonance with transformer 398410, for example, when tripler 398400 may, e.g., in combination with transistor 398430 and transistor 398450, triple the phases and amplitudes of first I shifted signal 398030 and/or second I shifted signal 398040. In some demonstrative aspects, transistors 398430, 398440, 398450 and 398460 may include FETs, BJTs, and/or any other type of transistors. In some demonstrative aspects, tripler 398400 may provide a tripled positive I signal and a tripled negative I signal to a mixer 398700. In some demonstrative aspects, quadrature LO generator 398000 may include a tripler 398500, which may be configured to triple a phase and/or frequency of first Q shifted signal 398060 and/or second I shifted signal 398070, e.g., as described below. For example, tripler 398500 may receive first Q shifted signal 398060, for example, through a series load 398375 and capacitor 398385, and may triple the phase and/or the frequency of first Q signal shifted 398060. For example, tripler 398500 may receive second Q shifted signal 398070, for example, through a series load 398375 and capacitor 398385, and may triple a phase and/or frequency of second Q shifted signal 398070. In some demonstrative aspects, tripler 398500 may include, for example, a transistor 398530 and a transistor 398550 in a common source arrangement, which may be coupled to a current source 398570. For example, current source 398470 may provide a predetermined current, for example, 1.2 mA, or any other current, to sources of transistors 398430 and 398450, if desired. In some demonstrative aspects, transistor 398540 may be configured to provide first Q shifted signal 398060 to a drain of transistor 398530 In some demonstrative aspects, a transistor 398560 may be configured to provide second Q shifted signal 398070 to a drain of transistor 398550. In some demonstrative aspects, tripler 398500 may include, for example, a capacitor 398520 and/or a transformer 398510. For example, capacitor 398520 may be configured to be in resonance with transformer 398510. For example, tripler 398400 may, e.g., in combination with transistor 398430 and transistor 398450, triple the phases and amplitudes of first Q shifted signal 398060 and/or second Q shifted signal 398070. In some demonstrative aspects, transistors 398530, 398540, 398550 and 398560 may include FETs, BJTs, and/or any other type of transistors. In some demonstrative aspects, tripler 398500 may provide a tripled positive Q signal and a tripled negative Q signal to a mixer 398600. In some demonstrative aspects, a quadrature LO generator, e.g., quadrature LO generator 398000, implementing a parallel connection of frequency triplers, e.g., tripler 398400 and tripler 398500, may provide, for example, a wider locking range, e.g., compared to a series of frequency triplers. In some demonstrative aspects, a quadrature LO generator, e.g., quadrature LO generator 398000, which implements ILO 398200 and ILO 398300, may provide more control on phase tuning, may have less amplitude imbalance, and/or may have a wider locking range around 60 GHz, for example, compared to a passive LO generator. Reference is made to FIG. 186, which schematically illustrates a passive quadrature LO generator 399000, in accordance with some demonstrative aspects. In some demonstrative aspects, passive quadrature LO generator 399000 may be configured to shift a phase of a first LO signal 399010 and a second LO signal 399020, by a predefined phase shift, for example, a 90o phase shift or any other phase shift, e.g., as described below. In some demonstrative aspects, one or more components of passive quadrature LO generator 399000 may be implemented, for example, as part of LO distribution network, e.g., LO distribution network 397500 (FIG. 184), for example, to provide I and Q signals, for example, to a transmitter, e.g., transmitter 397300 and/or a receiver, e.g., receiver 397100 (FIG. 184). In some demonstrative aspects, one or more components, sub-systems, and/or circuits of passive quadrature LO generator 399000 may be implemented, for example, as part of a Tx IQ generator, e.g., Tx IQ generator 397510 (FIG. 184), and/or as part of an Rx IQ generator, e.g., Rx IQ generator 397520 (FIG. 184). In some demonstrative aspects, passive quadrature LO generator 399000 may be configured to generate the I and Q signals, for example, based on an LO signal 399010 and/or an LO signal 399020, which may be provided by an LO 399100, e.g., as described below. In some demonstrative aspects, LO 399100 may be configured to generate LO signal 399010 and/or LO signal 399020, e.g., as described below. In some demonstrative aspects, LO signal 399020 may be out phased from LO signal 399010. For example, LO signal 399010 may have a 20 GHz frequency and a phase of +0o, and/or LO signal 399020 may have a frequency of 20 GHz and a phase of 90o. In other aspects, other frequencies and/or other phase shifts may be used. In some demonstrative aspects, passive quadrature LO generator 399000 may include a phase shifter 399200, which may be configured to shift a phase of LO signal 399010 and/or a phase of LO signal 399020, for example, by 30o. In other aspects, phase shifter 39200 may be configured to shift the phase of LO signal 399010 and/or LO signal 399020 to any other phases, if desired. In some demonstrative aspects, phase shifter 399200 may be configured to generate, for example, a first I shifted signal 399050, e.g., a positive I shifted signal, and/or a second I shifted signal 399060, e.g., a negative I shifted signal, for example, based on first LO signal 399010. In some demonstrative aspects, phase shifter 399200 may be configured to generate, for example, a first Q shifted signal 399040, e.g., a positive Q shifted signal, and/or a second Q shifted signal 399030, e.g., negative Q shifted signal, for example, based on second LO signal 399020, e.g., as described below. In some demonstrative aspects, phase shifter 399200 may include passive inductor-resistor-capacitor (LRC) circuitry 399205, which may be configured to generate, for example, first I shifted signal 399050, second I shifted signal 398040, first Q shifted signal 399040, and/or second Q shifted signal 399030, e.g., as described below. In some demonstrative aspects, LRC circuitry 399205, may include an arrangement of an inductor 399210, e.g., with an inductance of L, an inductor 399220, e.g., with an inductance of L, a capacitor 399230, e.g., with a capacitance of C, a capacitor 399240, e.g., with a capacitance of C, a resistor 399250, e.g., with a resistance of 2R, and/or a resistor 399260, e.g., with a resistance of 2R. For example, the arrangement of LRC circuitry 399205 may be configured to, for example, generate first I shifted signal 399050, second I shifted signal 398040, first Q shifted signal 399040, and/or second Q shifted signal 399030, for example, with a predefined phase shift, e.g., a 30o phase shift or any other phase shift, e.g., as described below. In some demonstrative aspects, inductor 399210, capacitor 399240, and/or resistor 399250 may be configured to provide, for example, first I shifted signal 399050 and/or second Q shifted signal 399030, for example, based on LO signal 399010. In some demonstrative aspects, inductor 399220, capacitor 399230, and/or resistor 399260 may be configured to provide, for example, first Q shifted signal 399040 and/or second I shifted signal 399060, for example, based on LO signal 399020. In some demonstrative aspects, a phase shift applied by phase shifter 399200 may be based, for example, on a quality (Q) factor, denoted Q, which may be related to the maximum or peak energy of, for example, LRC circuitry 399025. For example, for a Q factor Q=1 a phase shift of 90o may be applied, and/or for a Q factor Q=0.25 a phase shift of 30o may be applied. For example, the phase of LO signal 399010 and/or LO signal 399020 may be configured, for example, based on the Q factor, which may be determined, for example, as follows: (8) (9) (10) where Q denotes a quality factor, L denotes an inductance, C denotes capacitance, R denotes resistance, and denotes an angular frequency. In some demonstrative aspects, an input impedance of quadrature LO generator 399000 may be configured, for example, to a 50 Ohm impedance or any other impedance, by setting the resistance R, for example, to a 50 Ohm impedance. For example, an input impedance of phase shifter 399200 may be designed for a 50 Ohm impedance or higher impedances. In some demonstrative aspects, phase shifter 399200 may include, for example, a 30° phase shifter for a 60 GHz quadrature generator with a 50 Ohm input impedance. In one example, the 30° phase shifter may achieve less than 2° phase variation over the frequency band of 48-72 GHz. For example, an amplitude imbalance between I and Q signals of phase shifter 399200 may be, for example, 0.3 dB at the input of the triplers, e.g., as described below. In some demonstrative aspects, passive quadrature LO generator 399000 may include a tripler 399300, which may be configured to triple the phase and/or frequency of second Q shifted signal 399030 and first Q shifted signal 399040, e.g., as described below. For example, tripler 399300 may receive first Q shifted signal 399040 at a gate of transistor 399370, and second Q shifted signal 399030to a gate of transistor 399360. In some demonstrative aspects, transistor 399360 may be configured to oscillate, for example, according to second Q shifted signal 399030. In some demonstrative aspects, transistor 399370 may be configured to oscillate, for example, according to first Q shifted signal 399040. In some demonstrative aspects, tripler 399300 may include a transistor 399330, which may be configured to receive second Q shifted signal 399030 from transistor 399360, and to triple the phase and the frequency of second Q shifted signal 399030. In some demonstrative aspects, tripler 399300 may include a transistor 399350, which may be configured to receive first Q shifted signal 399040, and to triple the phase and the frequency of first Q shifted signal 399040. In some demonstrative aspects, tripler 399300 may include a transformer 399310, which may be configured to be in resonance with a capacitor 399320 at a frequency of, for example, 60 GHz, and a phase of, for example, 90o. In other aspects, the resonance frequency may be set to any other frequency. For example, transistor 399370 and/or transistor 399350 may triple the phase and frequency of first Q shifted signal 399040; and/or transistor 399360 and/or transistor 399330 may triple the phase and frequency second Q shifted signal 399030, according to the resonance frequency. In some demonstrative aspects, tripler 399300 may include imbalance and amplitude circuitry 399390, which may be configured to balance between amplitudes of second Q shifted signal 399030 and first I shifted signal 399050, e.g., as described below. In some demonstrative aspects, imbalance and amplitude circuitry 399390 may include a transistor 399340, e.g., a coupling transistor M5 or any other transistor, which may be configured to balance the phase and amplitude imbalance between second Q shifted signal 399030 and first I shifted signal 399050. In some demonstrative aspects, tripler circuitry 399300 may include imbalance and amplitude circuitry 399395, which may be configured to balance between amplitudes of first Q shifted signal 399040 and second I shifted signal 399060, e.g., as described below. In some demonstrative aspects, imbalance and amplitude circuitry 399395 may include a transistor 399380, e.g., coupling transistor M6 or any other transistor, which may be configured to balance the phase and amplitude imbalance between first Q shifted signal 399040 and second I shifted signal 399060 In some demonstrative aspects, transistors 399330, 399340, 399350, 399360, 399380 and/or 399390 may include FETs, BJTs, and/or any other type of transistor. In some demonstrative aspects, IQ generator 399000 may include a mixer 399500, which may be configured to mix a first tripled Q signal 399070, e.g., a positive tripled Q signal, with a second tripled Q signal 399075, e.g., negative tripled Q signal, to provide, for example, a Q shifted signal 399510. In some demonstrative aspects, passive quadrature LO generator 399000 may include a tripler 399400, which may be configured to triple phase and/or frequency of first I shifted signal 399050 and second I shifted signal 399060, e.g., as described below. For example, tripler 399400 may receive first I shifted signal 399050 at a gate of transistor 399460, and second I shifted signal 399060 to a gate of transistor 399470. In some demonstrative aspects, transistor 399460 may be configured to oscillate, for example, according to first I shifted signal 399050. In some demonstrative aspects, transistor 399470 may be configured to oscillate, for example, according to second I shifted signal 399060. In some demonstrative aspects, tripler 399400 may include a transistor 399430, which may be configured to receive first I shifted signal 399050 from transistor 399460, and to triple the phase and the frequency of first I shifted signal 399050. In some demonstrative aspects, tripler 399400 may include a transistor 399450, which may be configured to receive second I shifted signal 399060, and to triple the phase and the frequency of second I shifted signal 399060. In some demonstrative aspects, tripler 399400 may include a transformer 399410, which may be configured to be in resonance with a capacitor 399420 at a frequency of, for example, 60 GHz, and a phase of, for example, 90o, e.g., as described below. In some other aspects, the resonance frequency may be set to any other frequency. For example, transistor 399460 and/or transistor 399470 may triple the phase and frequency of first I shifted signal 399050 and/or second I shifted signal 399060, according to the resonance frequency. In some demonstrative aspects, tripler 399400 may include imbalance and amplitude circuitry 399490, which may be configured to balance between amplitudes of second Q shifted signal 399030 and first I shifted signal 399050, e.g., as described below. In some demonstrative aspects, imbalance and amplitude circuitry 399490 may include a transistor 399440, e.g., coupling transistor M5 or any other transistor, which may be configured to balance the phase and amplitude imbalance between second Q shifted signal 399030 and first I shifted signal 399050. In some demonstrative aspects, tripler circuitry 399400 may include imbalance and amplitude circuitry 399495, which may be configured to balance between amplitudes of first Q shifted signal 399040 and second I shifted signal 399060, e.g., as described below. In some demonstrative aspects, imbalance and amplitude circuitry 399495 may include a transistor 399480, e.g., coupling transistor M6 or any other transistor, which may be configured to balance the phase and amplitude imbalance between first Q shifted signal 399040 with second I shifted signal 399060 In some demonstrative aspects, transistors 399430, 399440, 399450, 399460, 399480 and 399490 may include FETs, BJTs, and/or any other type of transistor. In some demonstrative aspects, IQ generator 399000 may include a mixer 399600, which may be configured to mix a first tripled I signal 399085, e.g., a positive tripled I signal, with a second tripled I signal 399080, e.g., negative tripled I signal to provide, for example, an I shifted signal 399610. Advantageously, triplers 399300 and 399400 may provide substantially equal amplitudes for I and Q signals at the output of triplers 399300 and 399400. Referring back to FIG. 4, in some demonstrative aspects, RF circuitry 425 may be configured according to a radio architecture, which may include at least one dual channel wideband amplifier, which may be configured to an RF signal from a first channel with an RF signal from a second channel into a wideband RF signal, e.g., as described below. In some demonstrative aspects, a radio architecture may include, for example, a wideband transceiver, which may be configured to support multiple channels, for example, to support simultaneous communication over two or more channels, for example, according to one or more channel bonding and/or channel aggregation techniques, e.g., as described below. In some demonstrative aspects, a wideband transceiver may be configured to transmit RF signals over one or more wireless channels. For example, a wireless medium may be defined with respect to a frequency band, for example, a 60 GHz band, a 2.4 GHz band, a 5 GHz band, or the like. In some demonstrative aspects, the frequency band may be divided into one or more channels having a predefined channel bandwidth, for example, 20 Mega Hertz (MHz) or 40 MHz, e.g., in a 2.4 GHz or 5 GHz band, 2.16 GHz, 4.32 GHz, 6.48 GHz or 8.64 GHz, e.g., in a 60 GHz band, and/or any other bandwidth, e.g., as described below. In some demonstrative aspects, one or more channel bonding and/or channel aggregation techniques may be used, for example, to provide a wider channel bandwidth. In some demonstrative aspects, for example, in a 2.4 GHz or 5 GHz frequency band, channel bonding may increase data transportation by bonding and/or combining, for example, two 20 MHz channels into a 40 MHz channel, two 40 MHz channels into an 80 MHz channel, two 80 MHz channels into a 160 MHz channel, and/or any other number of channels of any other channel bandwidth. In some demonstrative aspects, for example, in a Directional Multi Gigabit (DMG) frequency band above a channel frequency of 45 GHz, e.g., a 60 GHz frequency band, one or more mechanisms may be implemented, for example, to support communication over a channel band width (BW) (also referred to as a “wide channel”, an “EDMG channel”, or a “bonded channel”) including two or more channels, e.g., two or more 2.16 GHz channels. In some demonstrative aspects, the channel bonding mechanisms may include, for example, a mechanism and/or an operation whereby two or more channels, e.g., 2.16 GHz channels, can be combined, e.g., for a higher bandwidth of packet transmission, for example, to enable achieving higher data rates, e.g., when compared to transmissions over a single channel. Some demonstrative aspects are described herein with respect to communication over a channel BW including two or more 2.16 GHz channels, however other aspects may be implemented with respect to communications over a channel bandwidth, e.g., a “wide” channel, including or formed by any other number of two or more channels, for example, an aggregated channel including an aggregation of two or more channels. In some demonstrative aspects, one or more channel bonding mechanisms may be implemented, for example, to support an increased channel bandwidth, for example, a channel BW of 4.32 GHz, a channel BW of 6.48 GHz, a channel BW of 8.64 GHz, and/or any other additional or alternative channel BW. In some demonstrative aspects, a wideband transceiver may be configured to support communication over two or more different channels, for example, with two or more different networks. In one example, some wireless networks may be configured to occupy a first channel bandwidth, for example, a 20 MHz channel bandwidth, and/or some other wireless networks may be configured to occupy a second channel bandwidth, for example, a 40 MHz channel bandwidth, or another wider channel bandwidth. In another example, some wireless networks may be configured to occupy a first channel bandwidth, for example, a 2.16 GHz channel bandwidth, and/or some other wireless networks may be configured to occupy a second channel bandwidth, for example, a 4.32 GHz channel bandwidth, or another wider channel bandwidth. In some demonstrative aspects, it may not be efficient to implement a wideband transmitter including one or more amplifiers, e.g., with low-Q matching networks, which may be configured, for example, to achieve a flat frequency response, and thus may draw more power to compensate for power losses. For example, when working in a single channel, the amplifiers may be power inefficient, for example, since a portion of the bandwidth may not be used. In some demonstrative aspects, a wideband transmitter, which may be configured for transmission over a wideband bandwidth, may include a wideband PA, which may be configured to amplify signals to be transmitted over two or more different bandwidths in a wideband bandwidth, e.g., as described below. In some demonstrative aspects, the wideband PA may include two or more PAs, which may be configured to amplify signals to be transmitted in two or more respective different bandwidths within the wideband bandwidth, e.g., as described below. In some demonstrative aspects, the wideband PA may be configured to utilize the two or more PAs, e.g., in combination, to amplify wideband signals to be transmitted over the wideband bandwidth including the two or more bandwidths, e.g., as described below. For example, the two or more PAs may be configured to generate a flat high gain wideband response, e.g., when transmitting a wideband RF signal. In some demonstrative aspects, the wideband PA may be configured to selectively utilize only some of the two or more PAs to amplify signals to be transmitted over a bandwidth, which is narrower than the wideband bandwidth, e.g., as described below. In some demonstrative aspects, implementing a wideband PA including two or more PAs, e.g., as described herein, may allow, for example, reducing an overall power consumption of the wideband PA, for example, when at least one PA of the PAs is switched off, and at least one other PA is used to transmit RF signals over a portion of the wideband frequency channel. In some demonstrative aspects, the wideband PA may include a selective network power combiner to selectively couple input RF signals to one or more of the PAs, and/or a selective network power splitter to selectively couple output RF signals from one or more of the PAs, e.g., as described below. In some demonstrative aspects, the selective network combiner may include, or may be implemented by, a transformer (“combiner transformer”), and/or the selective network splitter may include, or may be implemented by, a transformer (“splitter transformer”), e.g., as described below. In other aspects, the selective network combiner may be implemented by any other combiner, and/or the selective network splitter may be implemented by any other splitter. In some demonstrative aspects, the splitter transformer may include two or more sections to selectively couple the input RF signals to the two or more PAs, respectively; and/or the combiner transformer may include two or more sections to selectively couple the output RF signals from the two or more PAs, respectively, e.g., as described below. In some demonstrative aspects, a section of the combiner transformer may be configured to have a physical structure and/or size, which may be based on an operating frequency and/or a bandwidth of a respective PA to be coupled to the section, e.g., as described below. In some demonstrative aspects, a section of the splitter transformer may be configured to have a physical structure and/or size, which may be based on an operating frequency and/or a bandwidth of a respective PA to be coupled by the section, e.g., as described below. In some demonstrative aspects, for example, a size of a section of a transformer, e.g., the section of the combiner transformer and/or the section of the splitter transformer, may be configured to be proportional to a frequency of the PA to be coupled by the section. For example, a first section of the transformer, e.g., a first section of the combiner transformer and/or a first section of the splitter transformer, may have a first size configured for a first frequency of a first PA; and/or a second section of the transformer, e.g., a second section of the combiner transformer and/or a second section of the splitter transformer, may have a second size configured for a second frequency of a second PA. For example, the second size may be larger than the first size, e.g., when the second frequency is higher than the first frequency. In some demonstrative aspects, implementing different sizes for the different sections of the splitter transformer and/or the combiner transformer, may allow for example, reducing a chip area of the wideband PA, e.g., as described below. In some demonstrative aspects, implementing the wideband PA with the plurality of PAs, e.g., as described herein, may provide one or more benefits and/or solve one or more technical problems, for example, by achieving a reduced power consumption, increasing a linearity, and/or increasing efficiency, for example, by allowing selective switching of one or more PAs of the plurality of PAs, for example, based on a bandwidth to be utilized, e.g., as described below. In some demonstrative aspects, the wideband PA may be included as part of, and/or may perform one or more operations and/or functionalities of, radio chain circuitry, e.g., as part of sub-system 1035 (FIG. 10), and/or any other sub-system and/or element, if desired. Reference is made to FIG. 187, which schematically illustrates a block diagram of a transmitter 400000, in accordance with to some demonstrative aspects. In some demonstrative aspects, transmitter 400000 may be configured to transmit wideband RF signals and/or high frequency RF signals, for example, in a 60 GHz frequency band and/or any other frequency band, e.g., as described below. In some demonstrative aspects, transmitter 400000 may be operably coupled to, and/or may include, for example, one or more antennas 400100. For example, one or more antennas 400100 may include a phased-array antenna, a dipole antenna, an internal antenna, or the like. In other aspects, other different types of antennas may be used. In some demonstrative aspects, transmitter 400000 may include a wideband amplifier 400200, which may be configured to amplify wideband RF signals, which may be transmitted, for example, via one or more of antennas 400100, e.g., as described below. In some demonstrative aspects, transmitter 400000 may include baseband circuitry 400300, which may be configured to generate an IF input signal 400310. In some demonstrative aspects, transmitter 400000 may include RF circuitry 400400, which may be configured to generate, for example, an RF input signal 400410, for example, by upconverting IF input signal 400310 into RF input signal 400410. For example, RF input signal 400410 may be configured according to a frequency bandwidth of a channel to be used for transmission. In some demonstrative aspects, baseband circuitry 400300 may be operably coupled to RF circuitry 400400, for example, by an RF cable 400500. For example, RF cable 400500 may include a coax cable or the like. In other aspects, other types of RF cable, connectors and/or interfaces may be used. In other aspects, any other additional or alternative elements and/or sub-systems may be implemented to couple between baseband circuitry 400300 and RF circuitry 400400. In some demonstrative aspects, for example, transmitter 400000 may include one or more switches to operably couple between baseband 400300 and a plurality of RF circuitry elements 400400, e.g., as described below with reference to FIG. 404. In some demonstrative aspects, wideband amplifier 400200 may be configured to amplify RF input signal 400410, e.g., as described below. In some demonstrative aspects, wideband amplifier 400200 may include, for example, a 60 GHz amplifier configured to amplify RF signals 400410 in a 60 GHz frequency band, e.g., as described below. In other aspects, wideband amplifier 400200 may be configured for any other additional or alternative frequency bands. In some demonstrative aspects, wideband amplifier 400200 may be configured, for example, to amplify RF input signal 400410 over a wideband frequency, for example, by splitting the RF input signal 400410 into a high band frequency and a low band frequency, amplifying the high band frequency by a high band amplifier, amplifying the low band frequency by a low band amplifier, and combining a high band amplified signal with a low band amplified signal into a wideband amplified signal, e.g., as described below. In some demonstrative aspects, wideband amplifier circuitry 400200 may include a splitter 400210, which may be configured to split RF input signal 400410 into a plurality of signals over a respective plurality of frequency bands. For example, the plurality of signals may include at least first and second signals over first and second respective frequency bands, e.g., as described below. For example, splitter 400210 may be configured to split RF input signal 400410 into, for example, a high frequency band signal 400220 over a high frequency band, and/or a low frequency band signal 400230 over a low frequency band, e.g., as described below. In some demonstrative aspects, the high frequency band may include, for example, a frequency band including one or more first channels of a 5G frequency band, and/or the low frequency band may include, for example, a frequency band including one or more second channels of the 5G frequency band. In one example, the one or more first channels and/or the one or more second channels may include one or more 500 MHz channels and/or any other additional or alternative channels. In one example, the 5G frequency band may include, for example, a frequency band of 37-43.5 GHz, a frequency band of 24.5-39.5 GHz or any other frequency band. In other aspects, any other additional or alternative frequency bands may be implemented. Some demonstrative aspects are described herein with respect to a wideband amplifier implementing two frequency bands, e.g., the high frequency band and/or the low frequency band. In other aspects, the wideband amplifier may implement any other number of frequency bands, e.g., at least three frequency bands. In some demonstrative aspects, splitter 400210 may include, for example, a resistive splitter, a hybrid splitter, a transistor implemented splitter, a Wilkinson splitter and/or any other type of splitter. In some demonstrative aspects, splitter 400210 may include, for example, a transformer 400215, which may be configured to receive, for example, RF input signal 400410, at a first section 400218 of transformer 400215, to provide, by a second section 400212 of transformer 400215, for example, low frequency band signal 400230 to a low band amplifier 400250, and to match an impedance between, for example, second section 400212 of transformer 400215 and low band amplifier 400250, e.g., as described below. For example, transformer 400215 may be configured to match, for example, a 50 Ohm impedance, between second section 400212 and low band amplifier 400250. In other aspects, the impedance between second section 400212 and low band amplifier 400250 may include any other impedance value. In some demonstrative aspects, transformer 400215 may be configured to provide, for example, by a third section 400214 of transformer 400215, high frequency band signal 400220 to a high band amplifier 40240, and to match impedance between, for example, third section 400214 of transformer 400215 and high band amplifier 400240. For example, transformer 400215 may be configured to match, for example, a 50 Ohm impedance, between third section 400214 and high band amplifier 400240. In other aspects, the impedance between third section 400214 and high band amplifier 400240 may include any other impedance value. In some demonstrative aspects, splitter 400210 may include, for example, first circuitry 400211 to filter low frequency band signal 400230 from RF input signal 400410, and, for example, second circuitry 400213 to filter high frequency band signal 400220 from RF input signal 400410, e.g., as described below. In some demonstrative aspects, first circuitry 400211 may be implemented by, for example, second section 400212 of transformer 400215 and at least part of first section 400218 of transformer 400215, and/or second circuitry 400213 may be implemented, for example, by third section 400214 of transformer 400214 and at least part of first section 400218 of transformer 400215. In other aspects, first circuitry 400211 and/or second circuitry 400213 may be implemented by any other additional or alternative elements. For example, first circuitry 400211 and/or second circuitry 400213 may be implemented, for example, by a plurality of transistors, an integrated circuit, hybrid circuitry, and/or any other components. In some demonstrative aspects, high band amplifier 400240 may be configured to amplify, for example, high frequency band signal 400220, and may provide a first amplified signal, e.g., a high band amplified signal 400245, e.g., as described below. In some demonstrative aspects, high band amplifier 400240 may include an outphasing amplifier, e.g., as described above with reference to FIG. 177, a Doherty power amplifier, e.g., as described above with reference to FIG. 174, a digital power amplifier, e.g., as described above with reference to FIG. 167, and/or any other amplifier. In some demonstrative aspects, low band amplifier 400250 may be configured to amplify, for example, low frequency band signal 400230, and may provide a second amplified signal, e.g., a low band amplified signal 400255, e.g., as described below. In some demonstrative aspects, low band amplifier 400250 may include an outphasing amplifier, e.g., as described above with reference to FIG. 177, a Doherty power amplifier, e.g., as described above with reference to FIG. 174, a digital power amplifier, e.g., as described above with reference to FIG. 167, and/or any other amplifier. In some demonstrative aspects, wideband amplifier 400200 may include a combiner 400260, which may be configured to combine, for example, a first amplified signal, e.g., a high band amplified signal 400245, and a second amplified signal, e.g., a low band amplified signal 400255, into, for example, an amplified RF signal 400270, e.g., as described below. In some demonstrative aspects, combiner 400260 may include a resistive combiner, a hybrid combiner, a transistor implemented combiner, a Wilkinson combiner, and/or any other type of combiner. In some demonstrative aspects, combiner 400260 may include, for example, a transformer 400265, which may be configured to receive first (“high band”) amplified signal 400245 from high band amplifier 400240, at a first section 400262 of transformer 400265, and to match an impedance, for example, a 50 Ohm impedance, between first section 400262 of transformer 400265 and high band amplifier 400240, e.g., as described below. In other aspects, the impedance between, for example, first section 400245 and high band amplifier 400240 may include any other impedance value. In some demonstrative aspects, transformer 400265 may be configured to receive second (“Low band”) amplified signal 400255 from low band amplifier 400250, at a second section 400264 of transformer 400265, and to match an impedance, for example, a 50 Ohm impedance, between second section 400264 of transformer 400265 and low band amplifier 400250, e.g., as described below. In other aspects, the impedance between second section 400264 and low band amplifier 400250 may include any other impedance value. In some demonstrative aspects, transformer 400265 may include, for example, a third section 400267 to combine first amplified signal 400245 from the first section 400262 of transformer 400265 with second amplified signal 400255 from second section 400264 of transformer 400265 into amplified RF signal 400270. In some demonstrative aspects, third section 400267 may be configured to match, for example, a 50 Ohm impedance, between low band amplifier 400250 and, for example, one or more antennas 400100, and between high band amplifier 400240 and one or more antennas 400100. In other aspects, the impedance between third section 400267 and one or more antennas 400100 may include any other impedance value. In some demonstrative aspects, first section 400262 and second section 400264 may have, for example, different physical sizes, e.g., as described below. In some demonstrative aspects, a section of transformer 400265 may be configured to have a physical structure and/or size, which may be based on an operating frequency and/or a bandwidth of a respective PA to be coupled by the section. For example, a physical size of first section 400262 of the transformer 400265 may be larger than a physical size of second section 400264 of transformer 400265. In some demonstrative aspects, wideband amplifier circuitry 400200 may include a first switch 400270, which may be configured to activate low band amplifier 400250, for example, when RF input signal 400410 is at least over a first frequency band, e.g., including the low frequency band to be amplified by low band amplifier 400250, e.g., as described below. In some demonstrative aspects, wideband amplifier circuitry 400200 may include a second switch 400280, which may be configured to activate high band amplifier 400240, for example, when RF input signal 400410 is at least over a second frequency band, e.g., including the high frequency band to be amplified by high band amplifier 400240, e.g., as described below. In some demonstrative aspects, switch 400270 may be configured to deactivate low band amplifier 400250, for example, when RF input signal 400410 is not at least partially over the first frequency band, and/or switch 400270 may be configured to deactivate low band amplifier 400250, for example, when RF input signal 400410 at least partially outside of the second frequency band, e.g., as described below. In some demonstrative aspects, switch 400270 and/or switch 400280 may be controllably activated and/or deactivated, for example, by baseband circuitry 40310, for example, based on a frequency bands of RF signal 400410. Reference is made to FIG. 188, which schematically illustrates a band plan 401000 of a plurality of channels corresponding to a plurality of channel bandwidths, which may be implemented, in accordance with some demonstrative aspects. In some demonstrative aspects, a wideband amplifier, e.g., wideband amplifier 400200 (FIG. 187), may be configured to transmit RF signals over one or more channel bandwidths of the plurality of channel bandwidths according to the band plan of FIG. 188. In some demonstrative aspects, band plan 401000 may include, for example, a plurality of 2.16 GHz channels 401400, for example, at a frequency range from 57.24 GHz to 65.88 GHz, e.g., according to an IEEE 802.11-2016 Specification. For example, as shown in FIG. 188, band plan 401000 may include four 2.16 GHz channels, denoted as #1, #2, #3, and #4. In some demonstrative aspects, a wideband amplifier, e.g., wideband amplifier 400200 (FIG. 187), may be configured to transmit RF signals over one or more wide channel bandwidths, which may be formed, for example, by two or more of channels 401400, e.g., as described below. In some demonstrative aspects, a channel bandwidth 401100, for example, at a frequency range from 57.24 GHz to 65.88 GHz, may include, for example, an 8.64 GHz frequency bandwidth. For example, channel bandwidth 401100 may be split, for example, between low band amplifier 400250 (FIG. 187) and high band amplifier 400240 (FIG. 187), e.g., as described above. For example, low band amplifier 400250 (FIG. 187) may be configured, for example, for a first 4.32 GHz channel, e.g., channel #9 in FIG. 188, and high band amplifier 400250 (FIG. 187) may be configured, for example, for a second 4.32 GHz channel, e.g., channel #11 in FIG. 188. In some demonstrative aspects, wideband amplifier 400200 (FIG. 187) may include four amplifiers, and, for example, each channel of the four channels 401400 forming channel bandwidth 401100 may be provided to another respective amplifier of the four amplifiers, according to the frequency band of the channel and the frequency band of the amplifier. In some demonstrative aspects, for example, at a frequency range from 57.24 GHz to 63.72 GHz, a channel bandwidth 401200 may include, for example, a bandwidth 6.48 GHz. For example, channel bandwidth 401200 may be split, for example, between low band amplifier 400250 (FIG. 187) and high band amplifier 400240 (FIG. 187), e.g., as described above. In one example, low band amplifier 400250 (FIG. 187) may be configured, for example, for a first 2.16 GHz channel, e.g., channel #1 in FIG. 188, and high band amplifier 400240 (FIG. 187) may be configured, for example, for a 4.32 GHz bandwidth including channel #2 and channel #3 in Fig 401. In another example, low band amplifier 400250 (FIG. 187) may be configured, for example, for a 4.32 GHz channel, e.g., channel #9 in FIG. 188, and high band amplifier 400240 (FIG. 187) may be configured, for example, for a 2.16 GHz channel, e.g., channel #4 in FIG. 188. In some demonstrative aspects, for example, at a frequency range from 57.24 GHz to 65.88 GHz, a channel bandwidth 401300 may include, for example, 4.32 GHz bandwidth, and may include, for example, two channels, e.g., a low channel band from 57.24 GHz to 61.56 GHz, and a high channel band from, e.g., 61.56 GHz to 65.88 GHz. For example, the low channel band may be provided to low band amplifier 400250 (FIG. 187), and the high channel band may be provided to high band amplifier 400240 (FIG. 187), e.g., as described above. In one example, low band amplifier 400250 (FIG. 187) may be configured, for example, for a first 2.16 GHz channel, e.g., channel #1 in FIG. 188, and high band amplifier 400250 (FIG. 187) may be configured, for example, for a second 2.16 GHz channel, e.g., channel #2 in FIG. 188. In another example, low band amplifier 400250 (FIG. 187) may be configured, for example, for a third 2.16 GHz channel, e.g., channel #3 in FIG. 188, and high band amplifier 400250 (FIG. 187) may be configured, for example, for a fourth 2.16 GHz channel, e.g., channel #4 in FIG. 188. Reference is made to FIG. 189, which schematically illustrates a graph 402000 depicting a gain response of a low band amplifier and a high band amplifier, in accordance with some demonstrative aspects. In some aspects, the amplifier circuitry described herein can be incorporated in one or more circuits (e.g., radio chain circuitry 372) within the RF circuitry 325 (FIG. 3D) of mmWave communication circuitry 300 shown in FIG. 3A, although the amplifier circuitry is not limited to such. In some demonstrative aspects, wideband amplifier 400200 (FIG. 187) may include low band amplifier 400250 (FIG. 187) having a gain response 402100, and/or high band amplifier 400240 (FIG. 187) having a gain response 402200. For example, a combination of low band amplifier 400250 (FIG. 187) having gain response 402100 with high band amplifier 400240 (FIG. 187) having gain response 402200, may result, for example, in a wideband amplifier, e.g., wideband amplifier 400200 (FIG. 187), having a flat gain response. Reference is made to FIG. 190, which schematically illustrates a transformer 403000, in accordance with some demonstrative aspects. In some demonstrative aspects, transformer 403000 may be included as part of, and/or may perform one or more operations and/or functionalities of, a combiner, e.g., as part of transformer 400265 (FIG. 187), and/or a splitter, e.g., as part of transformer 400215 (FIG. 187), and/or any other sub-system and/or element, if desired. In some aspects, the transformers described herein can be incorporated in one or more circuits (e.g., radio chain circuitry 372) within the RF circuitry 325 (FIG. 3D) of mmWave communication circuitry 300 shown in FIG. 3A, although the transformers are not limited to such. In some demonstrative aspects, transformer 403000 may include, for example, a low band section 403100, which may be configured to receive and/or output low band frequencies by input/output ports 403400, e.g., as described below. In some demonstrative aspects, transformer 403000 may include, for example, a high band section 403200, which may be configured to receive and/or output high band frequencies by input/output ports 403300, e.g., as described below. In some demonstrative aspects, transformer 403000 may include, for example, a common section 403600, which may be configured to receive an RF signal and to output a combined RF signal at input/output ports 403500, e.g., as described below. In some demonstrative aspects, transformer 403000 may be configured to operate as, for example, a combiner and/or as a splitter, e.g., as described below. In some demonstrative aspects, for example, when operating as a combiner, transformer 403000 may receive a low band frequency signal at input port 403400 of low band section 403100, may receive, for example, a high band frequency signal at input port 403300 of high band section 403200, and may output, for example, a combined signal at output port 403500 of common section 403600. In some demonstrative aspects, for example, when operating as a splitter, transformer 403000 may receive, for example, an input RF signal at input port 403500 of common section 403600, may output, for example, a low band frequency signal at output port 403400 of low band section 403100, and may output, for example, a high band frequency signal at output port 403300 of high band section 403200. In some demonstrative aspects, the physical size of low band section 403100 may be, for example, smaller that the physical size of high band section 403200. Referring back to FIG. 1A, in some demonstrative aspects, baseband sub-system 110 and/or RFEMs 115 may be configured according to a radio architecture, which may include a plurality of impedance matching switches, which may be configured to match impedance between a modem core, e.g., a baseband sub-system, e.g., a baseband processor, 110, to a plurality of radio cores, e.g., RFEMs 115, for example, based on a count of the plurality of radio cores, e.g., as described below. In some demonstrative aspects, a modem core may include a baseband processor and/or one or more additional or alternative processing components to generate and/or process signals for wireless communication, e.g., via one or more radio cores. In some demonstrative aspects, a transceiver may include a plurality of radio cores and an at least one modem core, e.g., as described below. In some demonstrative aspects, a 5G transceiver may include at least two main cores connected, for example, by a coax, and/or any other RF compatible connection elements and/or sub-systems, e.g., as described below. For example, the at least two main cores may include a Modem-Baseband (M-Core) and two or more Radio Front-End (R-Core). In some demonstrative aspects, the R-core may be included as part of, and/or may perform one or more operations and/or functionalities of, one or more radio chain circuitry and/or sub-systems, e.g., as part of sub-system 435 (FIG. 4), and/or any other sub-system and/or element, if desired. In some demonstrative aspects, a plurality of switches may be configured to connect the M-Core to the plurality of R-Cores. For example, the plurality of switches may be switched according to wireless device requirements, e.g., as described below. For example, the M-Core may be connected to one R-Core at a time and/or, for example, to multiple R-Cores working simultaneously, e.g., as described below. In some demonstrative aspects, at least one switch of the plurality of switches, e.g., only some of the switches or each one of the switches, may be configured to match an impedance between an R-Core of a plurality of R-Cores and the M-core, for example, based on the number of R-Cores which may be connected to the M-core, e.g., as described below. In some demonstrative aspects, matching the impedance between the R-Core of the plurality of R-Cores and the M-core, for example, based on the number of R-Cores, which may be connected to the M-core, may provide one or more benefits and/or solve one or more technical problems. For example, matching the impedance between the R-Core and the M-core based on the number of R-cores to be connected to the M-core may allow, for example, to maintain a substantially constant impedance, for example, an impedance of 50 Ohm or any other impedance, between the M-core and the R-Core, e.g., between the M-core and each of the R-cores connected to the M-core. Reference is now made to FIG. 191, which schematically illustrates a block diagram of a wireless communication apparatus 404000, in accordance with some demonstrative aspects. In some aspects, wireless communication apparatuses (e.g., transmitters, receivers, transceivers, and so forth) described herein can be incorporated in (or implemented as) one or more circuits within the mmWave communication circuitry 300 shown in FIG. 3A, although the communication apparatuses are not limited to such. In some demonstrative aspects, wireless communication apparatus 404000 may be configured to transmit and/or receive wireless RF signals, for example, over a 2.4 GHz frequency band, a 5 GHz frequency band, a 60 GHz frequency band, a frequency band of a 5G communication network, and/or on any other frequency band, e.g., as described below. In some demonstrative aspects, wireless communication apparatus 404000 may include an M-core 404300, which may be implemented, for example, as part of a baseband, e.g., as part of baseband circuitry and/or logic, and/or as part of any other additional or alternative element, sub-system and/or circuit. In some demonstrative aspects, wireless communication apparatus 404000 may include a plurality of R-Cores 404100 to be selectively coupled to M-core 404300. For example, as shown in FIG. 191, the plurality of R-Cores 404100 may include at least two R-cores, for example, an R-Core 404130 and a R-Core 404160, to be selectively coupled to M-core 404300, e.g., as described below. For example, R-Core 404130 and/or R-Core 404160 may include a radio front end. For example, the radio front end may include one or more circuits, components, and/or sub-systems to receive and/or transmit RF signals, such as, for example, a power amplifier (PA), a low noise amplifier (LNA), an antenna interface, and/or the like. In one example, R-Core 404130 and/or R-Core 404160 may include one or more elements of, and/or perform one or more functionalities of, radio front end module 115 (FIG. 1). In some demonstrative aspects, R-Core 404130 and/or R-Core 404160 may include a half-duplex radio front end, a half-duplex transceiver, or the like, e.g., as described below. In some other demonstrative aspects, R-Core 404130 and/or R-Core 404160 may include a full duplex radio. In some demonstrative aspects, wireless communication apparatus 404000 may include and/or may be operably coupled to one or more antennas, e.g., including antenna 404400 and/or antenna 404450. For example, R-Core 404130 may be operably coupled to at least one antenna 404400, and/or radio core 404160 may be operably coupled to at least one antenna 404450. In some demonstrative aspects, antennas 404400 and/or 404450 may include, for example, one or more phased-array antennas, one or more dipole antennas, and/or any other type of antenna. In some demonstrative aspects, the plurality of R-Cores 404100 may be coupled to M-core 404300 via a plurality of RF cables 404500, e.g., such that M-core 404300 may be connected to an R-Core via at least one RF cable. For example, R-Core 404130 may be coupled to M-Core 404300 via an RF cable 404530, and/or R-Core 404160 may be coupled to M-Core 404300 via an RF cable 404560, e.g., as described below. In some demonstrative aspects, RF cable 404530 and/or RF cable 404560 may include a coaxial cable. In other aspects, RF cable 404530 and/or RF cable 404560 may include any other RF computable cable. Some demonstrative aspects are described herein with respect to an architecture implementing one or more RF cables to couple an M-core to a plurality of R-cores. However, in other aspects any other additional or alternative connectors, cables, and/or elements may be implemented to couple the M-core to the plurality of RF cores. In some demonstrative aspects, wireless communication apparatus 404000 may include a plurality of impedance matching switches 404600 to switchably couple M-core 404300 to one or more R-Cores of the plurality of R-Cores 404100, e.g., as described below. For example, as shown in FIG. 191, the plurality of impedance matching switches 404600 may include an impedance matching switch 404630 to switchably couple M-core 404300 to R-core 404130; and/or an impedance matching switch 404630 to switchably couple M-Core 404300 to R-Core 404160, e.g., as described below. In some demonstrative aspects, as shown in FIG. 191, the plurality of impedance matching switches 404600 may include two switches, e.g., switches 404630 and 404660, to switchably couple M-core 404300 to two respective R-Cores, e.g., R-Core 404130 and R-Core 404160. In other aspects, the plurality of impedance matching switches 404600 may include any other number of switches, e.g., three or more switches, to switchably couple M-core 404300 to any other number of R-Cores, e.g., three or more respective R-Cores. In some demonstrative aspects, an impedance matching switch of the plurality of impedance matching switches 404600, e.g., impedance matching switch 404630 and/or impedance matching switch 404660, may include a first terminal to be operably coupled the M-core 404300, and a second terminal to be operably coupled to a respective R-Core of the plurality of R-Cores 404100, e.g., as described below. In some demonstrative aspects, impedance matching switch 404630 may include a first terminal 404610 to be operably coupled the M-core 404300, and a second terminal 404620 to be operably coupled to R-Core 404130, e.g., as described below. In some demonstrative aspects, impedance matching switch 404660 may include a first terminal 404670 to be operably coupled the M-core 404300, and a second terminal 404680 to be operably coupled to R-Core 404160, e.g., as described below. In some demonstrative aspects, as shown in FIG. 191, an impedance matching switch of the plurality of impedance matching switches 404600, e.g., impedance matching switch 404630 and/or impedance matching switch 404660, may include impedance matching circuitry to controllably match an impedance between an R-Core of the plurality of R-Cores 404100 and M-Core 404300, for example, based on a count of the one or more R-Cores of the plurality of R-Cores, which may be coupled to M-core 404300 by the plurality of impedance matching switches 404600, e.g., as described below. In some demonstrative aspects, impedance matching switch 404630 may include impedance matching circuitry, which may be configured to controllably match an impedance between R-Core 404130 and M-core 404300, for example, based on a count of the one or more R-Cores of the plurality of R-Cores 404100, which may be coupled to M-core 404300, by the plurality of impedance matching switches 404600, e.g., as described below. In some demonstrative aspects, impedance matching switch 404660 may include impedance matching circuitry, which may be configured to controllably match an impedance between R-Core 404160 and M-core 404300, for example, based on a count of the one or more R-Cores of the plurality of R-Cores 404100, which may be coupled to M-core 404300, by the plurality of impedance matching switches 404600, e.g., as described below. In some demonstrative aspects, the impedance matching circuitry of the impedance matching switch, e.g., the impedance matching circuitry of impedance matching switch 404660 and/or the impedance matching circuitry of impedance matching switch 404630, may be switchable between a plurality of impedance matching modes according to a control signal, which may be provided, for example, by M-core 404300, e.g., as described below. In some demonstrative aspects, the impedance matching circuitry of impedance matching switch 404630 may be switchable between a plurality of impedance matching modes, for example, according to a first control signal 404010, which may be provided by M-core 404300, e.g., as described below. In some demonstrative aspects, the impedance matching circuitry of impedance matching switch 404660 may be switchable between the plurality of impedance matching modes, for example, according to a second control signal 404020 from M-core 404300, e.g., as described below. In some demonstrative aspects, the impedance matching circuitry of the impedance matching switch, e.g., the impedance matching circuitry of impedance matching switch 404660 and/or the impedance matching circuitry of impedance matching switch 404630, may be configured to, for example, at an impedance matching mode of the plurality of impedance matching modes, match an impedance between M-core 404300 and an R-Core of the plurality of R-cores 404100 corresponding to the impedance matching switch, for example, based on a R-Core count corresponding to the impedance matching mode, e.g., as described below. In some demonstrative aspects, the impedance matching circuitry of impedance matching switch 404630 may be configured to, for example, at an impedance matching mode of the plurality of impedance matching modes, match an impedance between M-core 404300 and R-Core 404130, for example, based on a R-Core count corresponding to the impedance matching mode, e.g., as described below. In some demonstrative aspects, the impedance matching circuitry of impedance matching switch 404660 may be configured to, for example, at an impedance matching mode of the plurality of impedance matching modes, match an impedance between M-core 404300 and R-Core 404160, for example, based on a R-Core count corresponding to the impedance matching mode, e.g., as described below. In some demonstrative aspects, the plurality of impedance matching modes may include, for example, at least a first impedance matching mode, in which the impedance matching circuitry may be configured to match the impedance between the M-core 404300 and one R-Core of R-Cores 404100, e.g., R-Core 404130 or R-Core 404160; a second impedance matching mode, in which the impedance matching circuitry may be configured to match the impedance between the M-core 404300 and two R-Cores of R-Cores 404100, e.g., both R-Cores 404130 and 404160; and/or a third impedance matching mode, in which the impedance matching circuitry may be configured to match the impedance between the M-core 404300 and three R-Cores, e.g., including R-Core 404130, R-Core 404160 and another R-Core of the plurality of R-Cores 404100 (not shown in FIG. 191), e.g., as described below. In other aspects, the plurality of impedance matching modes may include one or more additional or alternative impedance matching modes to match the impedance between M-core 404300 and any other number of R-cores 404100 In some demonstrative aspects, the impedance matching circuitry of the impedance matching switch, e.g., as described above, may include a plurality of transistors, which may be configured to couple, for example, M-core 404300 to an R-Core corresponding to the impedance matching switch, e.g., as describe below. In some demonstrative aspects, an impedance matching switch of the plurality of impedance matching switches 404600, e.g., impedance matching switch 404630 and/or impedance matching switch 404660, may be configured to maintain substantially constant impedance, for example, a 50 Ohm impedance or any other impedance, between M-core 404300 and an R-Core corresponding to the impedance matching switch, for example, regardless of and/or independent of the count of the one or more R-Cores 404100 to be connected to M-core 404300. In some demonstrative aspects, impedance matching switch 404630 may be configured to maintain substantially constant impedance, for example, a 50 Ohm impedance or any other impedance, between M-core 404300 and R-Core 404130, for example, regardless of and/or independent of the count of the one or more R-Cores404100 to be connected to M-core 404300. In some demonstrative aspects, impedance matching switch 404660 may be configured to maintain substantially constant impedance, for example, a 50 Ohm impedance or any other impedance, between M-core 404300 and R-Core 404160, for example, regardless of and/or independent of the count of the one or more R-Cores 404100 to be connected to M-core 404300. Reference is made to FIG. 192, which schematically illustrates an impedance matching switch 405000, in accordance to some demonstrative aspects. In some aspects, the switches described herein can be incorporated in one or more circuits (e.g., radio chain circuitry 372) within the RF circuitry 325 (FIG. 3D) of mmWave communication circuitry 300 shown in FIG. 3A, although the switches are not limited to such. In some demonstrative aspects, impedance matching switch 405000 may be configured to match impedance between an M-core, e.g., M-core 404300 (FIG. 191), and an R-Core of a plurality of R-cores, e.g., the plurality of R-Cores 404100 (FIG. 191), for example, based on a count of the R-Cores to be connected to the M-core, e.g., as described below. In some demonstrative aspects, impedance matching switch 405000 may be included as part of, and/or may perform one or more operations and/or functionalities of, impedance matching switch 404630 and/or impedance matching switch 404660 (FIG. 191), and/or any other sub-system and/or element, if desired. In some demonstrative aspects, impedance matching switch 405000 may include impedance matching circuitry 405100 having a first terminal 405010 to couple a M-Core 405700, e.g., M-core 404300 (FIG. 191), to impedance matching circuitry 405100, and a second terminal 405020 to couple an R-Core 405800, e.g., R-Core 404130 or R-Core 404160 (FIG. 191), to impedance matching circuitry 405100. In some demonstrative aspects, impedance matching circuitry 405100 may be configured to controllably match an impedance, for example, an impedance of 50 Ohm or any other impedance, between, M-core 405700 and R-core 405800, for example, based on a count of one or more R-Cores, e.g., R-cores 404100 (FIG. 191), which may be coupled to M-core 405700. In some demonstrative aspects, impedance matching circuitry 405100 may be switchable between a plurality of impedance matching modes, for example, including a first mode (mode A), a second mode (mode B) and a third mode (mode C), e.g., according to a control signal 405030. For example, control signal 405030 may be provided by M-Core 405700. In other aspects, impedance matching circuitry 405100 may be configured to be switched between any other number of impedance matching modes, for example, based on the number of R-Cores 404100 (FIG. 191). In some demonstrative aspects, at the impedance matching mode A, for example, the M-core 405700 may be coupled to a single R-core, e.g., R-core 405800, of the plurality of R-cores, e.g., the plurality of R-cores 404110 (FIG. 191). For example, at the impedance matching mode A, the impedance matching circuitry 405100 may be configured to, for example, match an impedance, e.g., an impedance of 50 Ohm and/or any other desired impedance, between R-Core 405800 and M-core 405700, for example, when M-core 45700 is coupled only to R-core 405800. In some demonstrative aspects, at the impedance matching mode B, for example, the M-core 405700 may be coupled to two R-cores, e.g., R-core 405800 and one other R-core of the plurality of R-cores, e.g., the plurality of R-cores 404110 (FIG. 191). For example, at the impedance matching mode B, the impedance matching circuitry 405100 may be configured to, for example, match an impedance, e.g., an impedance of 50 Ohm and/or any other desired impedance, between R-Core 405800 and M-core 405700, for example, when M-core 405700 is coupled to R-core 405800 and the one other R-core. In some demonstrative aspects, at the impedance matching mode C, for example, the M-core 405700 may be coupled to four R-cores, e.g., R-core 405800 and three other R-cores of the plurality of R-cores, e.g., the plurality of R-cores 404110 (FIG. 191). For example, at the impedance matching mode C, the impedance matching circuitry 405100 may be configured to, for example, match an impedance, e.g., an impedance of 50 Ohm and/or any other desired impedance, between R-Core 405800 and M-core 405700, for example, when M-core 405700 is coupled to R-core 405800 and the two other R-cores. In some demonstrative aspects, impedance matching circuitry 405100 may include a plurality of transistors, e.g., including transistors 405200, 405300 and/or 405400, which may selectively couple M-core 405700 to R-Core 405800 via a load, e.g., an RF load, of a plurality of loads, for example, according to the impedance matching mode, e.g., as described below. In some demonstrative aspects, a first load level, e.g., a zero load, may be applied between M-core 405700 to R-Core 405800, for example, at the impedance matching mode A; a second load level, e.g., higher than the first load level, may be applied between M-core 45700 to R-Core 405800, for example, at the impedance matching mode B; and/or a third load level, e.g., higher than the second load level, may be applied between M-core 45700 to R-Core 405800, for example, at the impedance matching mode C, e.g., as described below. In some demonstrative aspects, at the impedance matching mode A, for example, transistor 45400 may be controlled, e.g., by control signal 405060, to selectively couple M-Core 405700 to R-Core 405800, e.g., without any load. In some demonstrative aspects, at the impedance matching mode B, for example, transistor 405300 may be controlled, e.g., by control signal 405040, to selectively couple M-Core 405700 to R-Core 405800, for example, via a load 405600. In some demonstrative aspects, at the impedance matching mode C, for example, transistor 405200 may be controlled, e.g., by control signal 405030, to selectively couple M-Core 405700 to R-Core 405800, for example, via a load 405500. In some demonstrative aspects, load 405500 may be, for example, higher than load 405600. In some demonstrative aspects, load 405600 may include, for example, a load of 50 Ohm, and load 405500, may include, for example, a load of 100 Ohm. In other aspects, any other load values may be used. In some demonstrative aspects, load 405500 and/or load 405600 may include, for example, a resistor-inductor-capacitor (RLC) network. In other aspects, load 405500 and/or load 405600 may include an active load, a resistance load, a capacitive load, an inductive load, or the like. In some demonstrative aspects, the RLC network may be configured to maintain a predefined impedance, for example, a 50 Ohm impedance or any other impedance, between M-core 405700 and the R-Core 405800, for example, based on a count of the R-Cores to be connected to the M-core 405700. Referring back to FIG. 4, in some demonstrative aspects, RF circuitry 425 may be configured according to a radio architecture, which may include at least one bi-directional mixer, which may be configured to upconvert an IF signal into an RF signal, at an upconversion mode of the bi-directional mixer, and to downconvert an RF signal in an IF signal, at a downconversion mode of the bi-directional mixer, e.g., as described below. In some demonstrative aspects, a transceiver architecture, which may be implemented in mm-wave applications, such as, for example, 5G of cellular systems and/or WLAN with a communication frequency of about 60 GHz, for example, WiGig, may include a first mixer, which may be configured to upconvert a Tx IF signal into a RF signal, e.g., to be transmitted at a Tx mode of the transceiver; and/or a second mixer, which may be configured to downconvert a Rx RF signal into an Rx IF signal, e.g., at an Rx mode of the transceiver. In some demonstrative aspects, it may not be advantageous in some use cases, implementations and/or scenarios to implement a transceiver architecture including separate mixers, e.g., two separate mixers, for the Tx mode and the Rx mode. In some demonstrative aspects, a transceiver architecture may implement at least one bi-directional mixer, which may be configured for both the Rx mode and the Tx mode, e.g., as described below. In some demonstrative aspects, implementing a bi-directional mixer in a transceiver architecture may provide one or more benefits and/or solve one or more technical problems. For example, the bi-directional mixer may enable to reduce transceiver chip area, for example, by implementing one or more bi-directional elements, for example, one or more bi-directional amplifiers, e.g., a bi-directional RF amplifier and/or a bi-directional IF amplifier, and/or any other additional or alternative bi-directional elements, in the transceiver chip. In some demonstrative aspects, the bi-directional mixer may include a semi-passive mixer architecture, which may be well suited, for example, even for a low supply voltage and/or a low power consumption, for example, while providing sufficient conversion gain (C.G). For example, some bi-directional mixers may include an RF stage to process RF signals. Eliminating the RF stage of the bi-directional mixer may enable to reduce temperature dependence and current consumption, which may be required, for example, in order to achieve high linearity. In some demonstrative aspects, the bi-directional mixer may be included as part of, and/or may perform one or more operations and/or functionalities of, upconversion and downconversion circuitry, e.g., as part of sub-system 415 (FIG. 4), and/or any other sub-system and/or element, if desired. In some demonstrative aspects, the bi-directional mixer may be configured to operate at an upconversion mode and/or at a downconversion mode, e.g., as described below. For example, at the upconversion mode, the bi-directional mixer may upconvert an IF signal into an RF signal, and/or at the downconversion mode, the bi-directional mixer may downconvert an RF signal into an IF signal, e.g., as described below. In some demonstrative aspect, the bi-directional mixer may include one or more switches to switch a direction of signals to be processed by the bi-directional mixer, for example, from processing signals in a first direction to processing signals in a second direction, e.g., when switching from the upconversion mode to the downconversion mode; and/or from processing signals in the second direction to processing signals in the first direction, e.g., when switching from the downconversion mode to the upconversion mode, e.g., as described below. In some demonstrative aspects, the one or more switches of the bi-directional mixer may include, for example, one or more metal-oxide-semiconductor field effect transistors (MOSFET) having a Parameterize Cell (PCell), which may include a drain channel and a source channel, e.g., as described below. In some demonstrative aspects, the drain channel and the source channel of the MOSFET may be symmetrical. For example, roles of the drain channel and the source channel may be switched, for example, such that the drain channel may be used as the source channel and/or the source channel may be used as the drain channel, e.g., as described below. In some demonstrative aspects, the bi-directional mixer may include a Gilbert cell mixer, for example, a semi-passive Gilbert cell mixer e.g., as described below. In some demonstrative aspects, the Gilbert cell mixer may be configured to, e.g., at the upconversion mode, upconvert an IF signal into an RF signal, for example, by mixing the IF signal with a LO signal, e.g., as described below. In some demonstrative aspects, the Gilbert cell mixer may be configured to, e.g., at the downconversion mode, downconvert an RF signal into an IF signal, for example, by mixing the RF signal with an LO signal, e.g., as described below. Reference is made to FIG. 193, which schematically illustrates a block diagram of a transceiver 406100, in accordance with some demonstrative aspects. In some demonstrative aspects, transceiver 406100 may be configured as a half-duplex transceiver, e.g., as described below. In some demonstrative aspects, the half-duplex transceiver, e.g., transceiver 406100, may be switched between, a Tx mode, for example, to transmit Tx signals, and, an Rx mode, for example, to receive Rx signals, e.g., as described below. In some demonstrative aspects, transceiver 406100 may include, for example, a 60 GHz transceiver, which may be configured to transmit Tx signals and to receive Rx signals, for example, at least over a 60 GHz frequency band. In some demonstrative aspects, transceiver 406100 may include a 5G cellular transceiver. In other aspects, transceiver 406100 may include any other type of transceiver and/or may be configured to communicate Tx signals and/or Rx signals over any other additional or alternative frequency band. In some demonstrative aspects, transceiver 406100 may include, or may be operably coupled to, one or more antennas 406150. For example, antennas 406150 may be configured to transmit and/or receive one or more RF signals. In some demonstrative aspects, antennas 406150 may include one or more phased-array antennas, an in-chip antenna, and/or any other type of antennas. In some demonstrative aspects, transceiver 406100 may include a baseband 406110, which may beconfigured to generate and/or process baseband signals, for example, a Tx baseband signal 406113 and/or an Rx baseband signal 406117, e.g., as described below. For example, Tx baseband signal 406113 and/or Rx baseband signal 406117 may include a differential baseband signal and/or any other type of baseband signals. In some demonstrative aspects, baseband 406110 may include a digital baseband to process digital data and/or an analog baseband to, for example, convert the digital data into analog signals. In some demonstrative aspects, transceiver 406100 may include a bi-directional mixer 406130, which may be configured to upconvert an IF signal, e.g., a Tx IF signal 406123 into a Tx RF signal, e.g., a Tx RF signal 406143, for example, at the Tx mode; and/or to downconvert an Rx RF signal, e.g., an Rx RF signal 406147, into an Rx IF signal, e.g., an Rx IF signal 406127, for example, at the Rx mode, e.g., as described below. In some demonstrative aspects, bi-directional mixer 406130 may include a differential bi-directional mixer, which may be configured to upconvert a differential IF signal into a differential RF signal, and/or to downconvert a differential RF signal into a differential IF signal, e.g., as described below. In some demonstrative aspects, bi-directional mixer 406130 may include an IF terminal 406133 to input Tx IF signal 406123, e.g., at an upconversion mode, and to output Rx IF signal 406127, e.g., at a downconversion mode, e.g., as described below. In some demonstrative aspects, bi-directional mixer 406130 may include an RF terminal 406139 to output Tx RF signal 406143, e.g., at the upconversion mode, and to input Rx RF signal 406147, e.g., at the downconversion mode, e.g., as described below. In some demonstrative aspects, transceiver 406100 may include, or may be operably coupled to, an LO 406135 to generate an LO signal 406137, e.g., as described below. For example, LO signal 406137 may have a frequency of 60 GHz, and/or any other required signal, which may be applied to bi-directional mixer 406130. For example, LO signal 406137 may be used, at the upconversion mode, to upconvert one or more IF signals, and/or, at the downconversion mode, to downconvert one or more RF signals, e.g., as described below. In one example, LO signal 406137 may include a differential signal. In some demonstrative aspects, transceiver 406100 may include one or more amplifiers to amplify Tx baseband signal 406113, Tx RF signal 406143, Rx signal 406155, and/or Rx IF signal 406127, e.g., as described below. In some demonstrative aspects, transceiver 406100 may include one or more bi-directional amplifiers to amplify Tx baseband signal 406113, Rx IF signal 406127, Tx RF signal 406143, and/or Rx signal 406155, e.g., as described below. In other aspects, at least one of the bi-directional amplifiers may be replaced by a plurality of single-direction amplifiers. In some demonstrative aspects, transceiver 406100 may include a bi-directional IF amplifier 406120, which may be configured to amplify Rx signals from baseband 406110 at the Rx mode, and/or to amplify Tx signals from bi-directional mixer 406130 at the Tx mode. For example, bi-directional IF amplifier 406120 may be configured to amplify Rx IF signal 406127, e.g., at the Rx mode, and/or to amplify Tx baseband signal 406113, e.g., at the Tx mode, e.g., as described below. In some demonstrative aspects, bi-directional IF amplifier 406120 may be configured to, e.g., at the Tx mode, amplify Tx baseband signal 406113 into Tx IF signal 406123, and/or to, e.g., at the Rx mode, amplify Rx IF signal 406127, for example, from IF terminal 406133 of bi-directional mixer 406130, into Rx baseband signal 406117. In some demonstrative aspects, bi-directional IF amplifier 406120 may include a first IF amplifier (not shown in FIG. 193) to amplify signals at the Tx mode, and a second IF amplifier (not shown in FIG. 193) to amplify signals at the Rx mode, e.g., as described below. In one example, bi-directional IF amplifier 406120 may include a Tx IF amplifier, which may be configured to, at the Tx mode, amplify Tx baseband signal 406113, from baseband 406110, into Tx IF signal 406123; and an Rx IF amplifier, which may be configured to, at the Rx mode, amplify Rx IF signal 406127 into Rx baseband signal 406117to be provided to baseband 406110. In some demonstrative aspects, bi-directional IF amplifier 406120 may include, for example, a differential bi-directional IF amplifier. For example, the differential bi-directional IF amplifier may amplify differential IF signals. For example, Rx IF signal 406127 and/or Tx baseband signal 406113 may include a differential IF signal. In some demonstrative aspects, transceiver 46100 may include a bi-directional RF amplifier 406140, which may be configured to amplify Rx signals from antennas 406150, at the Rx mode, and/or to amplify Tx signals from bi-directional mixer 406130, at the Tx mode. For example, bi-directional RF amplifier 406140 may be configured to amplify an Rx signal 406155 from antennas 406150, e.g., at the Rx mode, and/or to amplify Tx RF signal 406143, e.g., at the Tx mode, e.g., as described below. In some demonstrative aspects, bi-directional RF amplifier 406140 may be configured to, e.g., at the Tx mode, amplify Tx RF signal 406143 into Tx signal 406153, and/or to, e.g., at the Rx mode, amplify Rx RF signal 406155, for example, from one or more antennas 406150 into Rx RF signal 406147. In some demonstrative aspects, bi-directional RF amplifier 406140 may include a first RF amplifier (not shown in FIG. 193) to amplify signals at the Tx mode, and a second RF amplifier (not shown in FIG. 193) to amplify signals at the Rx mode, e.g., as described below. In one example, bi-directional RF amplifier 406140 may include the first RF amplifier (not shown in FIG. 193), e.g., a Power Amplifier (PA), which may be configured to, at the Tx mode, amplify Tx RF signal 406143, from bi-directional mixer 406130, into a Tx signal 406153; and the second RF amplifier (not shown in FIG. 193), e.g., a Low Noise Amplifier (LNA), which may be configured to, at the Rx mode, amplify Rx signal 406155 into the first RF signal, e.g., Rx RF signal 406147 to be provided to bi-directional mixer 406130. In one example, bi-directional IF amplifier 406140 may include a differential bi-directional RF amplifier to amplify a differential RF signal, e.g., differential RF signal 406155, and/or a differential Tx RF signal, e.g., a differential Tx RF signal 406143, e.g., as described below. In some demonstrative aspects, bi-directional mixer 406130 may include a first voltage terminal 406131, and a second voltage terminal 406132, which may be configured to apply one or more bias voltages to bi-directional mixer 406130, e.g., as described below. In some demonstrative aspects, bi-directional mixer 406130 may include mixing circuitry (not shown in FIG. 193), which may be configured to operate at the upconversion mode, for example, when a first bias voltage is to be applied to the first voltage terminal 406131 and a second bias voltage is to be applied to the second voltage terminal 406132, e.g., as described below. In some demonstrative aspects, the mixing circuitry of bi-directional mixer 406130 may be configured to operate at the downconversion mode, for example, when the second bias voltage is to be applied to the first voltage terminal 406131 and the first bias voltage is to be applied to the second voltage terminal 406132, e.g., as described below. In some demonstrative aspects, the second bias voltage may be lower than the first bias voltage. In some demonstrative aspects, the first bias voltage may be a positive voltage for example, a voltage in the range of 1-5 Volts or any other voltage, and/or the second bias voltage may be a zero voltage and/or a voltage close to zero. In some demonstrative aspects, the mixing circuitry of bi-directional mixer 406130 may be configured, for example, to, e.g., at the downconversion mode, downconvert a first RF signal at the RF terminal 406139, e.g., Rx RF signal 406147, into a first IF signal at the IF terminal 406133, e.g., Rx IF signal 406127, e.g., as described below. In some demonstrative aspects, the mixing circuitry of bi-directional mixer 406130 may be configured, for example, to, e.g., at the upconversion mode, upconvert a second IF signal at the IF terminal 406133, e.g., Tx IF signal 406123, into a second RF signal at the RF terminal 406139, e.g., Tx RF signal 406143, e.g., as described below. In some demonstrative aspects, the mixing circuitry of bi-directional mixer 406130 may include, for example, a Gilbert-cell (not shown in FIG. 193), which may include, for example, a plurality of transistors, which may be configured to upconvert Tx IF signal 406123 into Tx RF signal 406143, for example, at the upconversion mode, and/or to downconvert Rx RF signal 406147 into Rx IF signal 406127, for example, at the downconversion mode, e.g., as described below. In some demonstrative aspects, for example, the plurality of transistors of the Gilbert cell may include one or more field effect transistors (FETs). In some demonstrative aspects, the mixing circuitry of bi-directional mixer 406130 may include, for example, a first transformer (not shown in FIG. 193), which may be configured to couple drains of the plurality of transistors to RF terminal 406139, and to voltage terminal 406131, e.g., as described below. In some demonstrative aspects, the mixing circuitry of bi-directional mixer 406130 may include, for example, a second transformer (not shown in FIG. 193), which may be configured to couple sources of the plurality of transistors to IF terminal 406133, and to voltage terminal 406132, e.g., as described below. In some demonstrative aspects, the mixing circuitry of bi-directional mixer 406130 may include, for example, an LO terminal (not shown in FIG. 193), which may be configured to couple LO signal 406137 from LO 406135 to gates of the plurality of transistors of the Gilbert cell, e.g., as described below. In some demonstrative aspects, for example, at the upconversion mode, the second transformer may provide Tx IF signal 406123 and the second bias voltage to the sources of the plurality of transistors of the Gilbert cell. For example, the Gilbert cell may be configured to mix Tx IF signal 406123 with LO signal 406137, for example, to provide a mixed RF signal to the drains of the plurality of transistors of the Gilbert cell, e.g., as described below. In some demonstrative aspects, for example, at the upconversion mode, the first transformer may combine the mixed RF signal at the drains of the plurality of transistors into Tx RF signal 406143, e.g., as described below. In some demonstrative aspects, at the downconversion mode, the first transformer may be configured to provide Rx RF signal 406147 and the second bias voltage to the drains of the plurality of transistors. For example, the Gilbert cell may be configured to mix Rx RF signal 406147 with LO signal 406137 to provide, for example, a mixed IF signal to the sources of the plurality of transistors, e.g., as described below. In some demonstrative aspects, for example, at the downconversion mode, the second transformer may combine the mixed IF signal at the sources of the plurality of transistors into Rx IF signal 406127, e.g., as described below. In some demonstrative aspects, the mixing circuitry of bi-directional mixer 406130 may include, for example, a first switch (not shown in FIG. 193), which may be configured to, e.g., at the upconversion mode, couple the first bias voltage to voltage terminal 406131, e.g., to couple the first bias voltage to the drains of the plurality of transistors of the Gilbert cell; and to, e.g., at the downconversion mode, couple the second bias voltage to voltage terminal 406131, e.g., to couple the second bias voltage to the drains of the plurality of transistors of the Gilbert cell, e.g., as described below. In some demonstrative aspects, the mixing circuitry of bi-directional mixer 406130 may include, for example, a second switch (not shown in FIG. 193), which may be configured to, e.g., at the upconversion mode, couple the second bias voltage to voltage terminal 406132, e.g., to couple the second bias voltage to the sources of the plurality of transistors of the Gilbert cell; and to, e.g., at the downconversion mode, couple the first bias voltage to voltage terminal 406132, e.g., to couple the first bias voltage to the sources of the plurality of transistors of the Gilbert cell, e.g., as described below. In some demonstrative aspects, transceiver 406100 may include a controller, e.g., controller circuitry 406160, which may be configured to switch, for example, a direction of operation of bi-directional IF amplifier 406120, bi-directional mixer 406130 and/or bi-directional RF amplifier 406140, for example, based on the Tx mode and/or the Rx mode of transceiver 406100, e.g., as described below. In some demonstrative aspects, controller circuitry 406160 may be operably coupled to a control line 406161, which may be configured to apply the first bias voltage to voltage terminal 406131, for example, at the upconversion mode, and, to apply the second bias voltage to voltage terminal 406131, for example, at the downconversion mode, e.g., as described below. In some demonstrative aspects, controller circuitry 406160 may be operably coupled to a control line 406162, which may be configured to apply, for example, at upconversion mode, the second bias voltage to voltage terminal 406132, and, at the downconversion mode, for example, the first bias voltage to voltage terminal 406132, as described below. In some demonstrative aspects, controller circuitry 406160 may be configured to switch the direction of bi-directional mixer 406130, for example, by switching between applying the first bias voltage to voltage terminal 406131 and applying the second bias voltage to voltage terminal 406131, e.g., through control line 406161; and switching between applying the second bias voltage to voltage terminal 406132 and applying the first bias voltage to voltage terminal 406132, e.g., through a control line 406162, e.g., as described below. In some demonstrative aspects, controller circuitry 406160 may be configured to switch bi-directional mixer 406130 to the upconversion mode, for example, by applying the first bias voltage, for example, through voltage terminal 406131, to drains of the plurality of transistors of bi-directional mixer 406130, and by applying the second bias voltage for example, through voltage terminal 406132, to sources of the plurality of transistors of bi-directional mixer 406130, e.g., as described below. In some demonstrative aspects, controller circuitry 406160 may be configured to switch bi-directional mixer 406130 to the downconversion mode, for example, by applying the first bias voltage, for example, through voltage terminal 406132, to the sources of the plurality of transistors of bi-directional mixer 406130, and by applying the second bias voltage, for example, through voltage terminal 406131, to the drains of the plurality of transistors of bi-directional mixer 406130, e.g., as described below. In some demonstrative aspects, at the Tx mode, baseband 406100 may provide a baseband signal, e.g., baseband signal 406113, to the bi-directional IF amplifier, e.g., bi-directional IF amplifier 406120. For example, bi-directional IF amplifier 406120 may amplify baseband signal 406113 into Tx IF signal 406123. In some demonstrative aspects, at the Tx mode, bi-directional mixer 406130 may receive Tx IF signal 406123 at IF terminal 406133, and may upconvert Tx IF signal 406123 into Tx RF signal 406143. In some demonstrative aspects, at the Tx mode, bi-directional RF amplifier 406140 may receive Tx RF signal 406143 from RF terminal 406139 of bi-directional mixer 406130, and may amplify Tx RF signal 406143 into a Tx signal 406153, which may be transmitted, for example, by one or more antennas 406150. In some demonstrative aspects, at the Rx mode, bi-directional RF amplifier 406140 may receive Rx signal 406155 from one or more antennas 406150, and may amplify, for example, Rx signal 406155 into Rx RF signal 406147. In some demonstrative aspects, at the Rx mode, bi-directional mixer 406130 may downconvert Rx RF signal 406147 into IF signal 406127. In some demonstrative aspects, at the RX mode, bi-directional IF amplifier 406120 may amplify Rx IF signal 406127 from IF terminal 406133 of bi-directional mixer 406130 into Rx baseband signal 406117. Reference is now made to FIG. 194, which schematically illustrates a block diagram of a half-duplex transceiver 407100, in accordance with some demonstrative aspects. In some demonstrative aspects, half-duplex transceiver 407100 may be configured to operate at the Tx mode and/or at the Rx mode, e.g., as described below. In some demonstrative aspects, half-duplex transceiver 407100 may include, for example, a 60 GHz transceiver configured to transmit the Tx signals and to receive the Rx signals, for example, over a 60 GHz frequency band. In other aspects, other frequency bands may be used. In some demonstrative aspects, half-duplex transceiver 407100 may include a 5G cellular transceiver. In other aspects, transceiver 407100 may include any other type of transceiver and/or may be configured to communicate the Tx and/or Rx signals over any other frequency band. In some demonstrative aspects, half-duplex transceiver 407100 may include or may be operably coupled to one or more antennas 407150. For example, one or more antennas 407150 may be configured to transmit and/or receive one or more RF signals. For example, antennas 407150 may include one or more phased-array antennas, an in-chip antenna, and/or any other type of antennas. In some demonstrative aspects, half-duplex transceiver 407100 may include a baseband 407110, which may beconfigured to generate and/or process baseband signals 407010 and 407015, e.g., as described below. For example, baseband 407110 may include a digital baseband to process digital data and/or an analog baseband to, for example, process analog signals. For example, baseband 407110 may include a differential baseband, which may be configured to process a differential baseband signal. In some demonstrative aspects, half-duplex transceiver 407100 may include a Tx IF amplifier 407120, which may be configured to amplify, for example, a Tx baseband signal 407010 into a first Tx IF signal 407020 and/or a second Tx IF signal 407025. In some demonstrative aspects, Tx IF amplifier 407120 may include, for example, a differential IF amplifier having a differential output and a differential input. In other aspects, any other differential and/or non-differential IF amplifier may be used. In some demonstrative aspects, half-duplex transceiver 407100 may include an Rx IF amplifier 407125, which may be configured to amplify, for example, a first Rx IF signal 407030 and/or a second Rx IF signal 407035 into an Rx baseband signal 407015. For example, Rx IF amplifier 407125 may include, for example, a differential IF amplifier having a differential input and a differential output. In other aspects, any other differential and/or non-differential IF amplifier may be used. In some demonstrative aspects, half-duplex transceiver 407100 may include a splitter 407127, which may be configured to distribute, for example, first Tx IF signal 407020 and/or second Tx IF signal 407025, from Tx IF amplifier 407120 to a bi-directional mixer 407130, and to distribute, for example, first Rx IF signal 407030 and/or second Rx IF signal 407035, from bi-directional mixer 407130 to Rx IF amplifier 407125. For example, the use of splitter 407127 may be optional, and in other aspects, splitter 407127 may not be included. In some demonstrative aspects, bi-directional mixer 407130 may be configured to upconvert first Tx IF signal 407020 and/or second Tx IF signal 407025 into a first Tx RF signal 407040 and/or a second Tx RF signal 407045; and/or, for example, to downconvert a first Rx RF signal 407050 and/or a second Rx RF signal 407055 into first Rx IF signal 407030 and/or second Rx IF signal 407035, e.g., as described below. In some demonstrative aspects, bi-directional mixer 407130 may include a differential bi-directional mixer. In some demonstrative aspects, bi-directional mixer 407130 may include, for example, an IF terminal 407133 to input and/or output IF signals, e.g., to input first Tx IF signal 407020 and/or second Tx IF signal 407025, and/or to output first Rx IF signal 407030 and/or second Rx IF signal 407035. In some demonstrative aspects, bi-directional mixer 407130 may include, for example, an RF terminal 407134 to input and/or output RF signals, e.g., to output first Tx RF signal 407040, and/or second Tx RF signal 407045, and/or to input first Rx RF signal 407050 and/or second Rx RF signal 407055. In some demonstrative aspects, bi-directional mixer 407130 may include, for example, a first voltage terminal 407131 to receive a first bias voltage and/or a second bias voltage via a first control line 407060, and a second voltage terminal 407132 to receive the first bias voltage and/or the second bias voltage via a second control line 407065, e.g., as described below. In some demonstrative aspects, half-duplex transceiver 407100 may include, or may be operably coupled to, an LO 407135 to generate a first LO signal 407070 and/or a second LO signal 407075, e.g., as described below. For example, first LO signal 407070 and/or second LO signal 407075 may have a frequency of 60 GHz, and/or any other frequency. In some demonstrative aspects, first LO signal 407070 and/or second LO signal 407075 may be applied to bi-directional mixer 407130 to upconvert, for example, first Tx IF signal 407020 and second Tx IF signal 407025; and/or to downconvert, for example, first Rx RF signal 407050 and second Rx RF signal 407055, e.g., as described below. In one example, first LO signal 407070 and/or second LO signal 407075 may be implemented as a differential signal. In some demonstrative aspects, transceiver 407100 may include a controller, e.g., control circuitry 407160, which may be configured to switch, for example, a direction of operation of bi-directional mixer 407130, e.g., as described below. In some demonstrative aspects, control circuitry 407160 may be configured to apply, for example, via the first control line 407060, the first bias voltage to voltage terminal 407131, e.g., at the upconversion mode, and to apply the second bias voltage to voltage terminal 407131, e.g., at the downconversion mode, as described below. In some demonstrative aspects, controller circuitry 407160 may be configured to apply, for example, via the second control line 407065, the second bias voltage to voltage terminal 407132, e.g., at upconversion mode, and to apply the first bias voltage to voltage terminal 407132, e.g., at the downconversion mode, as described below. In some demonstrative aspects, controller circuitry 407160 may be configured to switch the direction of bi-directional mixer 406130, for example, by switching between applying the first bias voltage and applying the second bias voltage to voltage terminal 407131, e.g., through a first control line 407060, and/or by switching between applying the second bias voltage and applying the first bias voltage to voltage terminal 406132, e.g., through a second control line 407065, e.g., as described below. In some demonstrative aspects, bi-directional mixer 407130, may include a plurality of transistors, for example, in a Gilbert cell arrangement, which may be configured to upconvert first Tx IF signal 407020 and second Tx IF signal 407025 into first Tx RF signal 407040 and second Tx RF signal 407045, for example, at the upconversion mode, and/or to downconvert first Rx RF signal 407055 and second Rx RF signal 407050 into first Rx IF signal 407030 and second Rx IF signal 407035, for example, at the downconversion mode, e.g., as described below. In some demonstrative aspects, controller circuitry 407160 may be configured to switch bi-directional mixer 407130 to the upconversion mode, for example, by applying the first bias voltage, for example, through voltage terminal 407131, to drains of the plurality of transistors of bi-directional mixer 407130, and/or by applying the second bias voltage, for example, through voltage terminal 407132, to sources of the plurality of transistors of bi-directional mixer 407130, e.g., as described below. In some demonstrative aspects, controller circuitry 407160 may be configured to switch bi-directional mixer 407130 to the downconversion mode, for example, by applying the first bias voltage, for example, through voltage terminal 407132, to the sources of the plurality of transistors of bi-directional mixer 407130, and/or by applying the second bias voltage, for example, through voltage terminal 407131, to the drains of the plurality of transistors of bi-directional mixer 407130, e.g., as described below. In some demonstrative aspects, half-duplex transceiver 407100 may include a splitter 407137, which may be configured to distribute, for example, first Rx RF signal 407050 and/or second Rx RF signal 407055 from an Rx Tx amplifier 407145 to bi-directional mixer 407130, and to distribute, for example, first Tx RF signal 407040 and/or second Tx RF signal 407045, from bi-directional mixer 407130 to a Tx RF amplifier 407140. For example, the use of splitter 407130 may be optional, and in other aspects, splitter 407130 may not be included. In some demonstrative aspects, Tx RF amplifier 407140 may be configured to amplify, for example, first Tx RF signal 407040 and/or second Tx RF signal 407045 into an RF signal 407060, and to provide RF signal 407060 to one or more of antennas 407150. For example, Tx RF amplifier 407140 may include a differential PA having a differential input and a differential output. In some demonstrative aspects, Tx RF amplifier 407140 may include an outphasing amplifier, e.g., as described above with reference to FIG. 177, a Doherty power amplifier, e.g., as described above with reference to FIG. 174, a digital power amplifier, e.g., as described above with reference to FIG. 167, and/or any other amplifier. In some aspects, Rx RF amplifier 407145 may be configured to amplify an RF signal 407070 from one or more of antennas 407150 into first Rx RF signal 407050 and/or second Rx RF signal 407055. In some demonstrative aspects, Rx RF amplifier 407145 may include a differential LNA having an input and a differential output. In other aspects, Rx RF amplifier 407145 may include a non-differential LNA, a wideband LNA and/or any other type of LNA. Reference is now made to FIG. 195, which schematically illustrates a bi-directional mixer 408000, in accordance to some demonstrative aspects. For example, one or more elements and/or components of bi-directional mixer 408000 may be implemented as part of a bi-directional mixer 406130, e.g., as described above with reference to FIG. 193, and/or bi-directional mixer 407130, e.g., as described above with reference to FIG. 194. In some demonstrative aspects, bi-directional mixer 408000 may include, for example, an RF terminal 408105, which may be configured to receive a first RF signal 408106, for example, from an Rx RF amplifier, e.g., Rx RF amplifier 407145 (FIG. 194), and/or to provide a second RF signal 408103, for example, to a Tx RF amplifier, e.g., Tx RF amplifier 407140 (FIG. 194), e.g., as described below. In some demonstrative aspects, bi-directional mixer 408000 may include, for example, an IF terminal 408160, which may be configured to receive a first IF signal 408166, for example, from a Tx IF amplifier, e.g., Tx IF amplifier 407120 (FIG. 194), and/or to provide a second IF signal 408163, for example, to an Rx IF amplifier, e.g., Rx IF amplifier 407125 (FIG. 194), e.g., as described below. In some demonstrative aspects, bi-directional mixer 408000 may include, for example, a first voltage terminal 408170, which may be configured to apply, for example, a first bias voltage 408175, e.g., VDD, and/or a second bias voltage 408185, e.g., VSS, for example, based on whether bi-directional mixer 408000 is to be operated at an upconversion mode or a downconversion mode, e.g., as described below. In some demonstrative aspects, bi-directional mixer 408000 may include, for example, a second voltage terminal 408180, which may be configured to apply, for example, the first bias voltage 408175, e.g., VDD, and/or the second bias voltage 408185, e.g., VSS, for example, based on whether bi-directional mixer 408000 is to be operated at an upconversion mode or a downconversion mode, e.g., as described below. In some demonstrative aspects, first bias voltage 408175 may be a positive voltage, for example, a voltage in the range of 1-5 Volts or any other voltage, and/or the second bias voltage 408185 may be a zero voltage and/or a voltage close to zero In some demonstrative aspects, bi-directional mixer 408000 may include, for example, mixing circuitry 408100, which may be configured, for example, to operate at the upconversion mode, for example, when first bias voltage 408175, e.g., VDD, is applied to first voltage terminal 408170, and second bias voltage 408185, e.g., VSS, is applied to second voltage terminal 408180, e.g., as described below. In some demonstrative aspects, mixing circuitry 408100 may be configured to operate, for example, at the downconversion mode, when second bias voltage 408185, e.g., VSS, may be applied to first voltage terminal 408170 and first bias voltage 408175, e.g., VDD, may be applied to second voltage terminal 408180, e.g., as described below. In some demonstrative aspects, mixing circuitry 408100 may be configured to, for example, at the downconversion mode, downconvert first RF signal 408106 at RF terminal 408106 into, for example, first IF signal 408163 at IF terminal 408160, e.g., as described below. In some demonstrative aspects, mixing circuitry 408100 may be configured to, for example, at the upconversion mode, upconvert, for example, a second IF signal 408166, at IF terminal 408160 into, for example, a second RF signal 408103, at RF terminal 408105, e.g., as described below. In some demonstrative aspects, mixing circuitry 408100 may include, for example, a Gilbert-cell 408120, including a plurality of transistors, for example, including transistors 408122, 408124, 408126 and/or 408128, e.g., as described below. In some demonstrative aspects, the plurality of transistors of Gilbert cell 408120, e.g., transistors 408122, 408124, 408126 and/or 408128 may include one or more FETs. In some demonstrative aspects, the plurality of transistors of Gilbert cell 408120, e.g., transistors 408122, 408124, 408126 and/or 408128, may be configured to upconvert, for example, second IF signal 408166 into second RF signal 408103, e.g., at the upconversion mode; and/or to downconvert, for example, first RF signal 408106 into first IF signal 408163, e.g., at the downconversion mode. In some demonstrative aspects mixing circuitry 408100 may include, for example, a first transformer 408110, which may be configured, for example, to couple drains of the plurality of transistors of Gilbert cell 408120, e.g., drains of transistors 408122, 408124, 408126 and/or 408128, to RF terminal 408160 and to first voltage terminal 408170, e.g., as described below. In some demonstrative aspects, mixing circuitry 408100 may include, for example, a second transformer 408130, which may be configured, for example, to couple sources of the plurality of transistors of Gilbert cell 408120, e.g., sources of transistors 408122, 408124, 408126 and/or 408128, to IF terminal 408160 and to second voltage terminal 408180, e.g., as described below. In some demonstrative aspects, mixing circuitry 408100 may include, for example, an LO terminal 408132, which may be configured to couple, for example, an LO signal 408136 to gates of the plurality of transistors of Gilbert cell 408120, e.g., gates of transistors 408122, 408124, 408126 and/or 408128, e.g., as described below. In some demonstrative aspects, LO terminal 408132 may be configured to apply to Gilbert cell 408120 a positive LO signal (LO+) component and/or a negative LO signal (LO-) component of LO signal 408136. In some demonstrative aspects, first transformer 408110 may be configured to, e.g., at the downconversion mode, provide, for example, first RF signal 408106 and second bias voltage 408185, e.g., VSS, to the drains of the plurality of transistors of Gilbert cell 408120, e.g., the drains of transistors 408122, 408124, 408126 and/or 408128. In some demonstrative aspects, for example, Gilbert cell 408120 may be configured to, e.g., at the downconversion mode, mix first RF signal 408106 with LO signal 408136, for example, to provide a mixed RF signal to the sources of the plurality of transistors of Gilbert cell 408120, e.g., the sources of transistors 408122, 408124, 408126 and/or 408128, e.g., as described below. In some demonstrative aspects, second transformer 408130 may be configured to, e.g., at the downconversion mode, combine, for example, the mixed RF signal at the sources of the plurality of transistors of Gilbert cell 408120, e.g., transistors 408122, 408124, 408126 and/or 408128, into second IF signal 408163. In some demonstrative aspects, second transformer 408130 may be configured to, e.g., at the upconversion mode, provide, for example, second IF signal 408166 and second bias voltage 408185, e.g., VDD, to the sources of the plurality of transistors of Gilbert cell 408120, e.g., transistors 408122, 408124, 408126 and/or 408128, e.g., as described below. In some demonstrative aspects, for example, Gilbert cell 408120 may be configured to, e.g., at the upconversion mode, mix second IF signal 408166 with LO signal 408136, for example, to provide a mixed RF signal to the drains of the plurality of transistors of Gilbert cell 408120, e.g., transistors 408122, 408124, 408126 and/or 408128, e.g., as described below. In some demonstrative aspects, first transformer 408110 may be configured to e.g., at the upconversion mode, combine, for example, the mixed IF signal at the drains of the plurality of transistors of Gilbert cell 408120, e.g., transistors 408122, 408124, 408126 and/or 408128, into first RF signal 408103. In some demonstrative aspects, mixing circuitry 408100 may include, for example, a first switch 408140, which may be operably coupled to, for example, first voltage terminal 408170. For example, at the upconversion mode, first switch 408140 may couple first bias voltage 408175, e.g., VDD, to the drains of the plurality of transistors of Gilbert cell 408120, e.g., the drains of transistors 408122, 408124, 408126 and/or 408128. For example, at the downconversion mode, first switch 408140 may couple second bias voltage 408185, e.g., VSS, to the drains of the plurality of transistors of Gilbert cell 408120, e.g., transistors 408122, 408124, 408126 and/or 408128, e.g., as described below. In some demonstrative aspects, a control signal 408190 may be configured to control first switch 408140 to selectively apply first bias voltage 408175 e.g., VDD, or second bias voltage 48185, e.g., VSS, to Gilbert cell 408120 via first transformer 408110. In some demonstrative aspects, first switch 408140 may include a plurality of transistors, which may be configured to, for example, at the upconversion mode, couple first bias voltage 408175, e.g., VDD, for example, from first voltage terminal 408170, to the drains of the plurality of transistors of Gilbert cell 408120, e.g., the drains of transistors 408122, 408124, 408126 and/or 408128. In some demonstrative aspects, first switch 408140 may include a plurality of transistors, which may be configured to, for example, at the downconversion mode, couple second bias voltage 408175, e.g., VSS, for example, from first voltage terminal 408170, to the drains of the plurality of transistors of Gilbert cell 408120, e.g., the drains of transistors 408122, 408124, 408126 and/or 408128. In some demonstrative aspects, mixing circuitry 408100 may include, for example, a second switch 408150, which may be operably coupled to, for example, second voltage terminal 408180. For example, at the upconversion mode, second switch 408150 may couple second bias voltage 408185, e.g., VSS, to the sources of the plurality of transistors of Gilbert cell 408120, e.g., transistors 408122, 408124, 408126 and/or 408128. In some demonstrative aspects, at the downconversion mode, second switch 408150 may couple first bias voltage 408175, e.g., VDD, to the sources of the plurality of transistors of Gilbert cell 408120, e.g., transistors 408122, 408124, 408126 and/or 408128. In some demonstrative aspects, a control signal 408195 may be configured to control second switch 408150 to apply, for example, first bias voltage 408175, e.g., VDD, or second bias voltage 408185, e.g., VSS, to Gilbert cell 408120 via second transformer 408130. In some demonstrative aspects, second switch 408150 may include a plurality of transistors, which may be configured to, for example, at the downconversion mode, couple first bias voltage 408175, e.g., VDD, for example, from second voltage terminal 408180, to the sources of the plurality of transistors of Gilbert cell 408120, e.g., the sources of transistors 408122, 408124, 408126 and/or 408128. In some demonstrative aspects, second switch 408150 may include a plurality of transistors, which may be configured to, for example, at the upconversion mode, couple second bias voltage 408175, e.g., VSS, for example, from second voltage terminal 408180, to the sources of the plurality of transistors of Gilbert cell 408120, e.g., the sources of transistors 408122, 408124, 408126 and/or 408128. In some demonstrative aspects, first switch 408140 and/or second switch 480150 may include, for example, a plurality of transistors, which may be configured to switch between the first and second bias voltages to be applied to, for example, the plurality of transistors of Gilbert cell 408120, e.g., as described below. For example, as shown in FIG. 195, the plurality of transistors of switch 408150 may include a transistor 408156 and a transistor 408153. For example, transistor 408156 may be configured to apply first bias voltage 408175, e.g., VDD to, for example, the plurality of transistors of Gilbert cell 408120, e.g., as described below. For example, transistor 408153 may be configured to apply second bias voltage 408175, e.g., VSS, to, for example, the plurality of transistors of Gilbert cell 408120, e.g., as described below. For example, transistor 408156 may be configured to, for example, apply first bias voltage 408175, e.g., VDD, to the plurality of transistors of Gilbert cell 408120, e.g., transistors 408122, 408124, 408126 and/or 408128, when a voltage level of control signal 408195 at a gate of transistor 408156 may be, for example, in a range of 1 to 5 Volts. For example, transistor 408153 may be configured to apply, for example, second bias voltage 408185, e.g., VSS, to, for example, the plurality of transistors of Gilbert cell 408120, e.g., transistors 408122, 408124, 408126 and/or 408128, when a voltage level of control signal 408195 at a gate of transistor 408153 may be, for example, in a range of 1 to 5 Volts. In some demonstrative aspects, transistors 408153 and/or 408156 may include a FET. In other aspects, transistors 408153 and/or 408156 may include any other type of transistors. A challenge for mmWave RFEMs is providing complete or near-complete directional coverage with high antenna gain. Usually this is achieved by phased array antennas that provide beam steering. However, the use of phased array antennas (such as an array of planar patch antennas) by themselves only provides limited angular coverage. Although beam steering can help to direct energy towards the intended receiver, a simple array limits the coverage of steering angles of beam steering. In addition, polarization of RF signals is also a challenge for mmWave RFEMs, at least for the reason that when transmitting to a mobile device, the position or orientation of the mobile device cannot be guaranteed, leading to less than optimum signal reception because the polarization of the transmitted signal may not be a suitable match for the position or orientation of the mobile device. These challenges are addressed in aspects described herein. In some aspects of the present disclosure, patch antennas are used. A patch antenna includes a narrowband, wide-beam antenna fabricated by etching the antenna element pattern in a metal trace bonded to an insulating dielectric substrate, such as a printed circuit board (PCB). In some cases, the ground plane of the antenna can be formed using a continuous, or nearly continuous, metal layer bonded to the opposite side of the substrate, which may form a ground plane. In other cases, the ground plane of the antenna can be formed using a continuous, or nearly continuous, metal layer bonded to the same side as the antenna element pattern. In some aspects of the present disclosure, one or more integrated circuit (IC) shield covering, which may be grounded, may be used as the antenna ground plane. Use of such a shield covering as a ground plane is not limited to patch antennas, but can apply as well to monopole antennas, dipole antennas, and combinations of all or some of the foregoing. Continuing with the discussion of patch antennas, patch antennas may by implemented by use of a microstrip which can be a printed metal strip on a circuit board for RF transmission. Common microstrip antenna shapes are square, rectangular, circular and elliptical, but any continuous shape is possible. In some aspects of the present disclosure, a patch antenna does not use a dielectric substrate and instead is made of a metal patch mounted above a ground plane using dielectric spacers. The metal patch can be mounted as close as possible (commensurate with other system requirements) to the shield, which, in turn, functions as the ground plane. Structures may be implemented to provide a wider bandwidth than the narrowband alluded to above. Because such antennas have a very low profile, are mechanically rugged and can be shaped to conform to system needs, they can be incorporated into mobile radio communications devices. In some aspects of the present disclosure, antennas can be subject to stringent space limitations. For example, when antennas are used as a part of a mobile device, such as UE, antennas can be subject to space limitations, such as limitations on the floorplan real estate of the electrical board and/or limitations on the thickness of the mobile device that can lead to height limitations. To address the space limitations, in some aspects of the present disclosure, antennas can use IC shields as a ground plane to meet some requirements of antennas. For example, IC shields, which may be a system requirement in any event, can be used to provide a radiation pattern that directs radiation primarily outward from the mobile device with low or minimal radiation power lost by reflection back into the mobile device. This allows the antennas to provide desired radiation while at the same time working within the confines of the limited space due, in some cases, to the requirements for Globalnaya Navigatsionnaya Sputnikovaya Sistema (GLONASS). In some aspects of the present disclosure, antennas can be integrated as one or more SMDs. In many cases, SMD antennas can have a small thickness, which is helpful for complying with the thickness requirement of mobile devices. The SMD itself, in the context of this patent, may comprise material suitable for printing or otherwise affixing an antenna or a feed line onto or within the SMD. The SMD may be a high frequency material similar to that of the main package hosting the radio frequency integrated circuit (RFIC). Depending on the specific solution, the material can be chosen to be the same as the main package or with different dielectric constant; for example, to optimize or improve the stacked patch solution of FIG. 446, the dielectric constant can be chosen to be lower than that of the main package. Typically, for good antenna performance, low dielectric constant and low loss tangent are desired. In some aspects of the present disclosure, an SMD antenna that has less height than the thickness of the mobile device can take advantage of on-board available height which is not being used. For example, an antenna may be implemented on and/or within an SMD within the mobile device where there would otherwise not be sufficient floor space for the antenna. In some aspects of the present disclosure, the SMD antenna can be soldered to the printed circuit board (PCB). Further, in some aspects of the present disclosure, the placement of the feeding of the desired transmit or receive signal can be used advantageously for the foregoing and other purposes. For example, the feed can be used for impedance matching as described below with respect to FIGS. 452B and 452C. In some aspects of the present disclosure, antenna types may offer single polarization. In some aspects of the present disclosure, antenna types may offer dual polarization. Generally, some polarization directions have been challenging to achieve. This problem may be solved, or at least ameliorated, by the antenna structures and combinations disclosed below. In some aspects of the present disclosure, antennas may offer single, dual or multiple polarization capability. In some aspects of the present disclosure, multiple antennas of different types are used to provide angular coverage and polarization coverage. In some aspects of the present disclosure, multiple different antenna types operate alone or in conjunction with each other, such as in a combination of phased arrays of antennas. In some aspects of the present disclosure, when multiple different antenna types that are implemented in a phased antenna array operating in conjunction with each other, they may be controlled by a controller and/or by codebook to enable the controlled arrays to provide vertical, horizontal, and/or diverse polarization as needed, depending on strength of the received polarized signal at the mobile device. In some aspects of the present disclosure, the strength of received polarized signal at the mobile device is fed back to the antenna or antenna array controllerto fire, or feed, the antenna arrays in a sequence that will provide the appropriate polarization at the receiver, which in some aspects of the present disclosure may be a UE, and thereby improve overall angular coverage. Thus, in some aspects of the present disclosure, multiple different antenna types may be operated together to provide polarization coverage in one or more directions. These advantages will be made clearer below in this written description. Using a low-cost planar array might result in reduced coverage and degraded service because of scanning limitations. The coverage can be restored by adding additional antenna arrays at extra cost. The additional antenna arrays at millimeter wave frequencies can extend coverage at small extra cost and enable low cost systems for very high data rate communications. In some aspects, the antenna (or antenna-related) circuitry described herein can be incorporated in the antenna array 330 of the mmWave communication circuitry 300 shown in FIG. 3A, although the antenna circuitry is not limited to such. FIG. 196Aillustrates at 40900 a transceiver, which may be within RFIC 40901 coupled to a phased-array 40903 comprising antennas 40905, according to some aspects of the present disclosure. The transceiver comprises RFIC 40901 which may operate, in some aspects of the present disclosure, in 60 GHz radios. The phased-array arrangement is used to overcome propagation loss at 60 GHz and allow multi-Gb/s communication over large distances. The RFIC 40901 may be coupled to phased array 40903 comprising antennas 40905 which may be patch or other type antennas located on substrate 40907. However, such phased-array transceivers can suffer from limited angle of coverage, which includes the angle over which the beam 40909 can be scanned without grating lobe performance degradation beyond required system specifications. FIG. 196Billustrates an antenna array with an original angle of coverage, according to some aspects of the present disclosure. The original angle of coverage can include the angle 40911 between beams A and B. Generally, the angle of coverage of an antenna array is smaller than the ideal 180 degrees (half space.) This limited angle of coverage tends to degrade the service of the communications system that uses the antenna array. In some aspects of the present disclosure, a microwave element disposed in a communication path from the antenna array can improve the angle of coverage. Fig. 196Cillustrates a microwave element used in conjunction with a phased-array antenna, according to some aspects of the present disclosure. The microwave element (e.g., a lens 40913) is configured to deflect the beams and extend the angle of coverage of the antenna array from the angle 40911 (between beams A and B) to the angle 40915 (between the deflected beams A1 and B1). This results in better spatial coverage for the communications system with the same number of antenna arrays. In FIG. 196C, a simple lens 40913 (e.g., a prism) is placed on top of the antenna array. Because the €r (permittivity) of the lens 40913 is higher than air, beam A is deflected closer to the lens and becomes beam A1, rather than continuesstraight (A2). Similarly, for beam B at the other end of the angle of coverage of the array. It is seen that the angle of coverage with the lens (angle 40915 between A1 and B1) is larger than the original angle of coverage (40911 angle between A2 and B2, which is also the angle between beams A and B of FIGS. 196Band 196C). This increased angle translates to increased coverage for the wireless system and smaller probability of outage. In some aspects of the present disclosure, the microwave element can include any lens assembly or lens system that allows the focusing of the electromagnetic radiation in the desired direction. The lens can be inexpensive. In some aspects of the present disclosure, anomalies of the lens will be taken care of by the beamforming training present in most directional millimeter wave systems. Beamforming training in this instance can mean an algorithm and/or procedure that allows creation of an optimal beam pointed in the desired direction. As an example, a reference receiver can be used to calibrate the beam of the device under test (DUT) when the DUT is configured as a transmitter (TX). The DUT TX beam can be adjusted by adjusting the weights (phase and possible amplitude) of the TX signal at each DUT antenna element so that signal at the reference receiver is maximized or highly improved. This would compensate for TX non-idealities in the RFIC as well as in the antennas and lens. A planar phased-array has been assumed in the discussion since this would result in the lowest cost solution, although those of ordinary skill in the art will recognize that other types of phased arrays may be used. In some aspects of the present disclosure, the microwave element can include a reflector. FIG. 196Dillustrates a convex reflector 40923 used in conjunction with a phased-array to deflect the radiated beams and extend the angle of coverage, according to some aspects of the present disclosure. As in FIGS. 196Band 196C, the antenna phased array has an original reduced angle of coverage, comprising angle 40911 between beams A and B. The angle 40911 represents limited angle of coverage covered by scanning. Beams A and B reflect off convex reflector 40923 resulting in a wider angle of coverage (e.g., angle 40915 between beams A1 and B1) than the original angle of coverage (angle 40911 between beams A and B). In some aspects of the present disclosure, the microwave element can include a combination of a lens 40913 and a reflector 40923. Relatively small beam steering that can result from a non-reflector array combination (e.g., an array with no reflector)corresponds to a larger angle of coverage after the reflection by reflector 40923. For example, the angle 40915 that results after reflection from reflector 40923 in the aspects of FIG. 196Dis greater than the angle 40911 before reflection from the reflector. So if the phased array is limited to approximately plus or minus 45 degrees of steering, the reflector can increase this degree range to as much as plus or minus 90 degrees, in some aspects of the present disclosure. In some aspects of the present disclosure, the convex reflector 40923 includes a spherical reflector. The convex reflector 40923 can be designed to comply with system requirements. In some cases, the convex reflector 40923 can use reflector curvatures of varying types and can be placed at varying distances from the phased array to satisfy system requirements. In some aspects of the present disclosure, the convex reflector 40923 can be configured to provide non-linear beam expansion without undue experimentation, where the angle of coverage after reflection increases with increased beam steering. As one example, if an initial increased reflection coverage of 1.5 times compared to the non-reflected case is achieved, beam steering that approaches the limit of the phased array beam steering range may achieve increased reflection coverage of 2 times or more, thus exhibiting increased coverage due to an increase in the beam steering. This improved coverage is a benefit without sacrificing an inordinate amount of steering angle resolution at smaller steering angles. This non-linear beam coverage expansion can be plotted as a function of amount of beam steering, for different types of reflector curvatures, again at varying distances of the phased array from the reflector. When using mmWave frequencies like 60 GHz or 28 GHz for communication, a relatively high antenna gain is used. While high antenna gain may be obtained by a single beam dish antenna, such an antenna is costly and requires substantial power to operate. To address this issue, the RFEM can be configured to use a phased array of antennas (e.g., 16 elements), or a plurality of such phased arrays, substantially at the focus of a Cassegrain or other type of reflector antenna, such as, in one aspect, a printed reflector antenna. One effect is that on the focus, the transmitted signal is amplified using the reflector itself, resulting in a more focused beam with higher gain. Further, if more than one phased array of, in one aspect, patch antennas were placed at or near the focus of the reflector antenna, a sectorized plurality of scan regions result from the same antenna or reflector, as discussed in additional detail below. As to placement, when the implementation is for mmWave frequencies, the RFEMs may, in some aspects of the present disclosure, be mounted through an arm-like fixture similar to, but, much smaller than, those of larger antennas in current use where the objective is to irradiate the focus, to allow the location of multiple RFEMs in the center feed. An alternative placement in some aspects of the present disclosure would be by way of a small number (perhaps two) of small and shorter arms that surround the Cassegrain dish or the printed reflector. Tolerance should be considered in the placement of the PAFs. In some aspects, tolerance is considered to be about 5% to 10% of the distance from the accurate center (or bottom in some aspects of the present disclosure) to obtain desired performance. Even if the location is not within the afore-mentioned tolerance, the system will still operate as described here but there may be linear degradation in performance. Whether a Cassegrain antenna or a printed reflector antenna is used can be a tradeoff. While a Cassegrain antenna can provide higher gain (and range) than a printed reflector antenna, a Cassegrain antenna is much bulkier, heavy and expensive than a printed reflector. So much depends on the system requirements. In some aspects of the present disclosure only medium range may be required and, for those aspects, printed reflectors may be the better choice. Phased array communication systems such as 5G mmWave and WiGig Access points and base stations implemented in these technologies have as an objective to provide multi-sector and multi-user coverage. Aspects discussed herein allow low-cost, high Equivalent Isotropic Radiated Power (EIRP) for mmWave phased array antenna implementations for multi-sector and multi-user coverage. A sector includes the range of angles in azimuth in which the beam scanning of an mmWave array is effective (typically plus or minus sixty (60) degrees). Additionally, implementations disclosed are aimed to provide multi-frequency capability in a single array (located per sector). This can be achieved by physically mounting three (or more) separate mmWave phased antenna arrays in the feed region of a reflector based antenna, such as those seen in FIGS. 410 through 415. These phased-arrays may be hereafter referred as “Phased-Array-Feeders” (“PAF”). Since each antenna-array may be located in a different position versus the optimum feed location of the antenna array, the beam-scanning pattern of each antenna array will be tilted differently as seen in the sectorization of FIG. 203discussed below. However, if the antenna array is placed at the center of either a Cassegrain or reflector array, a problem arises because, at mmWave frequencies, the mmWave antenna array itself, as well as the mechanism holding of that mmWave antenna array will detract from the emission of the reflector. This may occur because at the high frequency of mmWave as opposed to lower frequency arrays with frequencies at, for example, approximately 5 GHz essentially any obstacle, even non-metallic objects such as wood or plastic, actually blocks or otherwise interferes with the communication. So installing a relatively large mechanical holder for a small antenna array that fits right in the center of a dish, for example, may result in detraction of emission. One solution is to put the antenna array substantially on the focus. Another way to ameliorate this problem is to put the phased array on the side or the bottom of the reflector at an angle so that the beam will hit at the focus of the reflector and the irradiation or will emulate a beam placed at the focus of the reflector. FIG. 197illustrates an operation of a phased array/reflector combination when the antenna array is placed at the bottom of a Cassegrain array or reflector array, where FIG. 197indicates that by using a small phased antenna array, the beam can be directed so that it hits essentially the focus of the reflector or Cassegrain antenna. In some aspects of the present disclosure, the multi-sector antenna array with high antenna gain can be implemented using Massive-Antenna-Arrays. Massive-Antenna-Arraysinclude a coherent combination of one array that has antenna elements numbering much higher than the 8, 16, 32 or 64 element arrays sometimes used, or include multiple arrays, in both cases to create a high gain beam. The number of such elements, in some aspects of the present disclosure, could range into the hundreds. Then allocation of such multi-array per direction aspects (e.g. three multi-antenna arrays located physically 60 degrees from each other) can be implemented, much like the arrangements of three PAFs illustrated in FIGS. 410-415. Additional advantages of a plurality of phased array feeders placed at or near the focus of a reflector include, for example: a. Adding sectors in an easy form factor without enlarging the dimension of the antenna of each sector, merely byadding additional PAFs; b. Adding users with no degradation of throughput or effective isotropically radiated power (EIRP) (example: in different sectors two different Phased Array Feeders (PAF) would be active. In other schemes such as Massive Antenna Array, each user would get half of the array elements); c. Higher EIRP by changing the reflector; and d. Adding Phased Array Feeders (PAF) to create more sectors does not cause heating problems, since each PAF is “standalone” In case an antenna array is located in the feed of reflector based antenna, then some of its beam scanning capability is still preserved. In some aspects of the present disclosure, if an antenna array is used in the open air (without being mounted at the feed of the reflector array), then its typical scan range of plus or minus 3 dB is about plus or minus 60 degrees. Once such an array is mounted in a feed of the reflector based antenna, the scanning range is reduced to plus or minus 30 degrees (approximately). The scan range versus the zero-degree reference point changes depending on the physical location of the arrays in the reflector antenna. As the array is mounted closer to the ideal focus of the reflector, its scan range becomes more symmetrical and can range from -30 to +30 degrees (around the zero azimuth). Once the antenna array is located far from the ideal focus, its scan range will be centered at different angles (proportional to the distance of the antenna array from the focus). Each Phased Array-Feeder can operate in one frequency or in multiple frequency (e.g. 60 GHz and 28 GHz, inasmuch as they are a multiple of 2). The multi-feeds can be mounted in a printed reflector antenna-array as illustrated in FIGS. 410, 412, and 414 or a Cassegrain antenna with parabolic shape as illustrated in FIGS. 411, 413, and 415, according to some aspects of the present disclosure. FIG. 197illustrates a plurality of phased arrays used in conjunction with a printed reflector in a first configuration, according to some aspects of the present disclosure. In FIG. 197, reference 41000 illustrates a printed reflector 41010 wherein three phased arrays 41020, 41030, 41040 are located at the bottom of the antenna 41010. Since aspects described herein may be used in point-to point communication, such as communication between two nodes or end points, the phased arrays may be used in transmit mode or in receive mode, the timing controlled in accordance with system operation. The phased arrays 41020, 41030, and 41040 may be transmitting toward the reflector 41000 in transmission mode. In side view is illustrated incoming beams 41050, 41060, 41070 whenreceive mode is active. Reflector 41010 is seen in Front View (looking into the reflector), Side View (looking from the side of the reflector), and Top View (looking downwardly from the top of the reflector). These views are the traditionally named Front View, Side View, and Top View, in the engineering drawing sense for ease of description. However, if the combination were within a mobile device the views may be differently named, for example with what is called Front View in FIG. 197corresponding to looking downwardly into the mobile device, and what is called Top View in FIG. 197being looking at what may be termed the bottom area of the reflector. The views illustrated in FIG. 197are typical for FIGS. 411 through 415. FIG. 198illustrates a plurality of phased arrays used in conjunction with a Cassegrain antenna in the first configuration 41100, namely at the bottom of the Cassegrain antenna, according to some aspects of the present disclosure. FIG. 199illustrates a plurality of phased arrays used in conjunction with a printed reflector in a second configuration 41200, namely in the center region, according to some aspects of the present disclosure. The TOP view illustrates a view looking down from the top of the reflector. Array, Sector 1, and Array, Sector 3, are drawn essentially to size, whereas Array Sector 2 is drawn smaller for distinguishing Array, Sector 2 from the other two arrays in that view. FIGS. 413, 414, and 415 are typical (or similarly drawn) with respect to Array, Sector 1, Array, Sector 2, and Array, Sector 3, in the TOP view FIG. 200illustrates a plurality of phased arrays used in conjunction with a Cassegrain antenna in the second configuration 41300, namely in the center region, according to some aspects of the present disclosure. FIG. 201illustrates a plurality of phased arrays used in conjunction with a printed reflector in a third configuration, 41400, namely around the reflector, according to some aspects of the present disclosure. FIG. 202illustrates a plurality of phased arrays used in conjunction with a Cassegrain antenna in the third configuration 41500, namely around the reflector, according to some aspects of the present disclosure. The three arrays, Array, Sector 1, Array, Sector 2, and Array, Sector 3 in some aspects of the present disclosure will include or be part of an RFEM. The RFEMs are not, in practice, located at the bottom of the reflector as illustrated in FIGS. 410-415. Instead they are held in or near the middle of the reflector of with a mechanical arm which is not shown in the drawing. The different physical position of each phased array feeder will create a sectored scan-pattern which is shifted by a certain angle from each antenna array, creating a high gain sectorized-like deployment. Ideally, such a bias between the center of each scan-pattern of the array should be in the order of 60 to 90 degrees as illustrated in FIG. 203. FIG. 203illustrates a top view of sectorization 41600 resulting from a plurality of phased arrays used in conjunction with a reflecting antenna, according to some aspects of the present disclosure. At mmWave frequencies, a beam from an antenna array is very narrow, conceptually like a laser beam, and can be scanned across the sector. The narrow beam is indicated at 41601 and beam scanning across sectors is indicated by the double-ended arrow. FIG. 204illustrates scanning in each sector of the sectorized scan regions, according to some aspects of the present disclosure. The X axis is the angle of scan of the beam from an antenna array focused at the reflector antenna. The Y axis is the amplitude of the beam. Discussion here is with respect of Sector 1, but operation for Sector 2 and Sector 3 (and additional sectors, depending on the number of phased array feeders) is similar. For Sector 1 there is a variation of the amplitude of the scanned beam. Numbers given in this discussion are as examples only and do not represent actual tested numerical values. Beam amplitude 41701 occurs when the beam is being tuned, for example, to minus 50 degrees compared to boresight. Beam amplitude 41703 occurs when the beam is tuned closer to boresight, for example minus 20 degrees compared to boresight. Beam amplitude 41705 occurs when the beam is being tuned, for example, to minus 10 degrees compared to boresight. Beam amplitude 41707 occurs when the beam is tuned to boresight of Sector 1. The reason for amplitude variation each beam tuning angle is that as the beam is scanned there tends to be amplitude degradation because of various physical characteristics of the patches that comprise the phased array feeder. The PAF design discussed here also offers a link advantage. Consider the example in which only one sector is used (e.g., in an aspect that has only one phased array feeder, with many antenna elements in the array). If the PAF is scanned the entire plus or minus 90 degrees range, or scanned an abbreviated range of plus minus 80 degrees, a certain amount of attenuation of the array beam occurs at large angles, sometimes referred to as “at the sides,” (or “very large angles from boresight”). Even a high gain antenna at boresight can provide very poor gain (or exhibit high degradation) at the sides. However, with a PAF described here, the degradation at the sides might be of the order of minus 3 dB, which for many purposes is an acceptable degradation. Consequently, there is also a link budget advantage with the described PAF approach compared to phased arrays that are not used as feeders to a reflector antenna. In other words, it is sometimes beneficial to place the phased array in the center at the bottom. Then, by beam feeding, the beam will hit the focus because at 60 GHz the propagation is very similar to a laser beam and is so well focused that using beam feeding will shift the angle of the beam so that the above-described phenomenon occurs. Further, multiple arrays can be used as in FIGS. 410-415, described below, to create different scanning sectors. In summary, phased antenna arrays can be placed at the focus of a dish or reflector antenna, which will create high gain. Not only can the phased array be placed at the focus, but it can also be placed at the bottom of the reflector to interfere less with the signal created by the dish or by the reflector. Furthermore, multiple phased arrays can be placed at the center of the dish and when the beam is aimed at the focus sectorized emissions are created for each phased array at a certain area in front of the reflector and that in turn will create a sectorized emission to a target. The same phenomenon occurs when the phased array is placed at the bottom of, or around, the reflector as discussed above. In some aspects of the present disclosure, the PAF design can support multi-users. If the system is to be designed to support a plurality of users, instead of lowering the transmission to each user (resulting in lower overall quality of the signal), additional feeders can be added to the same reflector to increase the capacity of the system and the number of users the system can support without facing problems like inordinate heat dissipation at one location. While three PAFs have been illustrated in FIGS. 410-416, additional PAFs can be added as additional users are added for receiving the signal from the transmitter that is transmitting via the PAFs. For example, where three PAFs are used in an equilateral triangular arrangement about a point such as a focus, as in FIG. 202, four PAFs may be used in a square arrangement about the point. Five PAFs may be arranged similarly, (in a pentagram-like arrangement about the point). One application of this type of reflector/phased array would be that such a system would be implemented in an access point. One access point can support many users by dividing the coverage to different sectors or within each sector, to have a separate feeder to increase the capacity of each sector. As to polarization, in point-to-point systems, it is quite common for a reflector/phased array to have a vertical polarization feeder (V feeder) and a horizontal polarization feeder (H feeder). In some aspects of the present disclosure, the above reflector with a V feeder and an H feeder can cover both vertical polarization and horizontal polarization. The system can transmit with vertical polarization or horizontal polarization or, with both vertical polarization and horizontal polarization that is orthogonal to the vertical polarization. As discussed in further detail below, there are generally two feeds for each patch inside a phased array, so one of them can be for vertical polarization and one for horizontal polarization. When connecting to a user via a base station or an access point, then either of the two feeds (vertical polarization or horizontal polarization) can be called by a control program and used for scanning or “sector sweeping.” For example, if there are 63 sectors only with the vertical polarization, there can be 128 sectors with horizontal polarization. A sector is actually a combination of the phased array(s), phase shifter and polarization, which can mitigate polarization issues. For some aspects of the present disclosure in a WiGig implementation, the polarization techniques include just scanning. A test transmission packet in one set of phase shifter and one set of, for example, vertical polarization is transmitted to the receiver, and the receiver measures received signal strength. Another set with horizontal polarization is sent to the receiver and the receiver measures the received signal strength. Subsequently, the receiver transmits the polarization with the better signal strength and the transmitter then transmits in that polarization. In some aspects of the present disclosure, this process is continuous in order to transmit the better polarization continuously. This can be accomplished using a control message that has a very low fire rate, so that it has a very high processing rate and does not need the gain of the antenna. Instead of using another combination of phase shifter, a feed of another polarization is used. The system itself is not limited because there is good isolation between vertical polarization and horizontal polarization at the feeder. The patch antenna elements of a phased array have good isolation and the reflector does not degrade it significantly. Essentially, each patch antenna is double-feeding one vertical polarization signal and one horizontal polarization signal, each with the same information, and the appropriate polarization is used at the appropriate time. In other aspects, this process can be performed when certain criteria are met. The aspects disclosed herein are relatively inexpensive because, although several small arrays are used, only a single reflector is used, in some aspects of the present disclosure. Further, a relatively large area is not used, as it would be if the usual solution of three reflectors were used. The described solution is also power efficient because only a single reflector is used. The described solution provides a highly compact solution at low cost as well as low-volume. A brief discussion of the receiver is in order. In point to point communication, in FIG. 203, transmission may be in three different sectors. Each sector will be generally seen by a corresponding sector at a receiver, either another reflector or another multiple sector, multiple phased array system. The transmitting sectors are separate. In one aspect, Sector 1 transmits to a matching Sector 1 at a first receiver, Sector 2 transmits to a matching Sector 2 at a second receiver, and Sector 3 transits to a matching Sector 3 at a third receiver. As mentioned above, the beams are quite narrow and the sectors are really well isolated. In other words, the beam is really very narrow, perhaps 3 degrees, but it is scanned, where each triangle of FIG. 203represents a scan. Each sector scan is typically plus or minus 30 degrees. There may be transmission from Cassegrain reflector to Cassegrain reflector, from printed reflector to Cassegrain reflector, from printed reflector to printed reflector or even Cassegrain reflector or printed reflector to multi-antenna array. At the receiver, instead of using a Cassegrain or printed reflector, 4 or 8 smaller arrays can be combined together to create high gain in a multi-antenna array. Any option that has radiated emission holds. Instead of point to point communication (for example base station to base station), the receiver can be a smart phone. The foregoing component/device can be placed in a base station or in a mobile device, such as a smart phone. When placed in a base station, the component/device can be configured with a high gain. When the component/device is placed in a mobile device, the component/device can be configured with a lower gain than that of the base station. The system can be very easily upscaled. To accommodate more sectors or more users, the system can use the same reflector with added feeders, resulting in lower heat dissipation than for solutions without a reflector. Further, each feeder can operate at a different frequency from other feeders. Further, the type of transmission depends on whether or not there is line-of-sight between the transmitter and the receiver. If there is line-of-sight, then transmission is by scanning to the location of the receiver. If there is no line-of-sight to the receiver, then transmission is based on reflection. The disclosed techniques can also be advantageous when the component/device is deployed outdoors. For example, the disclosed component/device can be deployed on a street, e.g., as a base station installed on traffic lights that are subject to vibrations or other environmental factors. In such applications, the system can provide very good tracking to ameliorate the vibration effect of the base station itself, and the base station can then more effectively track a walking user that holds a smart phone. The tracking can include shifting between sectors, particularly when many sectors are supported by the reflector. The effect of the vibration can be ameliorated simply due to the fact that the reflective component/device employs a phased array and the phased array can tune the beam. Therefore, if the vibration is significantly large, or if the smart phone is detected to be in between two sectors, as an example, switching between sectors can aid in alleviating the effects of vibration. Further, even without ameliorating vibration, the scanned beam can follow a walking person who is holding a smart phone and, if signal strength shows a need to switch to different sectors, the system can switch to a different sector. FIG. 205illustrates a package within which antennas may be embodied within a user device, according to some aspects of the present disclosure. Individual packages 41800 and 41802 are illustrated. Items 41801, 41801A include a heat conducting mechanism from the die package onto an external surface. In some aspects of the present disclosure, items 41803, 41803A include a flip-chip chip-scale package (FC-CSP) that has an exposed die with a conformal shielding around it. In other aspects, items 41803, 41803A include a die with a mold and a copper heat spreader. Items 41805, 41805A include a laminate substrate that takes signals from the die onto another board. The laminate substrate can include, for example, a plastic pin grid array (PPGA), a plastic ball grid array (PBGA), and/or any other substrate that is capable of providing communication between the board and the die. In some aspects of the present disclosure, there may be no overmold at all with the die exposed. Item 41807 can include a patch antenna that is fed or excited. Items 41809, 41809A are SMD elements that include antennas printed on any side, such as antennas 41811, 41811A and 41813, 41813A. In some aspects of the present disclosure, there is no electrical connection to the chassis. The signals can be carried from the die to the substrate 41805, 41805A to the board. The board 41806, 41806A has various forms of antennas printed or SMD-mounted as discussed in more detail below. Alternatively, various forms of antennas may be configured within the SMD. The printed antennas and SMD antennas couple to directors like 41815, 41815A in the chassis. Item 41817 can be a ground plane in some aspects of the present disclosure. In some aspects of the present disclosure, either or both of the substrate and the PCB can include heat slugs or heat carrying elements. FIG. 206illustrates a graph of realized gain of a 1x4 dipole array embodied in either package 41800 or 41802 of FIG. 205, according to some aspects of the present disclosure. The realized gain graph 41901 shows the realized gain of antennas at thirty (30) degrees angle with the directors in the chassis fixed in location, but the dipole in the PCB at various heights away from the director, with the heights given in microns on the X-axis of the graph, where “hdipole[um]” indicates the placement height of the dipole in microns. The realized gain graph 41903shows the realized gain of antennas at sixty (60) degrees angle with the directors in the chassis fixed in location, but the dipole in the PCB at various heights away from, the chassis. The realized gain graph 41905 shows the realized gain of antennas at ninety (90) degrees angle with the directors in the chassis fixed in location, but the dipole in the PCB at various heights away. The graph shows that the ideal location is to place the dipole reasonably far away from the director in the chassis, where the realized gains of 41901, 41903, 41905 are generally higher at the left side of the graph (i.e., greater heights along the X-axis) and most of the realized gain graphs (i.e., 41901, 41903) decreasing as the position moves to the right of the graph (i.e., lesser heights along the X-axis). FIG. 207illustrates radiation patterns associated with the graph of FIG. 206, according to some aspects of the present disclosure. In FIG. 207, a dipole is implemented in PCB 42003 or, alternately, implemented as an SMD component. Director 42001 is in or on the chassis, and can be implemented at different heights and depths in the chassis. The grounds and feeding structures in the PCB 42003 are illustrated at 42005. The antenna pattern chart 42007 illustrates at 42009 the antenna pattern as a function of the angle of radiation (along the circumference of the antenna pattern chart 42007) and as a function of the location of the director. If the director is implemented as shown at 42001, then the radiation pattern rotates and one can radiate more in the upwards direction with respect to the orientation of the PCB 42003. The endfire gain of some WiGig products with vertical polarization is very low compared to broadside direction, due to their very small form factor. The endfire gain with vertical polarization has a major importance in coverage for laptop user, for tablet user and for smartphone user scenarios. In some cases, slot elements that have small gain to the endfire direction and larger form factor were used. Monopolar patches which have a good form factor but weak gain to the endfire direction (9 dB lower than broadside) have also been used. The aspect disclosed herein can improve endfire radiation while maintaining a good form factor. The aspect takes advantage of an IC shield structure that is used in the product for shielding integrated and discrete circuitry. The shield is incorporated into a combination of a monopolar stacked patch radiating element and parasitic element, as part of an antenna array. By doing so, the gain of the antenna has been shown to be improved to the endfire direction by 2 dB to 3 dB. The size of elements is also reduced up to 40% while keeping the same bandwidth. While a single parasitic element is described, those of ordinary skill in the art will recognize that in some aspects of the present disclosure it may be appropriate to use a plurality of parasitic elements. The benefit of this combination derives at least in part from the fact that vertical polarization is widely used in modern communications. This is because propagation with vertical polarization suffers smaller attenuation loss than horizontal polarization when propagating along the ground plane of the earth. The receiver and transmitter of a product using the disclosed combination may be aligned to vertical polarization when transmitting to the endfire direction. Such a monopole antenna is a good solution because it has a simple structure while providing the desired vertical polarization. Some monopole antennas use a high profile of quarter wavelengths which is unacceptable in the form factor system limitations often found in wireless communication products. Endfire gain of conventional monopolar patch antennas is small when compared to the 2 dB to 3 dB endfire gain imparted by the described monopolar patch antenna combined with an IC shield structure. FIG. 208illustrates the use of an IC shield as an antenna ground plane and a reflector for a stacked patch antenna, according to some aspects of the present disclosure. In the illustrated aspect, a PCB board 42108 is illustrated as transparent to show the internal structure of the board, which comprises a plurality of parallel layers, some or all of which can be metallized layers. A monopole antenna 42100 including metallized stacked patch antenna elements 42104, 42106 is combined with an IC shield structure 42102, thereby using the IC shield structure as a reflector and as a ground plane. The combination takes advantage of the IC shield, which is in user devices independent of antenna needs. For example, RFEMs such as those illustrated in FIGS. 5A and 5B include a grounded shield, such as 42102 of FIG. 208, covering the IC and discrete components of the RFEM for shielding purposes. The presence of this shield affects radiation patterns and impedance of antennas. Rather than avoid this region of the RFEM and thereby waste space that could otherwise be used for antennas, the shield may be used as a reflector and ground plane as alluded to above to make antennas that are smaller and correctly matched, and to direct radiation patterns in favorable directions. Specifically, a quarter-wave monopole antenna can be printed onto the board in close proximity to the shield. While a quarter-wave monopole is described, those of ordinary skill in the art will recognize that other wavelength monopoles may be used as may be appropriate for a given aspect. The feed point into the monopole can be used to tune impedance similarly to the method discussed below with respect to FIGS. 452B and 452C. Parasitically stacked dual patches 42104, 42106 are used, in some aspects of the present disclosure, to achieve broad bandwidth to meet the bandwidth requirements, such as the WiGig four channels bandwidth requirements. In one aspect, the bottom patch 42106 is the driven element and is excited via a feed line much like that shown in FIGS. 424B and 424C, discussed below. In some aspects of the present disclosure the patch 42104 is a parasitic element. Dimensions are determined by simulation. In the aspect under discussion, the space, in the Z direction in FIG. 209, between driven element 42106 and the parasitic element 42104 is 186 um. In this aspect, the dimension between the patch antenna and the shield 42102 is 165 um as illustrated in FIG. 210A. Simulation has shown that the dimension between the patch antenna and the shield 42102 affects the matching and gain characteristics of the patch antenna. FIG. 210Billustrates that in the aspect under discussion the length of the PCB used by the patch antenna is 1.25mm. FIG. 210Cillustrates that in the aspect under discussion, the patch element 42104 is slightly smaller than the patch element 42106 by 60 um. In another aspect, the antenna elements 42104, 42016 are the same size and the dimension between the patch antenna and the shield is 40 um. The shield 42102, acting as a ground layer and also as a reflector for the excited patch 42106 in FIGS. 208and 209, imparts approximately 2 dB gain to the patch antenna in the endfire direction. Consequently, the patch antenna when operating in endfire direction acts like a monopole antenna. Given the closeness of real estate space in a mobile device, it may be difficult to position the patch antenna close to the shield, but the objective is to place the patch antenna as close to the shield as possible in order to increase the gain in the endfire direction, the distance between the shield and the patch antenna being determinable by simulation. In some aspects of the present disclosure, in endfire operation, polarization can be vertical. In some aspects of the present disclosure, in broadside operation, polarization can be horizontal. Since the vertical polarization in endfire operation is approximately 7 dB to 8 dB below the horizontal polarization in broadside operation of the antenna, the approximately 2 dB to 3 dB gain imparted by the described combination can be an important aspect of improving endfire gain. The proximity of the shield to the patch affects the matching of the antenna and to tune the patch to 50 ohms over bandwidth and narrows the width of the patch which contributes to reducing the antenna size. FIG. 209illustrates a side view of the monopole antenna illustrated in FIG. 208showing an asymmetrical via feeding mechanism, according to some aspects of the present disclosure. Components of FIG. 209which are the same as those in FIG. 208will be given the same reference numerals as in FIG. 208for clarity. The IC circuitry 42202 is indicated as being incorporated below the shield 42102, which is similar to or the same as the shields illustrated in FIGS. 424A-424E, and in other figures that illustrate an IC shield, discussed in detail below. The drawing of FIG. 209is not to scale and the shield 42102 is drawn in partial view. But the shield in the aspects described coversthe IC and shieldsit from RF interference and electromagnetic interference. A more complete illustration of an RF shield is illustrated in FIGS. 454A and 461A. The driven element 42106 is fed by via feeding including via 42201 and feed strip 42203. Vias 42207 in the PCB 42108 are very close to the radiating element 42106. The distance between the vias and the patch can be optimized or improved to maximize the endfire gain as discussed in additional detail below. FIG. 211illustrates shield patch elements in an antenna array configuration with a mobile platform, which may be rectilinear, according to some aspects of the present disclosure. FIG. 211more clearly indicates the relationship of the shield and the monopole patch antenna in an array of such monopole patch antennas along the sides of the shield, as indicated generally at42300. Only the parasitic patch elements 42104 of the array are shown. Dipole Antenna with a Surface Mounted Device that Transitions to a Dipole Antenna with a Monopole Antenna Fig. 212A illustrates a dipole antenna with an SMD antenna that transitions the dipole to a dipole with a monopole, according to some aspects of the present disclosure. In general, and as alluded to in connection with FIG. 208, creating an endfire antenna radiation pattern with both vertical and horizontal polarization has proven difficult. Dipole antennas produce the required endfire radiation pattern, but cannot produce both polarizations. Vertical polarization is preferred for wall reflection characteristics and to match the installed base of docking stations, but the physical orientation of a handheld device cannot be guaranteed. Therefore, it is desirable to provide both polarizations. In some aspects of the present disclosure, to provide both polarizations, the antenna is printed onto an SMD. A surface mounted device is sometimes referred to as surface mounted technology (SMT). The SMD can have standard component dimensions for ease of assembly. The antenna combined here includes a modified dipole 42400 that has both horizontal and vertical polarization radiation. In some aspects of the present disclosure, as will be seen in the next several paragraphs, the antenna begins with a full dipole with both horizontal arms printed on a circuit board. Consequently, the antenna, a dipole at this point, has mostly horizontal polarization. In some aspects of the present disclosure, a vertical arm is added by an SMD, which adds vertical polarization, without reducing the horizontal polarization significantly. Referring to FIG. 212A, a dipole with an SMD configured to transform to a dipole with a monopole is shown generally at 42400. This may be embodied within a mobile device or other device where space is at a premium, for example, by having to meet space requirements for GLONASS. This limited space makes it difficult to design a properly functioning antenna. A PCB board, or other circuit board is seen at 42403 drawn as transparent in order to illustrate components internal to the circuit board. In some aspects of the present disclosure, the antenna includes a dipole 42405, 42407. Also shown is the SMD 42409, to be illustrated in more detail below with respect to FIGS. 212Dand 424E. Metal trace 42411 includes a part of the monopole, also discussed below. Because of space requirements, SMD size “0402” may be used. Generally, the described SMD provides a certain amount of vertical polarization. FIG. 212Bis a perspective view of the dipole portion of the antenna of FIG. 212A, according to some aspects of the present disclosure. FIG. 212Billustrates at 42402 the dipole arms 42405 and 42407 from FIG. 212A, and the beginning portion 42413 of the via 42413, 42413A of FIG. 212A, without the SMD element yet added. Via 42413, 42413A can be seen more clearly in FIGS. 212Dand 212Edescribed in detail below. FIG. 212Cillustrates a combined dipole and monopole antenna, according to some aspects of the present disclosure. In the antenna seen generally at 42404 of FIG. 212C, SMD 42409 has added the monopole, which in some aspects of the present disclosure include the upper trace 42411 if the length of via 42413, 42413A is of insufficient height due, for example, to height limitations in the user device in which the antenna is used. In other words, if simulation shows the antenna arm should be a certain height, which cannot be accommodated by the thickness of the user device, then the trace 42411, in some aspects of the present disclosure, can be added to via 42413, 42413A and “folded” onto the top of the SMD 42409. FIG. 212Dillustrates a perspective view of the monopole part of the antenna of FIG. 212A, according to some aspects of the present disclosure. The antenna is indicated generally at 42406. The shield is seen, again, at 42401. Metallized via 42413, 42413A is illustrated as an antenna arm, and metal trace 42411 functions to extend the arm 42413, 42413A if needed. One horizontal arm 42405 of the dipole is illustrated. Also shown is feed line 42415, which may be a strip line, internal to circuit board 42403. The shield, 42401 seen originally in FIG. 212A, is used as part of a smartphone or other user device, in any event, to shield integrated circuitry, and use is made of the shield both as a reflector for the antenna and also as a way to improve impedance matching. In one aspect the transitioning antenna was located about 1.2 millimeters from the edge of the shield to the center of the via that forms the monopole, and about 0.38 millimeter from the edge of the shield to the edge of the SMD. In practice, the distance is given primarily by how much space is available in the board for the user device, with the objective of trying to maximize the distance. FIG. 212Eis a side view of the antenna of FIGS. 212Aand 212D, according to some aspects of the present disclosure. FIG 212Eillustrates the entire package and illustrates the same components as FIG. 212Bwith additional detail. For example, the feedline 42415 can be seen as being inside the circuit board 42403 where it would be attached to an RFIC (not shown due to space limitations) that would be covered by shield 42401 shown in partial view (also due to space limitations). Feedline 42415 feeds vertical arm 42413, 42413A, which proceeds to the top of SMD 42409 where it is illustrated as including metal trace 42411. 42417 indicates the ground plane for the antenna. Simulated radiation patterns have shown that when placing the SMD component on the dipole element, the combination gives rise to vertical polarization without any significant negative impact to the performance of the horizontal polarization component of the antenna. FIG. 213illustrates a radiation pattern of the antenna of FIG. 212A, according to some aspects of the present disclosure. The x, y, and z coordinates correspond to those illustrated in FIG. 212A. FIG. 214Aillustrates an elevation cut 42600 of the radiation pattern of the antenna of FIG. 212A, according to some aspects of the present disclosure. Radiation pattern 42601 illustrates gain in vertical polarity, radiation pattern 42603 illustrates gain in horizontal polarity. Radiation pattern 42605 illustrates total gain. FIG. 214Billustrates a radiation pattern 42602 of the antenna of FIG. 212B, according to some aspects of the present disclosure. The antenna of FIG. 212Bis without the SMD part of the monopole and the radiation pattern is essentially that of the dipole 42405, 42407 of FIG. 212B, seen at 42605 of FIG. 214B. SMD L-Shaped Dipole with Shield Reflector An L-shaped dipole with backed shield is described below. FIG. 215Aillustrates a side view of an SMD L-shaped dipole with an IC shield used as a reflector, according to some aspects of the present disclosure. The dipole is seen generally at 42700. A single ended feed line 42701 from IC circuitry (not shown) that is shielded by the IC shield 42703 feeds the vertical section 42705 of the dipole. Vertical section 42705 continues as vertical section 42705A (that is within SMD 42708), vertical sections 42705, 42705A being connected by solder joint 42711, and the vertical sections 42707, 42705A, and the solder joint forming a vertical arm of the dipole. Ground 42704 of FIG. 427A is extended to act as the second arm of the dipole 42707, thus forming an L-shaped dipole (seen more clearly in FIG. 215Bas will be discussed in greater detail below). The IC shield is a conformal cover over IC that is on the board of a mobile device. The shield is usually grounded to the board as a shield from electromagnetic interference. An L-shaped dipole such as that described, combined with a backed shield, can radiate with a larger gain to the endfire direction (seen diagrammatically in FIG. 215B) than the standard patch element. In some aspects of the present disclosure, the L-shaped element 42705, 42705A, 42707 (where 42505A is seen in cutaway side view in FIG. 215Aas being internal to the SMD 42708) takes advantage of the area near the shield and the board height. The usual dipole has two horizontal arms. However, the dipole illustrated in FIG. 215Bhas one horizontal arm 42707 and one vertical arm 42705, 42705A. Part of the vertical arm 42705 of the dipole is in the board (where the excitation is located) and part 42705A is in the SMD 42708 to enable lower board height as may be needed. The metalized via 42705A in the SMD 42708 acts as a second dipole arm being folded up into the SMD 42708 to form a folded dipole. In other words, the two arms of the dipole are each in different planes. For example, the two arms of the dipole are each in orthogonal planes. This gives rise to two different polarizations, vertical from the vertical arm and horizontal from the horizontal arm. In some aspects of the present disclosure, the vertical arm 42705, 42705A may go entirely through the SMD 42708 and extend to the top 42709 of the SMD 42708. If, as it may happen, the height of the SMD 42708 is not electrically sufficient for the needed length of arm 42705A, for a given aspect, a horizontal metal trace, such as copper, may be added to 42705A (now extending to the top layer 42709 of the SMD 42708) as a horizontally folded extension of arm 42705A. This horizontally folded extension, or trace, extends from the via, at the top 42709 of the SMD 42708, much like metal trace illustrated at 42411 in FIG. 212A. This metal trace can be used to extend the vertical arm 42705, 42705A. In some aspects of the present disclosure, the SMD may be mounted onto the PCB using a land grid array pad (LGA Pad) seen in FIG. 215B, where the SMD 42709 is seen as attached via solder 42711. In other words, the dipole comprises two arms, one, a horizontal trace, such as copper, that forms horizontal arm 42707, being in the PCB and one, a vertical arm 42705A, being in the SMD 42709. As illustrated, one metallized horizontal arm of the dipole is from the ground 42704 and one metallized vertical arm, or metalized via in this instance, is in the SMD. In some aspects of the present disclosure, the width/diameter of the metallized via 42705A, which may function as a metal trace, has substantially the same width as the width of the horizontal trace 42707 that forms the horizontal arm of the dipole. Consequently, the vertical metallized via looks electrically as if it is the other arm of the dipole. In summary, the shield is seen as 42703 in FIG. 215Aand in FIG. 215B. The shield serves as a reflector for the dipole that comprises metallized horizontal arm 42707 from ground seen in FIG. 215Band metalized vertical (or folded) arm seen as via 42705, 42705A in FIG. 215A. The vertical arm is fed by feed line 42701 of FIG. 215A. In other words, the horizontal arm is ground and the vertical arm is signal-fed by the feedline from the IC. The PCB generally includes a plurality of layers. In some aspects of the present disclosure, the horizontal arm 42707 can be formed by removing metal from all layers in the area around the dipole except for the metal that forms the horizontal arm 42707, leaving horizontal arm 42707 as one arm of the dipole, the vertical arm 42705, 42705A forming a second arm of the dipole. SMD 42709 can be affixed to the PCB by solder 42711. While solder 42711 represents a discontinuity in the vertical arm, it has been seen that the solder does not hinder intended operation in any substantial way. FIG. 215Billustrates a perspective view of the SMD L-shaped dipole 42702, and illustrates more clearly that arm 42705, 42705A is partly within the SMD 42709 and that the arm 42705, 42705A is folded upward with respect to horizontal arm 42707. SMD L-Shaped Dipoles Symmetrical Array In some aspects of the present disclosure, an L-shaped dipole array can be configured to provide high gain to the endfire direction, with polarization diversity. FIG. 216illustrates a perspective view of an array of four of these SMD L-shaped dipoles, according to an aspect. While the array is described as comprising four L-shaped dipoles, such an array is not limited to four L-shaped dipoles but could be any appropriate number of L-shaped dipoles. The array is seen generally at 42800. Each individual L-shaped dipole element 42801, 42803, 42805 and 42807 may be of the type discussed with respect to FIGS. 215Aand 215B, above. Each such L-shaped dipole has a horizontal arm 42707 and a vertical arm 42705, 42705A internal to the SMD as discussed with respect to FIGS. 215Aand 215B. Each is situated with respect to shield wall 42802, also as discussed with respect to FIGS. 215Aand 215B. The X, Y, Z coordinate system for the array is as illustrated in FIG. 216. The shield 42802 has a shield extension which is discussed later in this patent. Each dipole element of the array, in some aspects of the present disclosure, has an RF chain input, dipole 42801 having RF chain 1 as an input, dipole 42803 having RF chain 2 as an input, dipole 42805 having RF chain 3 as an input and dipole 42807 having RF chain 4 as an input. The shield 42802, as the other shields illustrated in various figures herein, is only partly illustrated due to drawing space considerations. In practice the shield would extend to cover an IC, in this case an IC that provides RF chain 1, RF chain 2, RF chain 3 and RF chain 4. The four L-shaped dipole elements form a linear array in the described aspect. In some aspects of the present disclosure, the direction of the horizontal arm of the L-shaped dipoles is purposely arranged to be opposite in adjacent pairs of the L-shaped dipole antenna elements in order to achieve a certain field cancellation/addition between the elements for a given input phase of the respective RF chains. In the figures that follow in the description of this aspect, dipole array elements under discussion will be dipole elements 42801, 42803, 42805 and 42807 of FIG. 216and their respective horizontal arms will be referred to as horizontal arms 1, 2, 3 and 4, respectively, of FIGS. 217Aand 217B. FIG. 217Aillustrates the array of FIG. 216for vertical polarization, with the horizontally polarized fields cancelling out, according to some aspects of the present disclosure. In FIG. 217Afor the horizontal arms 1, 2, 3 and 4, the fields that arise from RF chains 1, 2, 3 and 4, respectively, cancel out. This is because for the horizontal arms 1, 2, 3 and 4, since they are arranged in respectively opposite (left/right) directions, as indicated by the arrows, the current flows in opposite directions, and thus the generated radiated fields cancel each other out. FIG. 217Billustrates the array of FIG. 216for vertical polarization, with the vertically polarized fields adding up, according to some aspects of the present disclosure. In FIG. 217B, for the vertical arms of dipole antenna elements 42801, 42803, 42805 and 42807 (illustrated in vertical hidden line), since they are arranged in the same directions (up, as indicated by the vertical arrows) the current flows in the same direction, and thus the generated radiated fields, add up. Consequently, vertical polarization is achieved. Stated another way, to obtain vertical polarization, vertical mode (0⁰, 0⁰, 0⁰, 0⁰) is being used in which the fields radiated by the horizontal arms cancel each other and the fields radiated by the vertical arms add up. FIG. 218Aillustrates the array of FIG. 216for horizontal polarization, with the horizontally polarized fields adding up, according to some aspects of the present disclosure. For horizontal arms 1, 2, 3, and 4, even though they are arranged in opposite directions (left/right) the opposite phases of signals from the respective RF chains 1, 2, 3 and 4 make the currents flow in the same direction, and thus the radiated fields add up. FIG. 218Billustrates the array of FIG. 216for horizontal polarization, with the horizontally polarized fields cancelling out, according to some aspects of the present disclosure. For the vertical arms of dipole antenna elements 42801, 42803, 42805 and 42807, even though they are arranged in the same direction (up, as indicated by the vertical arrows), the opposite phases of signals from the respective RF chains 1, 2, 3 and 4 make the currents flow in the opposite direction, and thus the vertically polarized radiated fields cancel out. Consequently, horizontal polarization is achieved. Stated another way, for horizontal polarization horizontal mode (0⁰, 180⁰, 0⁰, 180⁰) is being used, where the radiated fields from the vertical arms cancel and the radiated fields from the horizontal arms add up. FIG. 219illustrates a three-dimensional radiation pattern for vertical (theta) polarization, according to some aspects of the present disclosure. The illustrated three-dimensional radiation pattern of energy radiated by the L-shaped dipole array when vertical polarization mode (phases are 0o, 0o, 0o, and 0o). The realized gain for the vertical component of the electric field (E-theta) has been simulated, with a maximum of 7.43 dB. FIG. 220illustrates a radiation pattern for horizontal (phi) polarization, according to some aspects of the present disclosure. The illustrated three-dimensional pattern of energy radiated by the L-shaped dipole array when in horizontal polarization mode (phases are 0o, 180o, 0o, and 180o). The realized gain for the horizontal component of the electric field (E-phi) has been simulated, with a maximum of 7.14 dB. The aspectof the disclosure in FIG. 216not only takes advantage of limited space in a mobile device, but it also expands the uses of available RF chains. For example, if there are only four RF chains available (as illustrated) and ideally the system would use eight available RF chains so that the system could transmit four vertical polarization RF chains and four horizontal RF chains, a resolution is desirable. By using the described L-shaped dipole, one RF chain is effectively converted to two RF chains. Consequently, if limited space allows only a four antenna array and also the available chains from the circuitry are only four RF chains, the array of four L-shaped dipole antenna elements provides four vertically polarized radiating elements and four horizontally polarized radiating elements, thus yielding the desired eight elements. A four antenna array is used as an example, and those of ordinary skill in the art will recognize that additional numbers of antenna elements can be used in antenna arrays as may be appropriate for a given aspect. Furthermore, if a multiple of four RF chains is available from the circuitry that is covered by the IC shield, double the number of total effective RF chains could be achieved. For example, if the multiple of four RF chains were available in a rectangular or square sub-system, a number of L-shaped dipole arrays could be placed around the circuit sub-system, on top of the sub-system and, if desired, on the bottom of the sub-system, for feeding the individual RF chains to respective antennas. Thus double the multiple of four radiating elements could be achieved. In some aspects of the present disclosure, an SMD monopole can be used as an antenna by itself, thus achieving fully (or substantially fully) vertical (θ) polarization with a single element. Some conditions that allow an SMD monopole antenna to achieve fully vertical polarization are that the monopole has vertical polarization because of its orthogonal position in relation to the surface of an RFEM when used in a user device with an RFEM (or a feature that is equivalent to an RFEM). Furthermore, the placement of the feed of a monopole with respect to an IC shield, which acts as a reflector, is important. The shield’s function is to reflect the radiated energy in the desired direction, in this case, endfire. The shield is not intended to have an impact on the polarization of the radiated fields. FIG. 221illustrates a single SMD monopole Antenna 43303 and IC shield 43301, according to some aspects of the present disclosure. The IC itself is not illustrated due to space considerations but would be to the left of, and covered by, IC shield 43301, which is illustrated in partial view. The SMD monopole 43300 may include two parts: (1) a via element 43307 built on the edge of the RFEM package 43305, and (2) a via element 43307A, which may be a copper via, built within the SMD component 43303. Via 43307 realizes the bottom part of the monopole and via element 43307A realizes the top part of the monopole. The SMD may be soldered on the RFEM package using two pads: one, at the location of via 43307 for the signal and one, a dummy pad (not shown) for mechanical stability. Copper (or other metal) trace 43309 may be printed on the top layer of the SMD to extend the total length of the monopole as needed. The foregoing description of using two pads, and the other details recited are used merely as an example and those of ordinary skill in the art will recognize that these details may be changed as may be appropriate for a particular aspect. For example, trace 43309 may be used for tuning purposes if the via 43307, 43307A is not long enough because, among other things, of height limitation in the user device in which the monopole is situated. Stated another way, if the height of via 43307, 43307A is not sufficient to meet the requirements of tuning the antenna to a desired transmit frequency, the trace 43309 would be of appropriate length to add the required height to via 43307, 43307A, even though the trace is folded horizontally onto the top of SMD 43303. In some aspects of the present disclosure where via 43307, 43307A is of sufficient height, the trace 43309 may not be needed. In some aspects of the present disclosure, the SMD monopole 43300 may be fed with a stripline or other transmission line 43311 from the RFEM package. FIG. 222illustrates a three-dimensional radiation pattern, according to some aspects of the present disclosure. FIG. 222illustrates the radiation pattern of the single monopole at 60 GHz. FIG. 223illustrates an impedance plot of a single monopole, according to some aspects of the present disclosure. The impedance plot is represented on a Smith Chart and at 60 GHz the plot 43501 is near the center point, meaning the antenna is well matched. After calculating the length of the monopole based on the wavelength in the dielectric material at the frequency of interest, and similarly calculating the dimensions of the stripline or other transmission line feedline; iterative 3D simulations taking into account manufacturing constraints as well as the limited space available and distance of the shield, are performed to achieve the antenna impedance matching. FIG. 224illustrates the return loss of a single monopole over frequency, according to some aspects of the present disclosure. The plot shows that the antenna is well matched at 60 GHz and that it has an impedance bandwidth from 56.56 GHz to 66 GHz. FIG. 225illustrates realized vertical polarization gain (θ) in the X-Z plane from a single monopole, according to some aspects of the present disclosure. FIG. 225is a two-dimensional plot at 60 GHz and shows the vertical component of the electric field (E-theta) is dominant. The realized gain in the endfire direction is 3.33 dB. The traces represent the realized gain on the X-Z plane for a different polarization of the E-field. The endfire direction is ninety (90) degrees on this plot (which represents the positive x axis of the coordinate system on FIG. 221). FIG. 226illustrates realized vertical polarized (θ) gain over frequency, at 15o above endfire, from a single monopole, according to some aspects of the present disclosure. The realized gain for the E-theta component of the electric field is seen at 43803. Given that antenna polarization of a transmitting system and a receiving device may substantially match for good connection, the purpose of having dual polarization is to be able to maximize the transmission from a transmitter to another device (e.g., a dock, peripheral, or smartphone, and the like). The user device, such as a smartphone, with an RFEM similar to that described above, may be moving and changing its orientation with relation to the transmitter. Thus, the option for either polarization is used in an effort to provide good connection regardless of the relative position of the transmitter and receiver. In some aspects of the present disclosure, transmitted polarity, and therefore which type of antenna is firing at a given time, may be algorithmically controlled based on an indication of the polarity of the signal received with greatest strength. This indication can be continually being fed back to the transmitter from the user device. This operation is implemented to achieve transmitted polarization that matches the polarization at the receiver. In some aspects of the present disclosure, different array combinations can be implemented depending on the area available in a user device. In some aspects of the present disclosure, polarization diversity can be achieved in the endfire direction using an array of two monopoles for vertical (θ) polarization and an array of two dipoles for horizontal (Φ) polarization, with a total of 4 feed lines such as from four RF chains such as seen in FIG. 216, discussed above. Each array can be configured to operate at a given time. Parameters described in FIG. 227below, such as two monopoles for vertical polarization and two dipoles for horizontal polarization, are given by way of example only, and those of ordinary skill in the art will recognize that a different number or plurality of such antennas may be used as may be appropriate for a particular implementation. FIG. 227illustrates a two-element monopole and a two-element dipole array, according to some aspects of the present disclosure. FIG. 227illustrates a top view, 43900, of the two arrays. As discussed above, IC shield 43901, of which part of the top is illustrated in top view, is used as a reflector to provide additional gain in the desired direction. The IC itself would be covered by the shield and would be located toward the top of the drawing of FIG. 227beyond and coveredby the shield but is not illustrated due to space considerations in the drawing. A first array comprises monopole 43903 and monopole 43905. Monopoles 43903 and 43905 can be the same type of monopole discussed with respect to FIG. 221. Because the arrays are illustrated in top view, the signal connection for monopole vertical arm 43307, 43307A of FIG. 221can be seen at 43903A of FIG. 227and the dummy pad discussed above with respect to FIG. 221is seen at 43903B of FIG. 227for support purposes. Those of ordinary skill in the art will recognize that support can be provided other than by a dummy pad placed as illustrated. The two monopoles are fed, respectively, by feed line 43907 and feed line 43909. In some aspects of the present disclosure, dipoles 43911 and 43913 are printed on the RFEM package layers. The corners of the dipole arms are folded up in some aspects of the present disclosure in order to increase their length but to avoid interference with other metals around them, including coaxial connector 43915 which causes very limited space for the antenna arrays. Only one of the four folded upward dipole arms is enumerated, as 43911A, but the upward fold is typical for all four dipole arms in the aspect under discussion. In one aspect, the array has the dimensions illustrated on FIG. 227. The ground plane (GND) is on one of the layers of substrate 43902. The substrate 43902 is illustrated in partial view but in practice would be extended beyond the borders of 43902 illustrated in FIG. 227. The monopoles are at a certain distance from the shield, and the dipoles need to be at a certain distance from the GND plane for improved operation. Also, the distance between the elements of the array (dipole to dipole and monopole to monopole) is designed for improved performance given the limited area available. The dimensions discussed above may be determined using a simulation application and inputting into the application the dimensions that are available in the user device, and judging from simulation results the appropriate dimensions to obtain desirable results, which may be desired radiation directivity and other parameters. FIG. 228illustrates a three-dimensional radiation pattern of a two-dipole array at 60 GHz, according to some aspects of the present disclosure. In this aspect the total realized gain is measured with a maximum gain of approximately 4.16 dB. The direction +Z for the pattern is toward the bottom of the board as illustrated in FIG. 227. FIG. 229illustrates realized horizontal polarity (Ø) gain over frequency in the endfire direction from the two-dipole array of FIG. 227, according to some aspects of the present disclosure. The realized gain for the E-phi component of the electric field is shown at 44101. FIG. 230illustrates a three-dimensional radiation pattern of the two-monopole array of FIG. 227at 60 GHz, according to some aspects of the present disclosure. As with FIG. 228, the +Z direction is toward the bottom of the board. FIG. 231illustrates the realized vertical polarity (θ), according to some aspects of the present disclosure. The realized gain for the E-theta component of the electric field is shown at 44301. Multiple SMD Antenna Aspects Some general information applies to FIGS. 232-235, which are discussed below in greater detail. The length of the patch antennas discussed is typically λg/2 where λg is the wavelength in the dielectric. For a 60 GHz antenna on the dielectric materials that we’re using (for example, with dielectric constant of approximately (~) 3) that length is approximately 1.2 mm. The width of the patch antenna is slightly larger than the length; however, for a dual feed / dual polarized antenna, the width and length should be both the same (~1.2 mm). Another important dimension for the patch antennas is the thickness of the dielectric between the patch and the reference ground, and the thickness of the dielectric between the main and the parasitic patch (if a parasitic patch is present). The following are relevant factors. The thickness of the dielectric (in combination with the material properties) is directly related to the impedance bandwidth of the antenna. For example, as a reference point for WiGig (60 GHz), a bandwidth of ~8 GHz is desirable. For a solution with a single patch (for example, a main patch), the thickness of the dielectric should be ~ λg/10. If a wide bandwidth is desirable, such as in WiGig, the thickness should be ~300 um. For a solution with a parasitic patch (for a single + parasitic), the total thickness should be ~ λg/10 (in other words, adding the thickness of the dielectric between ground and main patch, plus dielectric between main and parasitic patches.)Which one is thicker depends on the dielectric constant of each dielectric material. The concept is that the main patch is more tightly coupled to the ground. In the case of FIG. 233, discussed generally in additional below, since the shield acts as ground reference, the dielectric between ground and main patch is just air. The following are relevant factors for the distance of the shield from the SMD in FIGS. 232-235, also discussed generally in additional detail below. For the aspects of the disclosure in FIGS. 232and 235, the distance of the shield from the SMD can be as close as manufacturing allows. For the aspect in FIG. 233, the distance of the shield from the SMD should follow the rule described above for thickness of the dielectric between ground reference and the main patch. For the aspectin FIG. 234, that distance depends on the intended direction of the radiation. The distance should be as far as possible for broadside radiation, and as close as possible for endfire radiation. Generally, the distance will be somewhere in between those two extremes. For the aspect in FIG. 236, the distance should be as far as possible, given the available space (space available being a limiting factor for essentially all the aspects described herein). This applies for both single and dual polarization. FIG. 232illustrates a single patch, dual feed, dual polarization vertical SMD patch antenna, according to some aspects of the present disclosure. In FIG. 232, a PCB is seen at 44401. RFIC shield 44405, which covers the RFIC 44403, can be configured to operate as a reflector for patch antenna 44409. In some aspects of the present disclosure, patch antenna 44409 is etched or otherwise configured on the face of the SMD 44407 adjacent director 44417 as illustrated. The patch antenna 44409 may be folded or non-folded. In other words, a patch antenna, such as at 44409, can wrap-around from the side of the DMC to the bottom, providing extra length if needed, as explained for above aspects. Ground that is etched or otherwise situated on the SMD is illustrated at 44411. Stated another way, ground 44411 in some aspects of the present disclosure can be on the side, as illustrated, and can, as needed, wrap-around as illustrated. In some aspects of the present disclosure, patch antenna 44409 is fed by dual feed lines 44413 on the board and 44415 within the SMD multilayer component, to connect the appropriate feed from the board to the appropriate SMD layer. Microvia 44416 extends from at or near the bottom of the SMD 44407 to an intermediate height within the SMD component, and is followed by a line in the device (i.e., upper line 44415) which feeds, and connects to, a location in the patch antenna and which (in combination with lower line 44415) makes the antenna function as a dual polarized antenna. In some aspects of the present disclosure, director 44417 is etched or formed on the chassis of the user device, such as a phone, laptop, and the like, to direct the radiation in direction 44419 to a receiver. FIG. 205, discussed above, illustrates chasses with placement of directors. Because the antenna is dual and orthogonally fed, it provides dual polarization in two orthogonal directions, the direction depending on which of the dual feeds is selected. In some aspects of the present disclosure, selection of which feed to use at a given time may be controlled by a controller to enable the antenna to provide one or the other polarization as needed, depending on the strength of the received polarized signal at the receiver. In some aspects of the present disclosure, the strength of received polarized signal at the user device is fed back for feed selection by the controller. This allows the controller to select the feed that provides the polarization capable of providing a stronger received signal, thereby improving overall performance. FIG. 233illustrates a stacked patch, single feed, single polarization vertical SMD patch antenna, according to some aspects of the present disclosure. In FIG. 233, a PCB is seen at 44501. RFIC shield 44505, which covers the RFIC 44503, acts as a reflector and ground reference for patch antenna 44509. Patch antenna 44509 is etched or otherwise configured on the illustrated face of SMD 44507. The patch antenna may be folded or non-folded. The patch antenna illustrated at 44511 is a parasitic element. Additional parasitic elements may be used for FIG. 233, and for the additional SMD illustration figures described below, as may be appropriate for other aspects. Patch antenna 44509 is fed by a single feed line 44513 on the board. Director 44515 is etched or formed on the chassis of the user device to direct the radiation in direction 44517. Because there is only a single feed, there is only a single polarization. FIG. 234illustrates a horizontal SMD patch antenna, according to some aspects of the present disclosure. In FIG. 234, a PCB is seen at 44601. RFIC shield 44605, which covers the RFIC 44603, acts as a reflector for patch antenna comprising driven capacitive patch antenna 44609 and parasitic patch antenna 44615. There is also ground layer 44611 within the PCB that acts as a ground reference for the primary capacitive patch 44609. Ground 44611 is not drawn to scale. The ground is much larger than the patch itself. In some aspects of the present disclosure the ground may be the entire area of the PCB. In some aspects of the present disclosure, capacitive patch antenna 44609 is etched or otherwise configured on the illustrated face of SMD 44607. The patch antenna may be folded or non-folded. Patch antenna 44609 is fed by dual feed lines 44613 on the board. Because there are dual feeds, there may be dual polarization, both vertical and horizontal polarization which may be algorithmically controlled as discussed above. FIG. 235illustrates a vertical SMD patch antenna 44708 using a cross-hatch pattern, according to some aspects of the present disclosure. In FIG. 235, a PCB is seen at 44701. RFIC shield 44705, which covers the RFIC 44703, acts as a reflector for patch antenna 44708. The ground reference, in some aspects of the present disclosure, is the cross-hatch pattern 44710 on the opposite side of SMD 44707, and extends down to the bottom layer of the PCB. Patch antenna 44708 may be a capacitive patch made using high density cross-hatch copper traces and microvias. Such a pattern can be implemented within the body of the SMD 44707 component and within the main host PCB 44701. The cross-hatch SMD component can be connected using multiple solder points 44709A and 44709B. The patch antenna 44708 may be folded or non-folded. Patch antenna 44708 is fed by dual feed lines 44713 on the board which should be two, orthogonal feeds for dual polarization. Director 44711 is etched or formed on the chassis to direct the radiation in direction 44719. FIG. 236illustrates an SMD spiral antenna with circular polarization, according to some aspects of the present disclosure. In FIG. 448, an RFIC 44803 is connected to PCB 44801. RFIC shield 44805 covers the RFIC 44803, acts as a reflector and ground reference for the spiral antenna 44809. Spiral antenna 44809 may be made using vias and traces on the top and bottom layers of the SMD 44807. If SMD 44807 is multilayer, then the spiral antenna could be implemented using vias and traces in the inner layers of the SMD 44807. Spiral antenna 44809 is fed by a single feedline 44813 on the board. Director 44813 is etched or formed on the chassis to direct the radiation in direction 44815. FIG. 237illustrates the implementation of a spiral antenna within an SMD, according to some aspects of the present disclosure. An RFIC is seen at 44903, or in some aspects of the present disclosure 44903 may designate a PCB that holds the RFIC. Traces 44907 may be printed on top and bottom of SMD 44905. Also, vias 44909 may be placed between top and bottom of the SMD to connect the traces as illustrated. While not circular, as spirals are often illustrated, the illustrated trace-via combination may act as one circular or oval loop of a spiral. A plurality of such loops may be connected together to function as circular loops. Note that the bottom trace 44907 is left open (not connected to via 44910) and may be connected to a second loop which may similarly be connected to a third, and so on, to form a spiral. For example, if the SMD component is multilayer, then trace loops and connecting vias may be constructed on inner layers, allowing more turns of the spiral. Via 44911 is connected to single strip line feed 44915 within the RFIC 44903. Vias 44909 are ground vias to stitch the GND layers that reference the strip line feed 44915. FIG. 238illustrates coupling radiation from an RFIC to a plurality of directors on a chassis, according to some aspects of the present disclosure. Illustrated is PCB 45001 with attached RFIC 45003. Four SMD components 45005 each include an antenna element such as those illustrated in FIGS. 232-235, are spaced at an adequate distance from each other for gain versus size, and are fed by feed mechanisms 45007 from RFIC 45003. Feed mechanism 45007 may be a single feed, single polarization feed mechanism, or a dual feed, dual polarization feed mechanism, each as respectively discussed above. As also discussed above in this patent, distance and other parameters are a function of space available in the device in which the antenna finds use. Distances and other parameters may then be determined, in many cases, by simulation, inputting the available distances or distance ranges, angles, and other parameters, into simulation software and determiningwhich set of distances, angles, gain, radiation pattern, and other parameters provide desirable results, also illustrated are four target features 45011, such as directors, on the device chassis 45009. The SMD components 45005 may represent a 28 GHz antenna array, each antenna element fed by RF signals of the same polarization. Illustrated by wavy lines at 45013 is an indication of the radiation between the SMD components and the target features. Spacing between the SMD components and the chassis features would be in the order of 0.5 mm to 1.0 mm. at 28 GHz. In this aspect, the antenna elements are SMD components, however they could also be realized on the PCB. As discussed above, RF sub-systems such as RFEMs, RFICs and the like use a shielding to protect from radio frequency interference (RFI) and electromagnetic interference (EMI). The shieldings are metallized and usually form a box to cover the active die placed within it. Described below are cutouts from the shielding, in various forms and patterns, that create antenna structures either as slot lines or as active metal line antennas that would be connected to the RFIC inside the shielding either through a metalized trace or through another suitable type of coupling mechanism. FIG. 239Ais a perspective view of an IC shield wall cut-out that forms an antenna, according to some aspects of the present disclosure. The IC shield 45100 is illustrated in a perspective view with a shield cover that is not shown. The top of the PCB to which the IC Shield is affixed indicated at 45113. In FIG. 239A, item 45113 appears away from the top of the PCB. However, this is merely because of lack of drawing space. Item 45113 is the top of the PCB on which the RFIC die is located. The shield may be affixed to the PCB by solder. Point 45115 illustrates a gap or opening. Theseare typical around the four corners of the top of the PCB, in some aspects of the present disclosure. RFIC die 45101 is also affixed to the PCB 45113, which in some aspects of the present disclosure may be by solder as indicated by solder balls at the bottom of RFIC die 45101. Two of the shield walls are visible, each marked “SHIELD WALL” and a third shield wall is visible in dash line. Consequently, the inside of the IC shield is visible. A cutout in shield wall 45103 is visible at 45105 and continues to the bottom of the shield wall at the PCB and functions as an antenna. This cutout forms wall element 45107 as an antenna which, in this aspect, is a planar inverted F antenna (PIFA). As indicated below, a PIFA is merely one example of the antennas that can be cut out of the shield and the aspects are not limited to using a PIFA. In the aspect under discussion the PIFA antenna is the cross-hatched section 45107 in FIG. 239A. It is metalized. The cutout is around PIFA 45107 is 45105, in two sections, which is not cross-hatched. So the metallization that forms the PIFA 45107 is shown in a diagonal lined section in the drawing. In FIG. 239Bthere is no surrounding metal illustrated around the PIFA antenna 45107 above the GND plane edge line, for clarity of illustration. But in FIG. 239Athe PIFA 45107 is illustrated as it appears, within the side of shield within a cutout 45105. In some aspects of the present disclosure, wall element 45107 may terminate at the PCB at feed transmission line 45111 that connects to appropriate transceiver circuitry of RFIC die 45101 and feeds the antenna that is formed by the cut-out 45105. Various types of feed mechanisms may be used, such as the coplanar waveguide shown, or micro strips, and the like. Transmission line 45111 may be formed on the floor 45113 of the PCB by removing metal to expose segments 45112 that isolate transmission line 45111 from, ground GND. As illustrated in FIG. 239A, the feed line 45111 is partially on the PCB and partially on the shield wall 45103 metallization leading to the PIFA 45107. In FIG. 239Athe vast majority of the transmission line 45111 is on the PCB on which the RFIC die is located, in some aspects of the present disclosure. The cross-hatch line filled area 45111 is metallized transmission line on the PCB, while only a small section of the transmission line is located on the shield wall. In other words, the cross-hatch lined filled areas 45107 and the rest of the shield wall 45103 (other than 45105) are metallization on the shield metal. The PIFA antenna 45107 is formed within a metallization free cutout 45105 in the shield wall in this example. On either side of the transmission line 45111, the areas 45112 are areas in which the PCB metallization was removed (delaminated) on either side 45112 of the feed line 45111 to make 45111 into a transmission line feeding the PIFA. This delamination is usually done by etching on PCB. Scraping instead of etching is possible but not considered accurate. The delamination may also be accomplished by machining or other mechanical cutout mechanisms on the shield metal. The feed line can be implemented using multiple technologies and not limited to one technology (e.g., on a PCB). An element 45109 of the wall that is adjacent to the cut-out 45105 connects to ground GND of the PCB and functions as a shorting line to ground for the cut-out antenna 45107. In some aspects of the present disclosure GND functions as a ground plane for the antenna formed by the cut-outs. FIG. 239Bis a side view of the wall cut-out that comprises the antenna illustrated in FIG. 239A, according to some aspects of the present disclosure. FIG. 239Bshows a planar inverted F antenna (PIFA) with elements 45105, as well as wall elements 45107, 45109 and feed transmission line 45111 being the same as the like-numbered elements in FIG. 239A. A PIFA is used in this aspect primarily because it presents a relatively simple way to connect an antenna to ground GND by way of wall element 45109, and also because of its known resonance at a quarter-wavelength, which reduces required space needed in the user device, and also because it has good signal absorption rate properties. In operation, feed transmission line 45111 is configured to feed the antenna element residing in cut-out 45105 which functions as an antenna, radiating RF energy outward from shield wall 45103. In some aspects of the present disclosure, such as the PIFA illustrated at 45107, the radiation may be substantially omnidirectional. The cut-out and antenna element may be in the form of other configurations, such as a notch or slot, or a patch with appropriate grounding. FIG. 239Cis a perspective view of an IC shield with a wall cut-out and a top cut-out that comprise antenna elements of an antenna array, according to some aspects of the present disclosure. In FIG. 239Cthe walls are seen typically at 45103 and the top is seen at 45106. Consequently, the perspective view of FIG. 239Cillustrates the IC shield covering RFIC 45101 that is shown in hidden view as being under the cover 45106 of the IC shield. The cut-out on top 45106 is seen at 45105A with wall element 45109A providinga path to ground by way of the PCB. Cut-out 45105A in FIG. 239Cfunctions as an antenna and is substantially the same type of antenna as cut-out 45105 of FIG. 239A, that is shown in hidden view in FIG. 239C. Feed transmission line 45111A shown in hidden line feeds antenna 45109A from RFIC 45101, and is the same as or simpler to feed transmission line 45111 in hidden view. In some aspects of the present disclosure, two or more antennas can be oriented orthogonal to one another. For example, two antennas 45105 and 45105A being substantially physically orientated orthogonal to each other support two different polarizations and/or spatial coverages. Each antenna can be fed with either the same signal to create a new vector summation or with two different signals or spatial streams to enable Multiple in Multiple Out (MIMO) modes of operation. When fed at different times, radiation can be caused at two different polarizations at different times, depending on the control configuration, as discussed above. In some aspects of the present disclosure, selection of which feed to use at a given time may be controlled by a controller to enable the antenna to provide one or the other polarization as needed, depending on the strength of the received polarized signal at a receiver to which the signal is transmitted. In some aspects of the present disclosure the strength of received polarized signal at the receiver is fed back for feed selection by the controllerto select the feed that provides the polarization, vertical or horizontal, that provides the stronger received signal at a given time. The feedback can be provided continuously, thereby continuously providing the appropriate polarization and improving overall performance. In some aspects of the present disclosure, both feeds are used to decipher MIMO signals having spatial orthogonality. FIG. 239Dis a perspective view of an IC shield with a first wall cut-out and a second wall cut-out that comprise antenna elements of an antenna array, according to some aspects of the present disclosure. The IC shield 45106 in FIG. 239Dis the same as that illustrated at 45100 in FIG. 239A. However, the shield has a second cutout 45105A including feed transmission line 45111A situated with respect to the die in the same manner as cutout 45105, and feed transmission line 45111. Because the shield is rectangular the two cut-outs 45105 and 45105A are orthogonal to each other and operate in the same manner as discussed with respect to FIG. 239C. Other implementations such as two orthogonal cut-out antennas on the top of the shield with similar feed mechanisms as those described, and other implementations, are possible. In a RF system, the antenna is connected to a transmit/receive (T/R) switch and then connected to the power amplifier (PA) and low noise amplifier (LNA) in the TX and RX chains, respectively. At mmWave frequencies, the loss associated with such a T/R switch is high and painful from the RF performance point of view. RF lineup and antenna feeding network (for both single and dual polarization) are shown for square patch antenna in FIGS. 240Aand 240B. However, this can be applicable to other types and shapes of antenna implementations. FIG. 240Aillustrates a patch antenna and RF feed line connection including a transmit/receive (TR) switch for a single polarization design, according to some aspects of the present disclosure. In FIG. 240A, patch antenna 45201 has feed line 45203 connected at a match point 45205, discussed in additional detail below. Antenna 45207 is the same as patch antenna 45201, feed line 45203, in a transceiver is attached to T/R switch 45209. PA 45211 and LNA 45213 are each connected to T/R switch 45209 as illustrated and the T/R switch is switched for transmit and receive modes. FIG. 240Billustrates a patch antenna and RF feed line connection including a transmit/receive (TR) switch for a dual polarization design, according to some aspects of the present disclosure. In FIG. 240B, patch antenna 45215 has horizontal polarization feed line feed line 45217 connected at a match point 45219. Vertical polarization feed line 45224 is connected at match point 45223. Antenna 45225 is the same as patch antenna 45215. For horizontal polarization, horizontal polarization feed line 45217, in a transceiver, is attached to T/R switch 45227. PA 45229 and LNA 45231 are each connected to T/R switch 45227 as illustrated and the T/R switch is switched for transmit and receive modes for horizontally polarized signals. For vertical polarization, vertical polarization feed line 45224, in a transceiver, is attached to T/R switch 45235. PA 45237 and LNA 45239 are each connected to T/R switch 45235 as illustrated and the T/R switch is switched for transmit and receive modes for vertically polarized signals. However, the T/R switch can be removed in some aspects of the present disclosure because of the feed line characteristics of patch antennas. With patch antennas, there can be one antenna feed line matching point that is slightly offset to one side when compared to a second antenna feed line matching point. This is seen in FIG. 240C. FIG. 240Cillustrates a patch antenna 45204 in a single polarization design, with the antenna feed line for the RX feed line matching point slightly offset to one side as compared to the TX feed line matching point, according to some aspects of the present disclosure. In other words, in FIG. 240C, the RX matched feed point is closer to the edge of the antenna than is the TX feed point. The reason for this is that the impedance of a connection point of a feed line is determined by the point on the patch antenna where the connection is made, with lower connection impedance being closer to the center of the patch antenna and higher connection impedance being closer to the edge of the patch antenna. For transmit and receive operation, both a TX feed line and an RX feed line are attached to the patch antenna. In some aspects of the present disclosure, a PA is attached to the transmitter side of the TX feed line. A PA operates at a very low impedance so the TX feed line matching point will be relatively close to the center of the patch antenna, as seen in FIG. 240C, to meet the low impedance matching requirements of the PA. An LNA is attached to the RX side of the RX feed line. An LNA operates at a high impedance so the TX feed line matching point will be relatively close to the edge of the patch antenna, also as seen in FIG. 240C. These two matching points, one near the center of the patch antenna and one near the edge of the patch antenna, results in the offset between the two matching points. This offset in matching points is also exhibited for a dual polarization design as seen in FIG. 240D. FIG. 240Dillustrates a patch antenna 45206 in a dual polarization design, with the antenna feed lines for the RX feed line matching point slightly offset to one side as compared to the TX feed line matching point, for both polarizations, according to some aspects of the present disclosure. In other words, in FIG. 240Dthere are two sets of offset matching points, one for horizontal polarization operation and one for vertical polarization operation. The above feed line matching point characteristic for a patch antenna enables the TX chain to be directly connected to the TX feed line matching point of the patch antenna and the RX chain to be directly connected to the RX feed line matching point of the patch antenna. Thus, the benefit for a T/R switch and the associated insertion loss to be included in the RF lineup is reduced. This in turn can significantly improve the RF performance from the TX output power/efficiency and RX noise figure (NF) points of view. The foregoing can be seen in FIGS. 241Aand 241B. The 180-degree phase inversion between TX and RX associated with the feed lines coming from opposite directions, can be overcome at the system level. FIG. 241Aillustrates a single polarization implementation of a TX feed line and an RX feed line connected directly to a patch antenna feed line matching points, according to some aspects of the present disclosure. In FIG. 241A, patch antenna 45301 has RX feed line 45307 connected to RX feed line matching point 45309 and TX feed line 45303 connected directly to TX feed line matching point 45305. Patch antenna 45311, which is the same or similar to patch antenna 45301 is connected directly to PA 45313 via TX feed line 45303 and directly to LNA 45315 via RX feed line 45307, without the need for a T/R switch. FIG. 241Billustrates a dual polarization implementation by way of a horizontal polarization TX feed line and horizontal RX feed line, and a vertical polarization TX feed line and vertical RX feed line, connected directly to a patch antenna feed line matching points without a T/R switch, according to some aspects of the present disclosure. FIG. 241Bis similar to FIG. 241Aexcept that there are both a horizontal polarization TX feed line 45327 and horizontal polarization RX feed line 45331, and a vertical polarization TX feed line 45319 and vertical polarization RX feed line 45323 connected to their respective feed line matching points 45329, 45333 and 45321, 45325. In this aspect, patch antenna 45335 is directly connected to PA 45337 by way of horizontal polarization TX feed line 45327 and directly connected to LNA 45339 by way of horizontal polarization RX feed line 45331, without a T/R switch. Similarly, patch antenna 45335 can be directly connected to PA 45343 by way of vertical polarization TX feed line 45319 and directly connected to LNA 45345 by way of vertical polarization RX feed line 45323, without a T/R switch. The direct connections illustrated in FIGS. 241Aand 241Ballow operation in a half-duplex mode, without T/R switches, where the TX and RX are operating at different times. FIG. 242Aillustrates an IC shield, according to some aspects of the present disclosure. IC Shield 45400 comprises two metal parts, the so-called “fence” 45401 which is soldered or otherwise affixed to a PCB and within which integrated and discrete circuitry may be situated, for example within the illustrated cut-outs in fence 45401; and the lid 45403 which is attached to the fence, in some aspects of the present disclosure by pressing it on top of the fence 45401. The two-piece IC shield technique allows the option to improve antenna gain by serving as a reflector to an antenna, or array of antennas, situated adjacent to the shield as discussed below. In some aspects of the present disclosure, the gain can be further improved by allowing part of the fence 45401 to bulge out, or extend, through a space in the lid 45403. FIG. 242Billustrates an IC shield with a bulge, or extension, of the fence at 45405, through the illustrated space in the lid 45403 to enhance antenna gain and directivity, according to some aspects of the present disclosure. In some aspects of the present disclosure, the lid itself might be made into an extension, although if a non-soldered lid is used it might deform, for example by the aspect falling and hitting the floor, or when handled by hand. Returning to the discussion of FIG. 242B, the bulge may be folded or unfolded. The fold in the bulge, or extension, is primarily to provide mechanical stability. FIG. 242Bshows a part of the floor plan of a user device, including coaxial connector 43915, originally seen in FIG. 227, which takes up much of the limited space for antenna arrays as discussed above. Adjacent to, and very close to, the shield in FIG. 242Bis an antenna array which includes stacked patch antennas 45407A and 45409A, and dipole antenna elements 45407B and 45409B, and may include directors 45407C, 45409C and 45407D, 45409D. In some aspects of the present disclosure the distance between dipole 45407B and director 45407C is 340 microns. The distance from dipole 45409B to the edge of the copper layers 45410 may be 780 microns. The distance from dipole to lid 45403 may be 2 millimeters. In some aspects of the present disclosure the distance between directors 45407C and 45407D is similarly 340 microns. The array may be fed as discussed above for patch and dipole aspects. Gain in the endfire direction (normal to the directors) that is attributed to the bulge has been measured at approximately 1 dBi. FIG. 242Cillustrates the use of a folded extension 45405 of the fence through the IC shield cover 45403 to improve the gain of an array of dipole antenna elements, 45411, 45413, 45415, 45417, according to some aspects of the present disclosure. The illustrated array is a 1x4 dipole array constructed within the PCB as discussed above. In some aspects of the present disclosure, the PCB may be made of Bismaleimide-Triazine (BT) epoxy. In the aspect of FIG. 454C, gain in the endfire direction (normal to the dipole arms) due to the bulge has been measured at approximately 0.5 dBi. FIG. 242Dillustrates a hole 45419 that is formed in the shield structure because of the bulge, according to some aspects of the present disclosure. Also seen is a part of the fence 45421 internal to the lid 45403. In some aspects of the present disclosure, the bulge is not hermetically closed. Therefore, a hole such as that at 45419 can be formed in the structure 45406 and there can therefore be RF leakage. Consequently, care may be taken when implementing the bulge 45405 to fold or otherwise situate the metal in such a way as to make hole 45419 as small as possible to minimize such leakage. FIG. 242Eis a close-up perspective view of the bulge and the hole of FIG. 242D, according to some aspects of the present disclosure. The combination 45408 of lid 45403 and fence 45421 illustrates the bulge 5405 and the hole 45419 more clearly. FIG. 243is a top view of a combined patch antenna and dipole antenna array with a shield reflector, according to some aspects of the present disclosure. Illustrated at 45500 is an array including patch antennas 45503, 45505, 45507, and dipole antennas 45509 and 45511 that supports dual polarization diversity to the endfire direction (normal to the dipole arms). In some aspects of the present disclosure, the patch antennas 45503, 45505, 45507 can be dual patches as discussed below with respect to FIG. 244. IC shield lid 45501 and IC shield fence bulge 45501A provide a reflector and ground for the antenna array. A plurality of holes illustrated at 45513 in FIG. 243are placed between the patches and are typical on each side of both dipole antennas of the array. In some aspects of the present disclosure, the holes clear the coupling between the ground provided by shield 45501 and the dipoles 45509, 45511, inasmuch as if ground is very close to the dipole the impedance matching will be degraded and will negatively impact effectiveness of the dipole. The dipole radiation efficiency can be degraded and not reflect the radiation appropriately if a metal is close to the antenna. To achieve reflection without substantially degraded antenna performance, the metal should be away from the radiator, in some aspects of the present disclosure by approximately a quarter wave length. The patch modes are between the patch and ground below the patch and may not require a large ground to be effective. Since the ground is finite there is diffraction, but the losses are minor. Ground clearance for the dipoles to the ground 45513 is such that the holes allow the dipole to be closer to the patches, thereby making the structure more compact. When looking in the endfire direction, the dipole has horizontal polarization and the patch antennas have vertical polarization, each patch antenna functioning as a monopolar element. FIG. 244is a side view of the antenna array of FIG. 243, according to some aspects of the present disclosure. The coordinate system for the array is seen adjacent shield 45501 with the Y coordinate actually proceeding out of the page. The patches and dipoles are in the PCB as indicated. One of the three patch antennas 45503, 45503A is illustrated in side view, the others being typical, and comprises a dual patch antenna wherein patch 45503A is a parasitic antenna and patch 45503B is a driven patch energized via feed line 45601 by use, in one aspect, of a via hole. Dipole antenna 45509 is seen in side view, being fed by feed line 45603, which may be a ground layer and also part of the dipole. The dipole is constructed from two layers, one arm is part of the ground 45603, and the second is from layer 45509 which excited from that layer. Those of ordinary skill in the art will recognize that the number of each type of antenna has been described for example only, and that differing numbers, or pluralities, of such antennas may be appropriate for additional aspects. Similarly, other dimensions than the described dimensions may find use in other aspects, depending on space available in the device in which the antenna arrays find use, as may be shown by simulation or other methods. FIG. 245is a perspective view of an interposer used with a patch array to bypass large obstacles in a user device, according to some aspects of the present disclosure. The material that comprises the interposer may be PCB laminate or other insulating material. Inasmuch as the patches already have ground in the RF sub-system, the interposer material does not have a large effect on the antenna. The interposer may be secured to the PCB by solder with pads, such as LGA pads. In some aspects of the present disclosure, the IF would be routed from the mother board to the RF sub-system for processing and ultimate feeding to the patch antenna array for transmission. In FIG. 245, a partial floorplan 54700 of a user device can include a PCB mother board which may be a low temperature co-fired ceramic (LTCC) in some aspects of the present disclosure. Item 45703 may be part of a laptop or other device chassis and may be made of magnesium in some aspects of the present disclosure. USB connector is seen at 45705, and obstructs effective antenna operation. In order to bypass the obstruction, an interposer 45707 with a patch antenna array 45709 with a reflector shield 45710, situated on top of the interposer may be used. The reflector shield may be part of an IC shield such as those described above in this patent. The entire IC shield and the IC itself is not shown due to space considerations but would be situated as discussed above, or as discussed below with respect to FIG. 461A. The interposer 45707 is intended to provide height and raise the entire RFEM so it contains GND vias and also IF signal vias for connection to ground and for feeding the antenna array, as needed. FIG. 246Ais a perspective view of an interposer illustrating an IC shield lid 45801, according to some aspects of the present disclosure. In FIG. 246A, an array of dipole antennas 45809 and a reflector 45810 are situated on an interposer, similar to the patch antenna array 45709 and reflector 45710 in FIG. 245. Item 45809A may be a patch antenna array with reflectors 45812, in some aspects of the present disclosure. Endfire direction of the array and reflector is illustrated. FIG. 246Bis a vertical view of the radiation pattern for the dipole antenna array of FIG. 246A, with the endfire direction illustrated at minus ninety (-90) degrees, according to some aspects of the present disclosure. The Broadside direction is indicated at zero (0) degrees. As can be seen, coverage is strong in the broadside direction in FIG. 458B. However, the interposer has enabled a certain amount of dipole array radiation in the endfire direction illustrated in FIG. 246B. There are several patterns illustrated in FIG. 246B, each pattern for a different height of the interposer. As can be seen from FIG. 246B, when a dipole array is placed on the interposer the radiation to the endfire is degraded, with low gain and small beamwidth at all illustrated interposer heights. For this the reason, placing a patch array on the interposer would be preferable FIG. 247illustrates realized gain of the patch antenna array of FIG. 246Aas a function of the height of the interposer, in various directions, according to some aspects of the present disclosure. The three curves 45901, 45903, and 45905 illustrate realized gain as a functioning of height of the interposer in the endfire direction, 5 degrees above endfire and 10 degrees above endfire, respectively. FIG. 248Aillustrates a combined patch and slot antenna for dual band, dual polarization operation, according to some aspects of the present disclosure. In FIG. 248A, antenna 46000 illustrates dual patch antennas 46001, 46002 that form a first antenna, and rectangular slot antenna 46003 that forms a second antenna. Each antenna is fed by two feed mechanisms, each of which is orthogonal to the other for dual polarization. For example, slot antenna 46003 is fed by feed lines 46005 and 46007, each orthogonal to the other. Items 46005A and 46005B are ground vias to reference the feed line 46005, with similar ground vias to reference feed line 46007. Patch antennas 46001, 46002 include a parasitic antenna element 46001 and a driven antenna element 46002. The driven antenna 46002 is fed, in the aspect illustrated, by via, such as at 46013, 46015 of FIG. 248B. The via 46013 may be coupled to a feed line such as 46011 also shown in FIG. 248B. Line 46011 may be fed by an integrated circuit (IC) of a user device (the IC not shown). Via 46015 may similarly be coupled to a feed line which may be orthogonal to feed line 46011 and likewise fed by the IC. Slot antenna 46003 may be fed, in the aspect illustrated, by proximity coupling or by any appropriate feed mechanism, such as by micro strip lines. Proximity coupling is illustrated in FIG. 248Band described below. FIG. 248Bis a side view of the combined patch antenna and slot antenna of FIG. 248A, according to some aspects of the present disclosure. From a side view, FIG. 248Billustrates slot antenna 46003 and one of the two feed mechanisms of slot antenna 46003, such as feed line 46007 which, in some aspects of the present disclosure, may be a micro strip feed line, metal traces, or other types of transmission lines. Micro strip feed line 46007 is illustrated as being within PCB and at a certain distance from the bottom of slot antenna 46003, and drives slot antenna 46003 by proximity coupling, enabling energy to be coupled from feed lines 46005, 46007 to slot antenna 46003. Lines 46005, 46007 may be coupled for feed signal purposes to the integrated circuitry of the user device (not shown) to slot antenna 46003. Micro strip feed line 46005 is situated orthogonal to feed line 46007. While the feed line has been described as a micro strip, it could be any suitable transmission line such as stripline, traces, and the like. In some aspects of the present disclosure, the feed lines include dual band feed lines, such as feed line 46005 in a band that includes 30 GHz and feed line 46007 in a band that includes 60 GHz. The feed lines may also be at the 39 GHz band or the 73 GHz band, or other appropriate band, with feed line 46005 being at a frequency within the band and feedline 46007 being at twice that frequency. In some aspects of the present disclosure, the patch antenna 46001, 46002 operates at one frequency and the slot antenna 46003 operates at a second frequency, the frequency of each antenna being dependent on the size of the antenna. In other words, the patch antenna and the slot antenna can be made to operate at different frequencies by designing the antenna dimensions to operate at the desired frequency. In some aspects of the present disclosure, each antenna operates at a different time, so that signals of the appropriate polarization can be transmitted at the appropriate time, depending on feedback from the receiving device that indicates which polarization is the better polarization at a given time. As mentioned above, in some aspects of the present disclosure, patch antenna 46001 is a parasitic antenna element and 46002 is a driven antenna element. As seen in FIG. 248B, the ground of driven antenna 46002 is “floating” in that it is fed by way of via holes 46013 and 46015 (only via 46015 being visible in FIG. 248A), each via being in a given band discussed above and each associated with feed line 46007 and 46005, respectively, for proximity coupling for feeding the driven element 46002. Such feed line may include a via connected to the driven element. The inner part of the slot element is rectangular metal which may acts as ground GND for the patch element, given that it may be made large enough for that purpose and the antennas operate at different times. The feed of the patch antennas and of the slot antennas being orthogonal supports polarization with spatial diversity. For example, for radiation in the X direction, excitation would be by way of a first feed line and for radiation in the Y direction, excitation would be by way of a second feed line that is orthogonal to the first feed line. For broadside radiation, each antenna can operate with dual polarization in the broadside (Z in FIG. 248B) direction. Each antenna can be algorithmically controlled to operate at a given time and at a given polarization, the polarization dependent on which feed line is activated at that given time, and that activation is dependent on the orientation of the receiving device, which is feeding back to the transmitter information that designates which polarization provides the better reception at that given time. For end-fire radiation, each antenna may operate with only one polarization, the polarization dependent on whether excitation is from the X-direction (46013 in FIG. 248B) or the Y direction (46015 in FIG. 248B), generally with lower gain than for broadside radiation. Additionally, for end-fire radiation each antenna may also operate with dual polarization if each antenna element is excited with two orthogonal feeds, but with much lower gain than for single polarization operation. While a single parasitic element has been described, those of ordinary skill in the art will recognize that a plurality of such parasitic elements, or in some aspects of the present disclosure, one or more directors, may be used as appropriate for a given aspect. Similarly, while a square slot antenna has been described, other configurations of slot antennas may also be used in various aspects. An antenna, or an array of antennas, may be extracted in the silicon circuitry, or chip, in a layer of a circuit board which in some aspects of the present disclosure is an ultra-thick metal (UTM). UTM is known to have one of the lowest losses for circuit board material. FIG. 249Ais an exploded view of an antenna-on-a-chip (AOC), according to some aspects of the present disclosure. AOC 46100 comprises PCB 46111 which may also be BT laminate board, and silicon circuitry 46103 which may include a transceiver for providing radio frequency (RF) signals. The AOC includes antennas 46105 which can comprise a 2x2 patch antenna array in some aspects of the present disclosure (one of the patch antennas being designated as 46105, but the other three are typical as illustrated), and may include IC metal shield 46101. While the aspect under discussion includes an array that comprises four patch antenna elements, aspects are not limited to patch antennas. Those of ordinary skill in the art will recognize that other antenna elements such as slot antennas or notch antenna, the frequency of operation of the antenna array may be in the mmWave bands and in frequency ranges that would support some or all of the WiGig frequency bands. The PCB board 46111 has metal clearance 46113 below the antenna array. Clearance 46113 prevents shorting out of the antenna array. Because the antenna radiation is through or via the circuit boards the clearance 46113 and also functions to enable antenna array radiation to be transmitted outside the board. FIG. 249Bis a bottom view of the antennas 46105 that comprise the AOC of FIG. 249A, according to some aspects of the present disclosure. Transformers 46107 comprise transformers used in the silicon circuitry, such as for conjugate matching, and other electronic functions. Traces may be placed at 46109 and may be used for routing between and among the patches 46105, including feeds for the patches, the feeds may be coupled to a transceiver within the silicon circuitry and may include small microstrip lines coupled to a power amplifier (PA) and a low noise amplifier (LNA) switch. FIG. 249Cis a side view of the AOC of FIG. 249Aand illustrates the IC shield 46101, silicon circuitry 46103, and PCB board 46111. The patches can be implemented at the bottom of the silicon 46103, and the IC shield 46101 can be used as ground. FIG. 250illustrates dimensions of the patch array that comprises four patch antennas one of which one is delineated as 46105 in FIG. 250. The patches themselves may be 1 millimeter square. FIG. 251is a simulated radiation pattern for the AOC of FIGS. 249A-249Cand 250, according to some aspects of the present disclosure. Pattern 46301 illustrates the E-plane and pattern 46303 represents the H-plane. FIG. 252Aillustrates another side view of an AOC for an embedded die in a package-on-package implementation, according to some aspects of the present disclosure. PCB 46401 includes silicon 46405 and ground 46403. When ground 46403 is provided, there is no need for an IC shield such as 46103 in FIG. 249Cto be used as ground. Connection between the antennas in the silicon 46405 and ground 46403 is made by 50-ohm connection 46407, sometimes referred to as a bump. Connection 46407 may comprise a via that goes from silicon to GND and it is being used here as part of the feed mechanism. In practice there may be many vias that connect the IC to the GND. FIG. 252Bis an illustration of radiation efficiency as a function of height of the silicon divided by height of the patches, according to some aspects of the present disclosure. Stated another way, the height of IC is the silicon thickness and the patch height is the antenna size thickness from GND to the radiated patch. For an aspect where the ground is 60 microns above the die in FIG. 252A, the realized gain was 0.46 dBi. FIG. 252Cis an illustration of realized gain in dBi as a function of height of the silicon divided by height of the patches, according to some aspects of the present disclosure. FIG. 253is another illustration of AOC symbolically showing a chip overview and including the relationship of the antennas and the circuitry on the chip, according to some aspects of the present disclosure. Chip overview 46500 illustrates a silicon chip with four AOC elements, one of which is indicated at 46501. On chip circuitry is indicated by a series of triangles, one of which is indicated at 46503. This circuitry may include an RFEM (or RFIC), comprising usual radio circuitry that comprises a transceiver, including but not limited to power amplifiers and low noise amplifiers. On-chip connectors are illustrated by straight lines, such as 46505 and may including usual circuitry connections and connections to the AOC. AOC provides substantial cost savings because a simple board can be used for implementation. In one aspect, the product that includes the AOC can be sold as the shielded silicon circuitry including the AOC, without a board, and an OEM that purchases the product can solder the product directly to the mother board. Alternatively, the AOC can be installed with its own PCB together with an IF or RF cable such that it could be placed anywhere in the platform. In that case the benefit of the AOC is that it will simplify the PCB compared with the regular antenna on board. Alternatively, the AOC product can be marketed already installed on the motherboard. This is cost effective because there is no need for a package inasmuch as the location of the AOC is limited to the motherboard area. In other words, there would be no package, which would be a substantial savings. The AOC provides an improved conducted power and noise figure inasmuch as there is no requirement for board routing and solder ball transition degradation. Generally, the patch size can be reduced by fifty percent (50%) compared to board patches. AOC supports wide band matching, perhaps as much as a 304GHz bandwidth, which can enable supporting more than four channels. The described AOC can be implemented with embedded die/package-on-package (POP) solutions. POP is a technique that combines two PCB’s. A main PCB contains the die (sometimes referred to as a “simple PCB”) and another PCB with a cavity filled with metal which behaves as shield and also allows signals and the antenna array to be placed on top of the shield. Further, because the AOC does not require traces to an external antenna, the antennas will have no, or very few, losses due to such traces. FIG. 254illustrates a block diagram of an example machine 46600 upon which any one or more of the techniques or methodologies discussed herein may be performed, according to some aspects of the present disclosure. In alternative aspects, the machine 46600 may operate as a standalone device or may be connected (e.g., networked) to other machines. In a networked deployment, the machine 46600 may operate in the capacity of a server machine, a client machine, or both in server-client network environments. In an example, the machine 46600 may act as a peer machine in peer-to-peer (P2P) (or other distributed) network environment. The machine 46600 may be a UE, eNodeB, AP, STA, personal computer (PC), a tablet PC, a set-top box (STB), a personal digital assistant (PDA), a mobile telephone, a smart phone, a web appliance, a network router, switch or bridge, or any machine capable of executing instructions (sequential or otherwise) that specify actions to be taken by that machine. Further, while only a single machine is illustrated, the term “machine” shall also be taken to include any collection of machines that individually or jointly execute a set (or multiple sets) of instructions to perform any one or more of the methodologies discussed herein, such as cloud computing, software as a service (SaaS), other computer cluster configurations. Examples, as described herein, may include, or may operate on, logic or a number of components, sub-systems, or mechanisms. Sub-systems are tangible entities (e.g., hardware) capable of performing specified operations and may be configured or arranged in a certain manner. In an example, circuits may be arranged (e.g., internally or with respect to external entities such as other circuits) in a specified manner as a sub-system. In an example, the whole or part of one or more computer systems (e.g., a standalone, client or server computer system) or one or more hardware processors may be configured by firmware or software (e.g., instructions, an application portion, or an application) as a sub-system that operates to perform specified operations. In an example, the software may reside on a machine readable medium. In an example, the software, when executed by the underlying hardware of the sub-system, causes the hardware to perform the specified operations. Accordingly, the term “sub-system” is understood to encompass a tangible entity, be that an entity that is physically constructed, specifically configured (e.g., hardwired), or temporarily (e.g., transitorily) configured (e.g., programmed) to operate in a specified manner or to perform part or all of any operation described herein. Considering examples in which sub-systems are temporarily configured, each of the sub-systems need not be instantiated at any one moment in time. For example, where the sub-systems comprise a general-purpose hardware processor configured using software, the general-purpose hardware processor may be configured as respective different sub-systems at different times. Software may accordingly configure a hardware processor, for example, to constitute a particular sub-system at one instance of time and to constitute a different sub-system at a different instance of time. Machine (e.g., computer system) may include a hardware processor 46602 (e.g., a central processing unit (CPU), a graphics processing unit (GPU), a hardware processor core, or any combination thereof), a main memory 46604 and a static memory 46606, some or all of which may communicate with each other via an interlink (e.g., bus) 46608. The machine 46600 may further include a display unit 46610, an alphanumeric input device 46612 (e.g., a keyboard), and a user interface (UI) navigation device 46614 (e.g., a mouse). In an example, the display unit 46610, input device 46612 and UI navigation device 46614 may be a touch screen display. The machine 46600 may additionally include a storage device (e.g., drive unit) 46616, a signal generation device 46618 (e.g., a speaker), a network interface device 46620, and one or more sensors, such as a global positioning system (GPS) sensor, compass, accelerometer, or other sensor. The machine 46600 may include an output controller 46628, such as a serial (e.g., universal serial bus (USB), parallel, or other wired or wireless (e.g., infrared (IR), near field communication (NFC), and the like.) connection to communicate or control one or more peripheral devices (e.g., a printer, card reader, and the like). The storage device 46616 may include a machine readable medium 46622 on which is stored one or more sets of data structures or instructions 46624 (e.g., software) embodying or utilized by any one or more of the techniques or functions described herein. The instructions 46624 may also reside, completely or at least partially, within the main memory 46604, within static memory 46606, or within the hardware processor 46602 during execution thereof by the machine. In an example, one or any combination of the hardware processor 46602, the main memory 46604, the static memory 46606, or the storage device 46616 may constitute machine readable media. While the machine readable medium 46622 is illustrated as a single medium, the term “machine readable medium” may include a single medium or multiple media (e.g., a centralized or distributed database, and/or associated caches and servers) configured to store the one or more instructions 46624. The term “machine readable medium” may include any medium that is capable of storing, encoding, or carrying instructions for execution by the machine and that cause the machine to perform any one or more of the techniques of the present disclosure, or that is capable of storing, encoding or carrying data structures used by or associated with such instructions. Non-limiting machine readable medium examples may include solid-state memories, and optical and magnetic media. Specific examples of machine readable media may include: non-volatile memory, such as semiconductor memory devices (e.g., Electrically Programmable Read-Only Memory (EPROM), Electrically Erasable Programmable Read-Only Memory (EEPROM)) and flash memory devices; magnetic disks, such as internal hard disks and removable disks; magneto-optical disks; Random Access Memory (RAM); and CD-ROM and DVD-ROM disks. In some examples, machine readable media may include non-transitory machine readable media. In some examples, machine readable media may include machine readable media that is not a transitory propagating signal. The instructions 46624 may further be transmitted or received over a communications network 46626 using a transmission medium via the network interface device 46620 utilizing any one of a number of transfer protocols (e.g., frame relay, internet protocol (IP), transmission control protocol (TCP), user datagram protocol (UDP), hypertext transfer protocol (HTTP), and the like). Example communication networks may include a local area network (LAN), a wide area network (WAN), a packet data network (e.g., the Internet), mobile telephone networks (e.g., cellular networks), Plain Old Telephone (POTS) networks, and wireless data networks (e.g., Institute of Electrical and Electronics Engineers (IEEE) 802.11 family of standards known as Wi-Fi®, IEEE 802.16 family of standards known as WiMax®), IEEE 802.15.4 family of standards, a Long Term Evolution (LTE) family of standards, a Universal Mobile Telecommunications System (UMTS) family of standards, peer-to-peer (P2P) networks, among others. In an example, the network interface device 46620 may include one or more physical jacks (e.g., Ethernet, coaxial, or phone jacks) or one or more antennas to connect to the communications network 46626. In an example, the network interface device 46620 may include a plurality of antennas to wirelessly communicate using at least one of single-input multiple-output (SIMO), multiple-input multiple-output (MIMO), or multiple-input single-output (MISO) techniques. In some examples, the network interface device 46620 may wirelessly communicate using Multiple User MIMO techniques. The term “transmission medium” shall be taken to include any intangible medium that is capable of storing, encoding or carrying instructions for execution by the machine, and includes digital or analog communications signals or other intangible medium to facilitate communication of such software. FIG. 255illustrates protocol functions that may be implemented in a wireless communication device, according to some aspects of the present disclosure. In some aspects, protocol layers may include one or more of physical layer (PHY) 46710, medium access control layer (MAC) 46720, radio link control layer (RLC) 46730, packet data convergence protocol layer (PDCP) 46740, service data adaptation protocol (SDAP) layer 46747, radio resource control layer (RRC) 46755, and non-access stratum (NAS) layer 46757, in addition to other higher layer functions not illustrated. According to some aspects, protocol layers may include one or more service access points that may provide communication between two or more protocol layers. According to some aspects, PHY 46710 may transmit and receive physical layer signals 46705 that may be received or transmitted respectively by one or more other communication devices. According to some aspects, physical layer signals 46705 may comprise one or more physical channels. According to some aspects, an instance of PHY 46710 may process requests from and provide indications to an instance of MAC 46720 via one or more physical layer service access points (PHY-SAP) 46715. According to some aspects, requests and indications communicated via PHY-SAP 46715 may comprise one or more transport channels. According to some aspects, an instance of MAC 46710 may process requests from and provide indications to an instance of RLC 46730 via one or more medium access control service access points (MAC-SAP) 46725. According to some aspects, requests and indications communicated via MAC-SAP 46725 may comprise one or more logical channels. According to some aspects, an instance of RLC 46730 may process requests from and provide indications to an instance of PDCP 46740 via one or more radio link control service access points (RLC-SAP) 46735. According to some aspects, requests and indications communicated via RLC-SAP 46735 may comprise one or more RLC channels. According to some aspects, an instance of PDCP 46740 may process requests from and provide indications to one or more of an instance of RRC 46755 and one or more instances of SDAP 46747 via one or more packet data convergence protocol service access points (PDCP-SAP) 46745. According to some aspects, requests and indications communicated via PDCP-SAP 46745 may comprise one or more radio bearers. According to some aspects, an instance of SDAP 46747 may process requests from and provide indications to one or more higher layer protocol entities via one or more service data adaptation protocol service access points (SDAP-SAP) 46749. According to some aspects, requests and indications communicated via SDAP-SAP 46749 may comprise one or more quality of service (QoS) flows. According to some aspects, RRC entity 46755 may configure, via one or more management service access points (M-SAP), aspects of one or more protocol layers, which may include one or more instances of PHY 46710, MAC 46720, RLC 46730, PDCP 46740 and SDAP 46747. According to some aspects, an instance of RRC 46755 may process requests from and provide indications to one or more NAS entities via one or more RRC service access points (RRC-SAP) 46756. FIG. 256illustrates various protocol entities that may be implemented in connection with a wireless communication device or a wireless communication system, according to some aspects of the present disclosure. More specifically, FIG. 256is an illustration of protocol entities that may be implemented in wireless communication devices, including one or more of a user equipment (UE) 46860, a base station, which may be termed an evolved node B (eNB), or new radio node B (gNB) 46880, and a network function, which may be termed a mobility management entity (MME), or an access and mobility management function (AMF) 46894, according to some aspects. According to some aspects, gNB 46880 may be implemented as one or more of a dedicated physical device such as a macro-cell, a femto-cell or other suitable device, or in an alternative aspect, may be implemented as one or more software entities running on server computers as part of a virtual network termed a cloud radio access network (CRAN). According to some aspects, one or more protocol entities that may be implemented in one or more of UE 46860, gNB 46880 and AMF 46894, may be described as implementing all or part of a protocol stack in which the layers are considered to be ordered from lowest to highest in the order PHY, MAC, RLC, PDCP, RRC and NAS. According to some aspects, one or more protocol entities that may be implemented in one or more of UE 46860, gNB 46880 and AMF 46894, may communicate with a respective peer protocol entity that may be implemented on another device, using the services of respective lower layer protocol entities to perform such communication. According to some aspects, UE PHY 46872 and peer entity gNB PHY 46890 may communicate using signals transmitted and received via a wireless medium. According to some aspects, UE MAC 46870 and peer entity gNB MAC 46888 may communicate using the services provided respectively by UE PHY 46872 and gNB PHY 46890. According to some aspects, UE RLC 46868 and peer entity gNB RLC 46886 may communicate using the services provided respectively by UE MAC 46870 and gNB MAC 46888. According to some aspects, UE PDCP 46866 and peer entity gNB PDCP 46884 may communicate using the services provided respectively by UE RLC 46868 and 5GNB RLC 46886. According to some aspects, UE RRC 46864 and gNB RRC 46882 may communicate using the services provided respectively by UE PDCP 46866 and gNB PDCP 46884. According to some aspects, UE NAS 46862 and AMF NAS 46892 may communicate using the services provided respectively by UE RRC 46864 and gNB RRC 46882. A MAC entity 46900 that may be used to implement medium access control layer functions according to an aspect is illustrated in FIG. 257. According to some aspects, MAC entity 46900 may include one or more of a controller 46905, a logical channel prioritizing unit 46910, a channel multiplexer and de-multiplexer 46915, a PDU filter unit 46915, random access protocol entity 46920, data hybrid automatic repeat request protocol (HARQ) entity 46925 and broadcast HARQ entity 46930. According to some aspects, a higher layer may exchange control and status messages 46935 with controller 46905 via management service access point 46940. According to some aspects, MAC service data units (SDU) corresponding to one or more logical channels 46945, 46955, 46965 and 46975 may be exchanged with MAC entity 46900 via one or more service access points (SAP) 46950, 46960, 46970 and 46980. According to some aspects, PHY service data units (SDU) corresponding to one or more transport channels 46985, 46995, 469105 and 469115 may be exchanged with a physical layer entity via one or more service access points (SAP) 46990, 469100, 469110 and 469120. According to some aspects, logical channel prioritization unit 46910 may perform prioritization amongst one or more logical channels 46945 and 46955, which may include storing parameters and state information corresponding to each of the one or more logical channels that may be initialized when a logical channel is established. According to some aspects, logical channel prioritization unit 46910 may be configured with a set of parameters for each of one or more logical channels 46945 and 46955, the each set including parameters which may include one or more of a prioritized bit rate (PBR) and a bucket size duration (BSD). According to some aspects, multiplexer and de-multiplexer 46915 may generate MAC PDUs, which may include one or more of MAC-SDUs or partial MAC-SDUs corresponding to one or more logical channels, a MAC header which may include one or more MAC sub-headers, one or more MAC control elements, and padding data. According to some aspects, multiplexer and de-multiplexer 46915 may separate one or more MAC-SDUs or partial MAC-SDUs contained in a received MAC PDU, corresponding to one or more logical channels 46945 and 46955, and may indicate the one or more MAC-SDUs or partial MAC-SDUs to a higher layer via one or more service access points 46950 and 46960. According to some aspects, HARQ entity 46925 and broadcast HARQ entity 46930 may include one or more parallel HARQ processes, each of which may be associated with a HARQ identifier, and which may be one of a receive or transmit HARQ process. According to some aspects, a transmit HARQ process may generate a transport block (TB) to be encoded by the PHY according to a specified redundancy version (RV), by selecting a MAC-PDU for transmission. According to some aspects, a transmit HARQ process that is included in a broadcast HARQ entity 46930 may retransmit a same TB in successive transmit intervals a predetermined number of times. According to some aspects, a transmit HARQ process included in a HARQ entity 46925 may determine whether to retransmit a previously transmitted TB or to transmit a new TB at a transmit time based on whether a positive acknowledgement or a negative acknowledgement was received for a previous transmission. According to some aspects, a receive HARQ process may be provided with encoded data corresponding to one or more received TBs and which may be associated with one or more of a new data indication (NDI) and a redundancy version (RV), and the receive HARQ process may determine whether each such received encoded data block corresponds to a retransmission of a previously received TB or a not previously received TB. According to some aspects, a receive HARQ process may include a buffer, which may be implemented as a memory or other suitable storage device, and may be used to store data based on previously received data for a TB. According to some aspects, a receive HARQ process may attempt to decode a TB, the decoding based on received data for the TB, and which may be additionally be based on the stored data based on previously received data for the TB. The formats of PDUs that may be encoded and decoded by MAC entity 46900 according to some aspects are illustrated in FIG. 258A. According to some aspects, a MAC PDU 47000 may consist of a MAC header 47005 and a MAC payload 47010, the MAC payload consisting of zero or more MAC control elements 47030, zero or more MAC SDU portions 47035 and zero or one padding portion 47040. According to some aspects, MAC header 47005 may consist of one or more MAC sub-headers, each of which may correspond to a MAC payload portion and appear in corresponding order. According to some aspects, each of the zero or more MAC control elements 47030 contained in MAC payload 47010 may correspond to a fixed length sub-header 47015 contained in MAC header 47005. According to some aspects, each of the zero or more MAC SDU portions 47035 contained in MAC payload 47010 may correspond to a variable length sub-header 47020 contained in MAC header 47005. According to some aspects, padding portion 47040 contained in MAC payload 47010 may correspond to a padding sub-header 47025 contained in MAC header 47005. The formats of PDUs that may be encoded and decoded by MAC entity 469100 according to some alternative aspects are illustrated in FIG. 258B. According to some aspects, a MAC PDU 47000 may consist of one or more concatenated MAC Sub-PDUs 47045 which may be followed by padding 47040. According to some aspects, each MAC Sub-PDU 47045 may contain a sub-header and one of a fixed length control element, a variable length control element and a MAC SDU. According to some aspects, a MAC Sub-PDU 47045 containing a fixed length control element may also contain a fixed length sub-header 47015. According to some aspects, a MAC Sub-PDU 47045 containing a variable length control element may also contain a variable length sub-header 47020. According to some aspects, a MAC Sub-PDU 47045 containing a MAC SDU may also contain a variable length sub-header 47020. Aspects of a fixed length MAC sub-header 47015 that may be contained in MAC header 47005 are illustrated in FIG. 258C. Aspects of a variable length MAC sub-header 47020 that may be contained in MAC header 47005 are illustrated in FIG. 258D. Aspects of a padding sub-header 47025 that may be contained in MAC header 47005 are illustrated in FIG. 258E. According to some aspects, a fixed length sub-header 47015 may contain one or more of reserved bits 47065, an extension bit 47070 and a logical channel identifier (LCID) field 47075. According to some aspects, a variable length sub-header 47020 may contain one or more of reserved bits 47065, an extension bit 47070, an LCID field 47075, a format field 47085 and a length field 47090. According to some aspects, padding sub-header 47025 may contain one or more of reserved bits 47065, an extension bit 47070 and a logical channel identifier (LCID) field 47075. According to some aspects, reserved bits 47065 may be set to zero. According to some aspects, extension bit 47070 may be set to a value that indicates whether the MAC sub-header is followed by one or more additional MAC sub-headers. According to some aspects, LCID 47075 may contain a value which indicates one of a type of a corresponding MAC control element 47030, a logical channel identifier of a corresponding MAC SDU portion 47035, or a padding type. According to some aspects, a format field 47085 may indicate a number of bits of a length field 47090. According to some aspects, length field 47090 may contain a value which indicates a length of a corresponding MAC SDU portion 47035. Aspects of functions contained within a radio link control (RLC) layer entity 47100 are illustrated in FIG. 459. According to some aspects, RLC layer entity 47100 may contain zero or more of each of a transparent mode (TM) transmit entity 47110, a TM receive entity 47115, an unacknowledged mode (UM) transmit entity 47120, a UM receive entity 47125 and an acknowledged mode (AM) entity 47130. According to some aspects, a higher layer entity may exchange control, status and data messages 47162, 47164, 47168, 47172 and 47174 with RLC layer entity 47100 via one or more service access points 47140, 47142, 47144, 47146, 47148 and 47150. According to some aspects, RLC layer entity 47100 may exchange control, status and data messages 47178, 47180, 47182, 47184 and 47186 with a lower layer protocol entity via service access points 47152, 47154, 47156, 47158 and 47160. Transparent Mode According to some aspects, zero or more of each of TM transmit entity 47110 and TM receive entity 47115 may each correspond to a distinct logical channel identifier (LCID), and may be created, configured, and disposed of dynamically, according to requests from a higher layer control entity, which may be a radio resource control (RRC) entity. According to some aspects, TM transmit entity 47110 may generate transparent mode data (TMD) PDUs from RLC SDUs received via TM SAP 47140, without segmenting or concatenating the SDUs or including any header data, and may pass the TMD PDUs to a lower layer via SAP 47152. According to some aspects, TM receive entity may accept TMD PDUs from a lower layer via SAP 47154, and may deliver the TMD PDUs as RLC SDUs to a higher layer, without any modification, via SAP 47142. Unacknowledged Mode According to some aspects, zero or more of each of UM transmit entity 47120 and UM receive entity 47125 may each correspond to a distinct logical channel identifier (LCID), and may be created, configured, and disposed of dynamically, according to requests from a higher layer control entity, which may be a radio resource control (RRC) entity. According to some aspects, UM transmit entity 47120 may generate unacknowledged mode data (UMD) PDUs from RLC SDUs by adding an RLC header to each RLC SDU, and may generate UMD PDU segments by dividing an RLC SDU into segments and adding an RLC header to each segment. According to some aspects, UM transmit entity 47120 may pass UMD PDUs and UMD PDU segments to a lower layer via SAP 47156. According to some aspects, UM receive entity 47125 may process UMD PDUs received via SAP 47158. According to some aspects, processing of received UMD PDUs by UM receive entity 47125 may include one or more of the steps of: detecting and discarding UMD PDUs that have been received in duplication, reordering received UMD PDUs and UMD PDU segments according to serial numbers contained in UMD PDU and UMD PDU segments, reassembling RLC SDUs from received UMD PDU segments, and delivering RLC SDUs to higher layers via SAP 47146 in ascending numerical order. Acknowledged Mode According to some aspects, zero or more of each of AM entity 47130 may each correspond to a distinct logical channel identifier (LCID), and may be created, configured, and disposed of dynamically, according to requests from a higher layer control entity, which may be a radio resource control (RRC) entity. According to some aspects, AM entity 47130 may generate acknowledged mode data (AMD) PDUs from RLC SDUs by adding an RLC header to each RLC SDU, and may generate AMD PDU segments by dividing an RLC SDU into segments and adding an RLC header to each segment. According to some aspects, AM entity 47130 may pass AMD PDUs and AMD PDU segments to a lower layer via SAP 47160. According to some aspects, AM entity 47130 may include in a header of an AMD PDU a polling bit, indicating that the peer AM entity receiving the PDU is requested to respond with an AM STATUS PDU, which may include information about which AMD PDUs and AMD PDU segments have been received correctly. According to some aspects, AM entity 47130 may store one or more transmitted AMD PDUs and AMD PDU segments in a retransmission buffer, and may retransmit one or more such PDUs if they are determined not to have been received correctly by the peer receiving AM entity. According to some aspects, on retransmission of an AMD PDU or AMD PDU segment, the AM entity may re-segment the PDU into two or more smaller segments if it is determined that a number of bytes of capacity available for transmission in a time interval is insufficient to retransmit the whole PDU. A TMD PDU 47200 that may be transmitted by a TM transmit entity 47110 and received by a TM receive entity 47115 according to some aspects is illustrated in FIG. 260A. According to some aspects, a TMD PDU 47200 may contain one or more octets of a data field 47205. A UMD PDU 47220 that may be transmitted by a UM transmit entity 47120 and received by a UM receive entity 47125 according to some aspects is illustrated in FIG. 260B. According to some aspects, a UMD PDU 47220 may consist of a UMD PDU header and a data field 47205. According to some aspects, a UMD PDU 47220 may contain one or more of each of reserved 1 (R1) bits 47225, segmentation flag (SF) bit 47230, last segment flag (LSF) bit 47235, sequence number (SN) field 47240, and one or more octets of data 47205. A UMD PDU segment 47250 that may be transmitted by a UM transmit entity 47120 and received by a UM receive entity 47125 according to some aspects isillustrated in FIG. 260C. According to some aspects, a UMD PDU segment 47250 may contain one or more of each of reserved 1 (R1) bits 47225, segmentation flag (SF) bit 47230, last segment flag (LSF) bit 47235, sequence number (SN) field 47240, segment offset (SO) field 47245, and one or more octets of data 47205. An AMD PDU 47260 that may be transmitted and received by an AM entity 47130 according to some aspects is illustrated in FIG. 260D. According to some aspects, an AMD PDU 47260 may consist of an AMD PDU header and a data field 47205. According to some aspects, an AMD PDU 47260 may contain one or more of each of a data/control (D/C) bit 47265, segmentation flag (SF) bit 47230, parity (P) bit 47270, reserved 1 (R1) bits 47225, last segment flag (LSF) bit 47235, sequence number (SN) field 47240, and one or more octets of data 47205. An AMD PDU segment 47280 that may be transmitted and received by an AM entity 47130 according to some aspects is illustrated in FIG. 260E. According to some aspects, an AMD PDU segment 47280 may contain one or more of each of a data/control (D/C) bit 47265, segmentation flag (SF) bit 47230, polling (P) bit 47270, reserved 1 (R1) bits 47225, last segment flag (LSF) bit 47235, sequence number (SN) field 47240, segment offset (SO) field 47245, and one or more octets of data 47205. According to some aspects, the value of an SF bit 47230 contained in a UMD PDU 47220, UMD PDU segment 47250, AMD PDU 47260 or AMD PDU segment 47280 may indicate whether the PDU is a one of a UMD PDU or AMD PDU, or one of a UMD PDU segment or AMD PDU segment, where a value of 0 may indicate that the PDU is one of a UMD PDU or AMD PDU and a value of 1 may indicate that the PDU is one of a UMD PDU segment or AMD PDU segment. According to some aspects, the P bit contained in an AMD PDU 47260 or AMD PDU segment 47280 may be set to a value that indicates whether a transmitting AMD PDU entity 47230 is requesting that a peer receiving AMD PDU entity 47230 respond by sending a STATUS PDU 47290. According to some aspects, the value of an LSF bit 47235 contained in a UMD PDU segment 47250 or AMD PDU segment 47280 may be set to indicate whether the UMD PDU segment or AMD PDU segment respectively contains the last segment of a UMD PDU or AMD PDU respectively. According to some aspects, the value of a SN field 47240 contained in a UMD PDU 47220 or AMD PDU 47260 may indicate a sequence number of the PDU. According to some aspects, the value of a SN field contained in a UMD PDU segment 47250 or AMD PDU segment 47280 may indicate a sequence number of a UMD PDU, of which the UMD PDU segment or AMD PDU segment is a segment. A STATUS PDU 47290 that may be transmitted and received by an AM entity 47130 according to some aspects is illustrated in FIG. 260F. According to some aspects, a STATUS PDU 47290 may contain one of each of a D/C bit 47265 and a control protocol type (CPT) field. According to some aspects, a CPT field contained in a STATUS PDU 47290 may be set to a value which indicates that the PDU is a STATUS PDU. According to some aspects, a STATUS PDU 47290 may contain an acknowledgement field group and zero or more negative acknowledgement field groups. According to some aspects, an acknowledgement field group may include an acknowledgement sequence number (ACK_SN) field, which may be 18 bits long, and an extension 1 (E1) bit which may be set to a value indicating whether the acknowledgement field group is followed by one or more negative acknowledgement field groups. According to some aspects, a negative acknowledgement field group may include a negative acknowledgement sequence number (NACK_SN) field, which may be 18 bits long, followed by an E1 bit, an extension 2 (E2) bit, an extension 3 (E3) bit and zero, one or two optional fields, the E1 bit set to a value which indicates whether the negative acknowledgement field group is followed by an additional negative acknowledgement field group, the E2 bit set to a value which indicates whether the optional fields include a segment offset start (SOstart) field and the E3 bit set to a value which indicates whether the optional fields include a segment offset end (SOend) field. Aspects of functions which may be contained within a packet data convergence protocol (PDCP) layer entity 47300 are illustrated in FIG. 261. According to some aspects, PDCP layer entity 47300 may contain one or more of sequence numbering, duplicate detection and reordering circuitry 47325, header compression and decompression circuitry 47330, integrity protection and verification circuitry 47335, ciphering and deciphering circuitry 47340, and encapsulation and de-capsulation circuitry 47345. According to some aspects, a higher layer entity may exchange PDCP service data units (SDU) 47305 with PDCP layer entity 47300 via SAP 47310. According to some aspects, PDCP layer entity 47300 may exchange PDCP protocol data units (PDU) 47315 with a lower layer protocol entity via SAP 47320. According to some aspects, PDCP layer entity 47300 may include a control unit 47350, which may provide configuration and control inputs to, and receive status information from, one or more of sequence numbering, duplicate detection and reordering circuitry 47325, header compression and decompression circuitry 47330, integrity protection and verification circuitry 47335, ciphering and deciphering circuitry 47340 and encapsulation and de-capsulation circuitry 47345. According to some aspects, PDCP layer entity 47300 may include memory 47355, which may be used to store one or more of configuration parameters and state information. According to some aspects, a higher layer entity may exchange control and status messages 47360 with control unit 47350 via an interface 47365. A PDCP PDU 47400 that may be transmitted and received by a PDCP entity 47300 according to some aspects is illustrated in FIG. 262. According to some aspects, a PDCP PDU 47400 may contain one or more of each of a reserved (R) bit 47405, a PDCP sequence number (SN) field 47410, one or more octets of data 47420 and a four octet message authentication code for data integrity (MAC-I) field 47420. Aspects of communication between instances of radio resource control (RRC) layer 47500 are illustrated in FIG. 263. According to an aspect, an instance of RRC 47500 contained in a user equipment (UE) 47505 may encode and decode messages, transmitted to and received from respectively, a peer RRC instance 47500 contained in a base station 47510, which may be an evolved node B (eNodeB), gNodeB or other base station instance. According to an aspect, an RRC 47500 instance may encode or decode broadcast messages, which may include one or more of system information, cell selection and reselection parameters, neighboring cell information, common channel configuration parameters, and other broadcast management information. According to an aspect, an RRC 47500 instance may encode or decode RRC connection control messages, which may include one or more of paging information, messages to establish, modify, suspend, resume or release RRC connection, messages to assign or modify UE identity, which may include a cell radio network temporary identifier (C-RNTI), messages to establish, modify or release a signaling radio bearer (SRB), data radio bearer (DRB) or QoS flow, messages to establish, modify or release security associations including integrity protection and ciphering information, messages to control inter-frequency, intra-frequency and inter-radio access technology (RAT) handover, messages to recover from radio link failure, messages to configure and report measurement information, and other management control and information functions. States of an RRC 47500 that may be implemented in a user equipment (UE) in some aspects are illustrated in FIG. 264. According to some aspects, an RRC entity 47500 may be in one of the states NR RRC Connected 47605, NR RRC Inactive 47628 or NR RRC Idle 47625 when connected to or camped on a cell belonging to a 5G new radio (NR) network. According to some aspects, an RRC entity 47500 may be in one of the states E-UTRA RRC Connected 47610 or E-UTRA RRC Idle 47630 when connected to or camped on a cell belonging to a long term evolution (LTE) network. According to some aspects, an RRC entity 47500 may be in one of the states CELL_DCH 47615, CELL_FACH 47645, CELL_PCH/URA_PCH 47645 or UTRA_Idle 47635 when connected to or camped on a cell belonging to a universal mobile telecommunication system (UMTS) network. According to some aspects, an RRC entity 47500 may be in one of the states GSM_Connected/GPRS_Packet_Transfer_Mode 47620 or GSM_Idle/GPRS_Packet_Idle 47640 when connected to or camped on a cell belonging to a global system for mobile telecommunication (GSM) network. According to some aspects, an RRC entity 47500 may transition from one of the states in the set consisting of NR RRC Connected 47605, E-UTRA RRC Connected 47610, CELL_DCH 47615, CELL_FACH 47645, and GSM_Connected/GPRS_Packet_Transfer_Mode 47640, which may be termed connected states, to another state in the same set via a handover transition 47660. According to some aspects, an RRC Entity 47500 may transition from one of the states in the set consisting of NR RRC Idle 47625, E-UTRA RRC Idle 47630, UTRA_Idle 47635, and GSM_Idle/GPRS_Packet_Idle 47640, which may be termed idle states, to another state in the same set via a cell reselection transition 47680. According to some aspects, an RRC entity 47500 may transition between states NR RRC Connected 47605 and NR RRC Idle 47625, via an RRC connect/disconnect transition 47670. According to some aspects, an RRC entity 47500 may transition between states E-UTRA RRC Connected 47610 and E-UTRA RRC Idle 47630, via an RRC connect/disconnect transition 47670. According to some aspects, an RRC entity 47500 may transition between states CELL_PCH/URA_PCH 47645 and UTRA_Idle 47635, via an RRC connect/disconnect transition 47670. According to some aspects, an RRC entity 47500 may transition between states GSM_Connected/GPRS_Packet_Transfer_Mode 47620 and GSM_Idle/GPRS_Packet_Idle 47640, via an RRC connect/disconnect transition 47670. The above detailed description includes references to the accompanying drawings, which form a part of the detailed description. The drawings show, by way of illustration, specific aspects in which the aspects of the disclosure can be practiced. These aspects are also referred to herein as “examples.” In the event of inconsistent usages between this document and those documents so incorporated by reference, the usage in the incorporated reference(s) should be considered supplementary to that of this document; for irreconcilable inconsistencies, the usage in this document controls. In this document, the terms “a” or “an” are used, as is common in patent documents, to include one or more than one, independent of any other instances or usages of “at least one” or “one or more.” In this document, the term “or” is used to refer to a nonexclusive or, such that “A or B” includes “A but not B,” “B but not A,” and “A and B,” unless otherwise indicated. In the appended claims, the terms “including” and “in which” are used as the plain-English equivalents of the respective terms “comprising” and “wherein.” Also, in the following claims, the terms “including” and “comprising” are open-ended, that is, a system, device, article, or process that includes elements in addition to those listed after such a term in a claim are still deemed to fall within the scope of that claim. Moreover, in the following claims, the terms “first,” “second,” and “third,” etc. are used merely as labels, and are not intended to impose numerical requirements on their objects. The above description is intended to be illustrative, and not restrictive. For example, the above-described examples (or one or more aspects thereof) may be used in combination with each other. Other aspects can be used, such as by one of ordinary skill in the art upon reviewing the above description. Also, in the above Detailed Description, various features may be grouped together to streamline the disclosure. This should not be interpreted as intending that an unclaimed disclosed feature is essential to any claim. Rather, inventive subject matter may lie in less than all features of a particular disclosed aspect. Thus, the following claims are hereby incorporated into the Detailed Description, with each claim standing on its own as a separate aspect. The scope of various aspects of the disclosure can be determined with reference to the appended claims, along with the full scope of equivalents to which such claims are entitled. EXAMPLES Example 665 is an apparatus of a communication device. The apparatus may comprise a digital polar transmitter. The digital polar transmitter may comprise: a rectangular-to-polar converter, a digital-to-time converter (DTC) and an output oscillator. The rectangular-to-polar converter may be configured to provide a polar output signal based on a rectangular input signal supplied thereto. The DTC may be configured to receive a radio frequency (RF) oscillator signal and in response provide a DTC output signal based on the polar output signal. The output oscillator may be configured to receive the DTC output signal and an output oscillator signal at a mmWave frequency. In example 666, the subject matter of example 665 optionally includes that the output oscillator may comprise a pulse shaper and an injection oscillator. The pulse shaper may be configured to receive the DTC output signal and provide harmonics of the DTC output signal at the mmWave frequency. The injection oscillator may be configured to receive the harmonic from the pulse shaper and lock the output oscillator signal to the harmonics to produce the output oscillator signal at the mmWave frequency. In example 667, the subject matter of example 666 optionally includes that the pulse shaper and injection oscillator form an integral circuit. In example 668, the subject matter of example 667 optionally includes that the integral circuit may comprise a tank circuit and an injection locking circuit. The tank circuit may comprise an inductor-capacitor combination configured to resonate at the mmWave frequency. The injection locking circuit may be configured to receive the harmonics of the DTC output signal and induce the tank circuit to resonate at the mmWave frequency. The injection locking circuit may comprise series-connected transistors to which the harmonics of the DTC output signal are supplied as gate voltages to inject current into the tank circuit. In example 669, the subject matter of any one or more of examples 665–668 optionally include that the DTC may comprise a time-interleaved DTC that comprises a plurality of individual DTCs configured to be triggered at different times. In example 670, the subject matter of example 669 optionally includes that the digital polar transmitter may further comprise a serial-to-parallel converter to convert the polar output signal from the rectangular-to-polar converter to a digital word, and supply the digital word to the plurality of individual DTCs to generate the DTC output signal. In example 671, the subject matter of example 670 optionally includes that the time-interleaved DTC may further comprise a logical combiner configured to combine outputs from the individual DTCs to generate the DTC output signal. In example 672, the subject matter of any one or more of examples 665–671 optionally include that the DTC may be configured to dynamically delay an edge of the RF oscillator signal every period to introduce phase modulation in generation of the DTC output signal. In example 673, the subject matter of example 672 optionally includes that the digital polar transmitter may further comprise a multi-modulus divider configured to reduce a frequency of the RF oscillator signal to an intermediate frequency and a digitally-controlled edge interpolator configured to receive the intermediate frequency and in response generate self-aligned phase signals based thereon at a higher frequency. In example 674, the subject matter of any one or more of examples 665–673 optionally include an antenna that may be configured to transmit a signal dependent on the output oscillator signal. Example 675 is a method of providing a mmWave frequency signal. The method may comprise receiving a reference oscillation signal and employing a multi-stage process to generate a phase modulated output signal at a mmWave frequency based on the reference oscillation signal. The multi-stage process may comprise reducing a frequency of the reference oscillation signal to a lower frequency signal; modulating, dependent on an input signal, a phase of the lower frequency signal at a digital-to-time converter (DTC) to generate a phase-modulated signal at a frequency higher than that of the lower frequency signal; transmitting the phase-modulated signal from the DTC to an oscillator circuit; and generating a phase-modulated signal at the mmWave frequency at the oscillator circuit based on the phase-modulated signal. In example 676, the subject matter of example 675 optionally includes that generating the phase-modulated signal at the mmWave frequency may comprise amplifying a harmonic of the phase-modulated signal and locking an oscillator signal of the oscillator circuit to the harmonic to generate the output oscillator signal. In example 677, the subject matter of example 676 optionally includes that locking the oscillator signal of the oscillator circuit to the harmonic may comprise injecting, via series connected transistors, current into a tank circuit to induce the tank circuit to resonate at the mmWave frequency. In example 678, the subject matter of any one or more of examples 675–677 optionally include that modulating the phase of the lower frequency signal may comprise providing a digital word to a plurality of individual DTCs of the DTC. The digital word may be dependent on the input signal. The modulating may further comprise triggering the individual DTCs based on the digital word. In example 679, the subject matter of example 678 optionally includes that modulating the phase of the lower frequency signal may comprise converting a rectangular input signal into a polar output signal and generating parallel copies of the digital word, to send the copies of the digital word to the individual DRCs, based on the polar output signal. In example 680, the subject matter of example 679 optionally includes that modulating the phase of the lower frequency signal may comprise logically combining outputs from the individual DTCs to generate the phase-modulated signal. In example 681, the subject matter of any one or more of examples 675–680 optionally include wherein modulating the phase of the lower frequency signal may comprise dynamically delaying an edge of the reference oscillator signal every period to introduce phase modulation to generate the phase-modulated signal. In example 682, the subject matter of example 681 optionally includes using edge interpolation to generate self-aligned phase signals based on the lower frequency signal. Example 683 is an apparatus of a digital polar transmitter. The apparatus may comprise means for converting a rectangular input signal into a polar output signal for a digital-to-time converter (DTC); means for receiving a reference oscillation signal; means for reducing a frequency of the reference oscillation signal to a lower frequency signal; means for modulating, depending on the input signal, a phase of the lower frequency signal at the DTC to generate a phase-modulated signal at a frequency higher than the lower frequency signal; means for transmitting the phase-modulated signal from the DTC to an oscillator circuit; and means for generating a phase-modulated signal at a mmWave frequency at the oscillator circuit based on the phase-modulated signal. In example 684, the subject matter of example 683 optionally includes means for amplifying a harmonic of the phase-modulated signal and means for locking an oscillator signal of the oscillator circuit to the harmonic to generate the output oscillator signal. In example 685, the subject matter of example 684 optionally includes means for injecting, via series connected transistors, current into a tank circuit to induce the tank circuit to resonate at the mmWave frequency. In example 686, the subject matter of any one or more of examples 683–685 optionally include means for providing a digital word to a plurality of individual DTCs of the DTC, the digital word dependent on the polar output signal; and means for triggering the individual DTCs based on the digital word. In example 687, the subject matter of example 686 optionally includes means for generating parallel copies of the digital word, to send to the individual DTCs, based on the polar output signal. In example 688, the subject matter of example 687 optionally includes means for logically combining outputs from the individual DTCs to generate the phase-modulated signal. In example 689, the subject matter of any one or more of examples 683–688 optionally include means for dynamically delaying an edge of the reference oscillator signal every period to introduce phase modulation to generate the phase-modulated signal. In example 690, the subject matter of example 689 optionally includes means for using edge interpolation to generate self-aligned phase signals based on the lower frequency signal. Example 691 is a computer-readable storage medium that stores instructions for execution by one or more processors of a communication device. The one or more processors may configure the communication device to reduce a frequency of a reference oscillation signal to a lower frequency signal. The one or more processors may further configure the communication device to modulate, at a digital-to-time converter (DTC), a phase of the lower frequency signal to generate a phase-modulated signal at the frequency of the reference oscillation signal. The one or more processors may further configure the communication device to transmit the phase-modulated signal from the DTC to an oscillator circuit. The one or more processors may further configure the communication device to generate a phase-modulated signal at a mmWave frequency at the oscillator circuit based on the phase-modulated signal. In example 692, the subject matter of example 691 optionally includes that the one or more processors may further configure the communication device to amplify a harmonic of the phase-modulated signal and lock an oscillator signal of the oscillator circuit to the harmonic to produce the output oscillator signal. In example 693, the subject matter of example 692 optionally includes that the one or more processors may further configure the communication device to inject, via series connected transistors, current into a tank circuit to induce the tank circuit to resonate at the mmWave frequency. In example 694, the subject matter of any one or more of examples 691–693 optionally include that the one or more processors may further configure the communication device to convert a rectangular input signal into a polar output signal. The one or more processors may further configure the communication device to provide a digital word to a plurality of individual DTCs of the DTC. The digital word may be dependent on the polar output signal. The one or more processors may further configure the communication device to trigger the individual DTCs based on the digital word. In example 695, the subject matter of example 694 optionally includes that the one or more processors may further configure the communication device to generate parallel copies of the digital word, to send to the individual DRCs, based on the polar output signal. In example 696, the subject matter of example 695 optionally includes that the one or more processors may further configure the communication device to logically combine outputs from the individual DTCs to generate the phase-modulated signal. Example 697 is an apparatus of a receiver. The apparatus may comprise a feedforward equalizer (FFE). The FFE may comprise a plurality of FFE stages connected in series and to which vertically and horizontally polarized in-phase (I) and quadrature-phase (Q) signals are provided in parallel. Each FFE stage may comprise a plurality of delays. The vertically and horizontally polarized I and Q signals may be cross-coupled at a tap adjacent to each delay. The cross-coupling may be configured to provide cross-coupled vertically and horizontally polarized I and Q signals. In example 698, the subject matter of example 697 optionally includes that the delays may comprise: horizontal I delays on a horizontally polarized I signal line on which a horizontally polarized I input signal is provided, horizontal Q delays on a horizontally polarized Q signal line on which a horizontally polarized Q input signal is provided, vertically polarized I delays on a vertically polarized I signal line on which a vertically polarized I input signal is provided, and vertically polarized Q delays on a vertically polarized Q signal line on which a vertically polarized Q input signal is provided. In example 699, the subject matter of any one or more of examples 697–698 optionally include that each cross-coupling may comprise: a first set of multipliers each configured to weight the vertically polarized I signal supplied to the cross-coupling to produce a weighted vertically polarized I signal, a second set of multipliers each configured to weight the horizontally polarized I signal supplied to the cross-coupling to produce a weighted horizontally polarized I signal, a third set of multipliers each configured to weight the vertically polarized Q signal supplied to the cross-coupling to produce a weighted vertically polarized Q signal, a fourth set of multipliers each configured to weight the horizontally polarized Q signal supplied to the cross-coupling to produce a weighted horizontally polarized Q signal. In example 700, the subject matter of example 699 optionally includes that weighting coefficients of at least some of the first, second, third and fourth set of multipliers are independent of each other. In example 701, the subject matter of example 700 optionally includes that the weighting coefficients of at least one of the first, second, third and fourth set of multipliers are independent of the weighting coefficients of at least another of the first, second, third and fourth set of multipliers. In example 702, the subject matter of any one or more of examples 700–701 optionally include that each weighting coefficient within one of the first, second, third and fourth set of multipliers is independent of other weighting coefficients within the one of the first, second, third and fourth set of multipliers. In example 703, the subject matter of any one or more of examples 699–702 optionally include that each cross-coupling may comprise a first of the weighted vertically polarized I signals combined with a first of the weighted horizontally polarized I signals, a first of the weighted vertically polarized Q signals and a first of the weighted horizontally polarized Q signals to provide a combined I horizontal polarized signal, a second of the weighted horizontally polarized I signals combined with a second of the weighted vertically polarized I signals, a second of the weighted vertically polarized Q signals and a second of the weighted horizontally polarized Q signals to provide a combined vertically polarized I signal, a third of the weighted vertically polarized Q signals combined with a third of the weighted horizontally polarized I signals, a third of the weighted vertically polarized I signals and a third of the weighted horizontally polarized Q signals to provide a combined Q horizontal polarized signal, and a fourth of the weighted horizontally polarized Q signals combined with a fourth of the weighted vertically polarized I signals, a fourth of the weighted vertically polarized Q signals and a fourth of the weighted horizontally polarized I signals to provide a combined vertically polarized Q signal. In example 704, the subject matter of any one or more of examples 699–703 optionally include that in one of the FFE stages: the combined I horizontal polarized signal of each cross-coupling may be combined to form an output horizontally polarized I signal from the one of the FFE stages and the output horizontally polarized I signal may be provided one of as an input horizontally polarized I signal to another FFE stage or as an output horizontally polarized I signal of the FFE. In the FFE stage, the combined vertically polarized I signal of each cross-coupling may be combined to form an output vertically polarized I signal from the one of the FFE stages and the output vertically polarized I signal may be provided one of as an input vertically polarized I signal to the other FFE stage or as an output vertically polarized I signal of the FFE. In the FFE stage, the combined Q horizontal polarized signal of each cross-coupling may be combined to form an output horizontally polarized Q signal from the one of the FFE stages and the output horizontally polarized Q signal is provided one of as an input horizontally polarized Q signal to the other FFE stage or as an output horizontally polarized Q signal of the FFE; and the combined vertically polarized Q signal of each cross-coupling is combined to form an output vertically polarized Q signal from the one of the FFE stages and the output vertically polarized Q signal is provided one of as an input vertically polarized Q signal to the other FFE stage or as an output vertically polarized Q signal of the FFE. In example 705, the subject matter of any one or more of examples 697–704 optionally include that a number of taps is the same in each FFE stage. In example 706, the subject matter of any one or more of examples 697–705 optionally include that a number of taps in at least one FFE stage is different from a number of taps in at least one other FFE stage. In example 707, the subject matter of example 706 optionally includes that a number of taps tapers across the FFE stages. In example 708, the subject matter of any one or more of examples 699–707 optionally include that a number of taps corresponds to a number of pre-cursor inter-symbol interference (ISI) to be cancelled, each tap configured to cancel a different pre-cursor ISI type. In example 709, the subject matter of example 708 optionally includes that each FFE stage comprises vertically polarized I (VI) signals, horizontally polarized I (HI) signals, vertically polarized Q (VQ) signals and horizontally polarized Q (HQ) signals, and the FFE is configured to cancel direct ISI that include VI-to-VI, VQ-to-VQ, HI-to-HI, HQ-to-HQ ISI and crosstalk ISI that include VI-to-VQ, VI-to-HI, VI-to-HQ, VQ-to-VI, VQ-to-HI, VQ-to-HQ, HI-to-VI, HI-to-VQ, HI-to-HQ, HQ-to-VI, HQ-to-VQ, HQ-to-HI ISI. In example 710, the subject matter of any one or more of examples 697–709 optionally include that each weighting coefficients for the vertically and horizontally I and Q polarized signals in each FFE stage is adjusted while the FFE is in operation. In example 711, the subject matter of example 710 optionally includes that the weighting coefficients, other than at an initial tap, are each initially set to a pre-defined value prior to convergence and stabilization. In example 712, the subject matter of any one or more of examples 697–711 optionally include an antenna that provides input signals to the FFE. Example 713 is a method of providing analog signal equalization. The method may comprise providing a plurality of types of signals to a plurality of series-connected feedforward equalizer (FFE) stages of a FFE. The plurality of types of signals may comprise vertically and horizontally polarized in-phase (I) and quadrature-phase (Q) signals (VI, VQ, HI and HQ signals). The method may further comprise at a first of the FFE stages, delaying input VI, VQ, HI and HQ signals through a series of delays to form a plurality of sets of delayed VI, VQ, HI and HQ signals. Each set of delayed VI, VQ, HI and HQ signals may be associated with a different tap of a plurality of taps. The method may further comprise at the first of the FFE stages weighting each of the VI, VQ, HI and HQ signals at each tap with each of a plurality of types of weighting coefficients to form VI, VQ, HI and HQ weighted signals at the tap. The plurality of types of weighting coefficients may comprise VI, VQ, HI and HQ weighting coefficients. The method may further comprise at the first of the FFE stages combining the VI weighted signals at each tap to form a VI output signal, the VQ weighted signals at each tap to form a VQ output signal, the HI weighted signals at each tap to form a HI output signal and the HQ weighted signals at each tap to form a HQ output signal. The method may further comprise at the first of the FFE stages providing each of the VI, VQ, HI and HQ output signal one of as a VI, VQ, HI and HQ input signal to another FFE stage or as a VI, VQ, HI and HQ output of the FFE. In example 714, the subject matter of example 713 optionally includes using the VI, VQ, HI and HQ weighted signals at each tap to cancel a different pre-cursor inter-symbol interference (ISI) type. In example 715, the subject matter of any one or more of examples 713–714 optionally include that at least some of the VI, VQ, HI and HQ weighting coefficients are independent of each other. In example 716, the subject matter of any one or more of examples 713–715 optionally include that each type of weighting coefficient of one type of signal is independent of each other type of weighting coefficient of the one type of signal. In example 717, the subject matter of any one or more of examples 713–716 optionally include that one type of weighting coefficient of each type of signal is independent of the one type of weighting coefficient of each other type of signal. In example 718, the subject matter of any one or more of examples 713–717 optionally include repeating the delaying, weighting and combining on input signals for successive FFE stages. In example 719, the subject matter of any one or more of examples 713–718 optionally include that a number of taps is the same in each FFE stage. In example 720, the subject matter of any one or more of examples 713–719 optionally include that a number of taps tapers across the FFE stages. In example 721, the subject matter of any one or more of examples 713–720 optionally include initially setting the VI, VQ, HI and HQ weighting coefficients for each of the VI, VQ, HI and HQ signal, other than at an initial tap, to a pre-defined value and updating the VI, VQ, HI and HQ weighting coefficients during an adaption process to converge and stabilize the VI, VQ, HI and HQ weighting coefficients during the weighting. Example 722 is an apparatus of a communication device. The apparatus may comprise means for providing a plurality of types of signals to a plurality of series-connected feedforward equalizer (FFE) stages of a FFE. The plurality of types of signals may comprise vertically and horizontally polarized in-phase (I) and quadrature-phase (Q) signals (VI, VQ, HI and HQ signals); at a first of the FFE stages. The apparatus may further comprise means for delaying input VI, VQ, HI and HQ signals through a series of delays to form a plurality of sets of delayed VI, VQ, HI and HQ signals. Each set of delayed VI, VQ, HI and HQ signals may be associated with a different tap of a plurality of taps. The apparatus may further comprise means for weighting each of the VI, VQ, HI and HQ signals at each tap with each of a plurality of types of weighting coefficients to form VI, VQ, HI and HQ weighted signals at the tap. The plurality of types of weighting coefficients may comprise VI, VQ, HI and HQ weighting coefficients. The apparatus may further comprise means for combining the VI weighted signals at each tap to form a VI output signal, the VQ weighted signals at each tap to form a VQ output signal, the HI weighted signals at each tap to form a HI output signal and the HQ weighted signals at each tap to form a HQ output signal. The apparatus may further comprise means for providing each of the VI, VQ, HI and HQ output signal one of as a VI, VQ, HI and HQ input signal to another FFE stage or as a VI, VQ, HI and HQ output of the FFE. In example 723, the subject matter of example 722 optionally includes means for using the VI, VQ, HI and HQ weighted signals at each tap to cancel a different pre-cursor inter-symbol interference (ISI) type. In example 724, the subject matter of any one or more of examples 722–723 optionally include that at least some of the VI, VQ, HI and HQ weighting coefficients are independent of each other. In example 725, the subject matter of any one or more of examples 722–724 optionally include that each type of weighting coefficient of one type of signal is independent of each other type of weighting coefficient of the one type of signal. In example 726, the subject matter of any one or more of examples 722–725 optionally include that one type of weighting coefficient of each type of signal is independent of the one type of weighting coefficient of each other type of signal. In example 727, the subject matter of any one or more of examples 722–726 optionally include means for repeating the delaying, weighting and combining on input signals for successive FFE stages. In example 728, the subject matter of any one or more of examples 722–727 optionally include that a number of taps is the same in each FFE stage. In example 729, the subject matter of any one or more of examples 722–728 optionally include that a number of taps tapers across the FFE stages. In example 730, the subject matter of any one or more of examples 722–729 optionally include means for initially setting the VI, VQ, HI and HQ weighting coefficients for each of the VI, VQ, HI and HQ signal, other than at an initial tap, to a pre-defined value; and means for updating the VI, VQ, HI and HQ weighting coefficients during an adaption process to converge and stabilize the VI, VQ, HI and HQ weighting coefficients during the weighting. Example 731 is a computer-readable storage medium that stores instructions for execution by one or more processors of a communication device. The instructions may be configured to instruct the one or more processors to provide a plurality of types of signals to a plurality of series-connected feedforward equalizer (FFE) stages of a FFE. The plurality of types of signals may comprise vertically and horizontally polarized in-phase (I) and quadrature-phase (Q) signals (VI, VQ, HI and HQ signals). The instructions may further be configured to instruct the one or more processors to, at a first of the FFE stages, delay input VI, VQ, HI and HQ signals through a series of delays to form a plurality of sets of delayed VI, VQ, HI and HQ signals. Each set of delayed VI, VQ, HI and HQ signals may be associated with a different tap of a plurality of taps. The instructions may further be configured to instruct the one or more processors to, at the first of the FFE stages, weight each of the VI, VQ, HI and HQ signals at each tap with each of a plurality of types of weighting coefficients to form VI, VQ, HI and HQ weighted signals at the tap. The plurality of types of weighting coefficients may comprise VI, VQ, HI and HQ weighting coefficients. The instructions may further be configured to instruct the one or more processors to, at the first of the FFE stages, combine the VI weighted signals at each tap to form a VI output signal, the VQ weighted signals at each tap to form a VQ output signal, the HI weighted signals at each tap to form a HI output signal and the HQ weighted signals at each tap to form a HQ output signal. The instructions may further be configured to instruct the one or more processors to, at the first of the FFE stages, provide each of the VI, VQ, HI and HQ output signal one of as a VI, VQ, HI and HQ input signal to another FFE stage or as a VI, VQ, HI and HQ output of the FFE. In example 732, the subject matter of example 731 optionally includes wherein the instructions further instruct the one or more processors to use the VI, VQ, HI and HQ weighted signals at each tap to cancel a different pre-cursor inter-symbol interference (ISI) type. In example 733, the subject matter of any one or more of examples 731–732 optionally include that at least some of the VI, VQ, HI and HQ weighting coefficients are independent of each other. In example 734, the subject matter of any one or more of examples 731–733 optionally include that each type of weighting coefficient of one type of signal is independent of each other type of weighting coefficient of the one type of signal. In example 735, the subject matter of any one or more of examples 731–734 optionally include that one type of weighting coefficient of each type of signal is independent of the one type of weighting coefficient of each other type of signal. In example 736, the subject matter of any one or more of examples 731–735 optionally include that the instructions further instruct the one or more processors to repeating the delaying, weighting and combining on input signals for successive FFE stages. In example 737, the subject matter of any one or more of examples 731–736 optionally include that a number of taps is the same in each FFE stage. In example 738, the subject matter of any one or more of examples 731–737 optionally include that a number of taps tapers across the FFE stages. In example 739, the subject matter of any one or more of examples 731-738 optionally include that the instructions further instruct the one or more processors to initially set the VI, VQ, HI and HQ weighting coefficients for each of the VI, VQ, HI and HQ signal, other than at an initial tap, to a pre-defined value; and update the VI, VQ, HI and HQ weighting coefficients during an adaption process to converge and stabilize the VI, VQ, HI and HQ weighting coefficients during the weighting. Example 740 is an apparatus of a receiver. The apparatus may comprise a Decision Feedback Equalizer (DFE). The DFE may comprise a path having a serial chain and parallel chains. The serial chain may be configured to provide a 1 bit output, and a 2 bit, most significant bit (MSB) and least significant bit (LSB), output. The apparatus may further comprise a selector configured to select between the serial and parallel chains and a plurality of taps disposed along the path. A number of taps may be dependent on which of the serial chain and parallel chains is selected by the selector. Outputs from the taps may be configured to compensate for post-cursor inter-symbol interference (ISI). In example 741, the subject matter of example 740 optionally includes a plurality of delays each triggered by a clock signal. Each tap may be taken from an output of a different delay. In example 742, the subject matter of example 741 optionally includes that each delay comprises a D flipflop. In example 743, the subject matter of example 742 optionally include that the selector comprises a plurality of multiplexers. Each multiplexer may be associated with a different delay and having an output connected with an input of the associated delay. In example 744, the subject matter of example 743 optionally includes that each multiplexer is connected with a same selector signal. The selector signal may be configured to control selection of which of the serial chain and parallel chains is used by the DFE. In example 745, the subject matter of example 744 optionally includes that inputs of each selector comprise an output from a previous delay in the serial chain and an output from a previous delay in the parallel chains. In example 746, the subject matter of any one or more of examples 740–745 optionally include that the selector is configured to select a chain type based on a modulation scheme. The chain type may comprise the serial chain and the parallel chains. In example 747, the subject matter of example 746 optionally includes that the serial chain is selected for Quadrature Phase-Shift Keying (QPSK) and the parallel chains are selected for 16Quadrature Amplitude Modulation (16QAM) or higher. In example 748, the subject matter of any one or more of examples 740–747 optionally include that the taps comprise first and second taps and remaining taps after the first and second taps. The apparatus may further comprise a first and second latch disposed prior to the remaining taps. The first tap may be taken from an input of the first latch and the second tap may be taken from an output of the second latch. An output of the first latch may be connected with an input of the second latch. In example 749, the subject matter of example 748 optionally includes that in the serial chain. The output of the second latch may be connected with an input of a first of delays that form the serial chain. In example 750, the subject matter of any one or more of examples 748–749 optionally include that in the parallel chains: the MSB is taken from between the first and second latches; the LSB is taken from an output of a third latch; an output of the first latch is further connected with a selector input of a multiplexer; an output of the multiplexer is connected with an input of the third latch; and the second tap is taken from an output of the second and third latches. In example 751, the subject matter of any one or more of examples 740–750 optionally include that the taps comprise first and second taps and remaining taps after the first and second taps. The first tap may have a stringent delay constraint. Each of the remaining taps may be taken from an output of a different D flipflop. The first tap may be taken from an input of a first latch and the second tap taken from an output of a second latch. An output of the first latch and an input of the second latch may be connected together and connected with a selector input of a multiplexer in one of the parallel paths to avoid affecting a delay of the first tap when the multiplexer is present and the parallel paths are selected. In example 752, the subject matter of any one or more of examples 740–751 optionally include an antenna configured to receive radio frequency (RF) signals compensated by the DFE. Example 753 is a method of compensating for post-cursor inter-symbol interference (ISI) in a receiver. The method may comprise determining a modulation scheme of a signal received at a Decision Feedback Equalizer (DFE) in the receiver. The method may further comprise based on the modulation scheme, determining a tap number of taps to use in the DFE. The method may further comprise selecting which of a serial chain and parallel chains to use in the DFE based on the tap number. The serial chain and parallel chains may have different tap numbers. The method may further comprise compensating for post-cursor ISI of the signal using outputs from the taps. In example 754, the subject matter of example 753 optionally includes simultaneously trigging a plurality of delays. Each tap may be taken from an output of a different delay. In example 755, the subject matter of any one or more of examples 753–754 optionally include that the selecting which of a serial chain and parallel chains to use may comprise applying a same selector signal to a plurality of multiplexers that are each associated with a different delay and have an output connected with an input of the associated delay. In example 756, the subject matter of any one or more of examples 753–755 optionally include that the selecting which of a serial chain and parallel chains to may comprise selecting the serial chain for Quadrature Phase-Shift Keying (QPSK) and the parallel chains for 16Quadrature Amplitude Modulation (16QAM) or higher. In example 757, the subject matter of any one or more of examples 753–756 optionally include that when the parallel chains are selected, the method may further comprise selecting a least significant bit (LSB) using a latched output between a first and second of the taps of a most significant bit (MSB). In example 758, the subject matter of any one or more of examples 753–757 optionally include that the taps comprise first and second taps and remaining taps after the first and second taps. The first tap may have a stringent delay constraint. The method may further comprise avoiding affecting a delay of the first tap when the parallel paths are selected by: taking the first tap from an input of a first latch and the second tap from an output of a second latch; and connecting an output of the first latch with an input of the second latch in a first of the parallel paths and with a selector input of a multiplexer in a second of the parallel paths. Example 759 is an apparatus of a Decision Feedback Equalizer (DFE). The apparatus may comprise means for determining a modulation scheme of a signal received at the DFE. The apparatus may further comprise means for determining, based on the modulation scheme, the tap number of taps to use in the DFE. The apparatus may further comprise means for selecting which of a serial chain and parallel chains to use in the DFE based on the tap number. The serial chain and parallel chains may have different tap numbers. The apparatus may further comprise means for compensating for post-cursor inter-symbol interference (ISI) of the signal using outputs from the taps. In example 760, the subject matter of example 759 optionally includes means for simultaneously trigging a plurality of delays. Each tap may be taken from an output of a different delay. In example 761, the subject matter of any one or more of examples 759–760 optionally include that the means for selecting which of a serial chain and parallel chains to use comprises means for applying a same selector signal to a plurality of multiplexers that are each associated with a different delay and have an output connected with an input of the associated delay. In example 762, the subject matter of any one or more of examples 759–761 optionally include that the means for selecting which of a serial chain and parallel chains to use comprises means for selecting the serial chain for Quadrature Phase-Shift Keying (QPSK) and the parallel chains for 16Quadrature Amplitude Modulation (16QAM) or higher. In example 763, the subject matter of any one or more of examples 759–762 optionally include that when the parallel chains are selected, the apparatus may further comprise means for selecting a least significant bit (LSB) using a latched output between a first and second of the taps of a most significant bit (MSB). In example 764, the subject matter of any one or more of examples 759–763 optionally include that the taps comprise first and second taps and remaining taps after the first and second taps. The first tap may have a stringent delay constraint. The apparatus may further comprise means for avoiding affecting a delay of the first tap when the parallel paths are selected by providing: means for taking the first tap from an input of a first latch and the second tap from an output of a second latch; and means for connecting an output of the first latch with an input of the second latch in a first of the parallel paths and with a selector input of a multiplexer in a second of the parallel paths. Example 765 is a computer-readable storage medium that stores instructions for execution by one or more processors of a communication device. The instructions may be configured to instruct the one or more processors to determine a modulation scheme of a signal received at a Decision Feedback Equalizer (DFE). The instructions may further be configured to instruct the one or more processors to, based on the modulation scheme, determine the tap number of taps to use in the DFE. The instructions may further be configured to instruct the one or more processors to select which of a serial chain and parallel chains to use in the DFE based on the tap number. The serial chain and parallel chains may have different tap numbers. The instructions may further be configured to instruct the one or more processors to compensate for post-cursor inter-symbol interference (ISI) of the signal using outputs from the taps. In example 766, the subject matter of example 765 optionally includes that the instructions are further configured to instruct the one or more processors to simultaneously trigger a plurality of delays. Each tap may be taken from an output of a different delay. In example 767, the subject matter of any one or more of examples 765–766 optionally include that the instructions are further configured to instruct the one or more processors to apply a same selector signal to a plurality of multiplexers that are each associated with a different delay and have an output connected with an input of the associated delay. In example 768, the subject matter of any one or more of examples 765–767 optionally include that the instructions are further configured to instruct the one or more processors to select the serial chain for Quadrature Phase-Shift Keying (QPSK) and the parallel chains for 16Quadrature Amplitude Modulation (16QAM) or higher. In example 769, the subject matter of any one or more of examples 765–768 optionally include that the instructions are further configured to instruct the one or more processors to select a least significant bit (LSB) using a latched output between a first and second of the taps of a most significant bit (MSB). In example 770, the subject matter of any one or more of examples 765–769 optionally include that the taps comprise first and second taps and remaining taps after the first and second taps. The first tap may have a stringent delay constraint. The instructions may be further configured to instruct the one or more processors to avoid affecting a delay of the first tap when the parallel paths are selected by: taking the first tap from an input of a first latch and the second tap from an output of a second latch; and connecting an output of the first latch with an input of the second latch in a first of the parallel paths and with a selector input of a multiplexer in a second of the parallel paths. Example 771 is an apparatus of a mmWave communication device. The apparatus may comprise at least one of: a receiver hybrid beamforming architecture configured to receive mmWave beamformed signals or a transmitter hybrid beamforming architecture configured to transmit mmWave beamformed signals. The receiver hybrid beamforming architecture may be configured to receive mmWave beamformed signals and the transmitter hybrid beamforming architecture may be configured to transmit mmWave beamformed signals. The receiver hybrid beamforming architecture may comprise an analog receiver beamforming structure and a digital receiver beamforming structure that comprise different numbers of analog-to-digital converters (ADCs) that have different resolutions. The transmitter hybrid beamforming architecture may comprise an analog transmitter beamforming structure and a digital transmitter beamforming structure that comprise different numbers of digital-to-analog converters (DACs) that have different resolutions. In example 772, the subject matter of example 771 optionally includes that the analog receiver beamforming structure comprises an ADC and the analog transmitter beamforming structure comprises a DAC, and the digital receiver beamforming structure comprises a plurality of ADCs and the digital transmitter beamforming structure comprises a plurality of DACs. In example 773, the subject matter of example 772 optionally includes that the resolution of the ADC is higher than the resolution of each of the plurality of ADCs, and the resolution of the DAC is higher than the resolution of each of the plurality of DACs. In example 774, the subject matter of example 773 optionally includes that the resolution of each of the plurality of ADCs is variable. In example 775, the subject matter of any one or more of examples 772-774 optionally include that each of the analog receiver and transmitter beamforming structure may further comprise a phase shifter associated each of the antennas and a combiner connected with each phase shifter. In example 776, the subject matter of any one or more of examples 772-775 optionally include that the receiver hybrid beamforming architecture may further comprise a receiver switch associated with each antenna, the receiver switch controlling which of the analog and digital receiver beamforming structure is selected. The transmitter hybrid beamforming architecture may further comprise a transmitter switch associated with each antenna. The transmitter switch may control which of the analog and digital transmitter beamforming structure is selected. At least one of the receiver or transmitter switch may be controlled based on a channel type of a channel on which radio frequency (RF) signals are communicated by the antennas, a signal type of the RF signals, channel conditions, mobility of a user equipment (UE), or modulation scheme. In example 777, the subject matter of example 776 optionally includes that the at least one of the receiver or transmitter switch selects analog beamforming in response to the channel type being line of sight (LOS), a high order modulation scheme is used, and a high signal to noise ratio (SNR) and low mobility are present. In example 778, the subject matter of any one or more of examples 776-777 optionally include that the at least one of the receiver or transmitter switch selects digital beamforming in response to at least one of: the signal type being a control signal and a low order modulation scheme is used; or the signal type being a data signal, the channel type being non-line of sight (NLOS), and a low SNR is present. In example 779, the subject matter of any one or more of examples 771-778 optionally include that the receiver hybrid beamforming architecture comprises shared analog receiver components that comprise for each antenna: a low noise amplifier configured to amplify a complex radio frequency (RF) signal from the antenna, mixers configured to downconvert in-phase and quadrature-phase components of the RF signal to baseband, a variable gain connected to each mixer and a low pass filter configured to provide low pass filtering of an output from each variable gain. In example 780, the subject matter of any one or more of examples 771-779 optionally include a plurality of antennas configured to communicate mmWave signals. Example 781 is a method of communicating beamformed mmWave signals. The method may comprise determining channel and signal characteristics of mmWave signals to be communicated. The method may further comprise, based on a determination from the channel and signal characteristics of the mmWave signals that high-resolution quantization or conversion from digital to analog is to be used, selecting an analog beamforming architecture, of a hybrid beamforming architecture that comprises the analog beamforming architecture and a digital beamforming architecture, to use in communicating the mmWave signals. The method may further comprise based on a determination from the channel and signal characteristics of the mmWave signals that low-resolution quantization or conversion from digital to analog is to be used, selecting the digital beamforming architecture to use in communicating the mmWave signals. The method may further comprise communicating the mmWave signals via beamforming using the analog or digital beamforming architecture selected. A number of converters in the analog and digital beamforming architecture may be different. In example 782, the subject matter of example 781 optionally includes that the analog beamforming structure comprises either an analog-to-digital converter (ADC) or a digital-to-analog converter (DAC), and the digital beamforming structure comprises either a plurality of ADCs or a plurality of DACs. In example 783, the subject matter of example 782 optionally includes that a resolution of each of the ADCs and DACs is fixed. In example 784, the subject matter of any one or more of examples 782-783 optionally include varying a resolution of each of the ADCs and DACs dependent on the channel and signal characteristics of the mmWave signals. In example 785, the subject matter of any one or more of examples 782-784 optionally include when the analog beamforming architecture is selected, the method further comprises phase shifting each of the mmWave signals to produce phase shifted signals and combining the phase shifted signals to form a combined signal to be quantized. In example 786, the subject matter of any one or more of examples 782-785 optionally include controlling selection of the analog or digital beamforming architecture based at least on which of a line of sight (LOS) or non-LOS (NLOS) channel is to be used to communicate the mmWave signals, which of a control or data signal the mmWave signals are, a signal to noise ratio (SNR), and a modulation scheme to be used to communicate the mmWave signals. In example 787, the subject matter of example 786 optionally includes that the analog beamforming architecture is selected in response to the channel type being LOS, a high order modulation scheme being used, and a high SNR and low mobility. In example 788, the subject matter of any one or more of examples 786-787 optionally include that the digital beamforming architecture is selected in response to at least one of: the signal type being a control signal and a low order modulation scheme being used; or the signal type being a data signal, the channel type is NLOS, and a low SNR is present. In example 789, the subject matter of any one or more of examples 781-788 optionally include sharing analog components between the analog and digital beamforming architecture. The shared analog components may comprise a low noise amplifier configured to amplify the mmWave signals, mixers configured to downconvert in-phase and quadrature-phase components of the mmWave signals to baseband, a variable gain connected to each mixer and a low pass filter configured to provide low pass filtering of an output from each variable gain. Example 790 is an apparatus of a communication device. The apparatus may comprise means for determining channel and signal characteristics of mmWave signals to be communicated. The apparatus may further comprise, based on a determination from the channel and signal characteristics of the mmWave signals that high-resolution quantization or conversion from digital to analog is to be used, means for selecting an analog beamforming architecture, of a hybrid beamforming architecture that comprises the analog beamforming architecture and a digital beamforming architecture, to use in communicating the mmWave signals. The apparatus may further comprise, based on a determination from the channel and signal characteristics of the mmWave signals that low-resolution quantization or conversion from digital to analog is to be used, means for selecting the digital beamforming architecture to use in communicating the mmWave signals. The apparatus may further comprise, means for communicating the mmWave signals via beamforming using the analog or digital beamforming architecture selected. A number of converters in the analog and digital beamforming architecture may be different. In example 791, the subject matter of example 790 optionally includes that the analog beamforming structure comprises either an analog-to-digital converter (ADC) or a digital-to-analog converter (DAC), and the digital beamforming structure comprises either a plurality of ADCs or a plurality of DACs. In example 792, the subject matter of example 791 optionally includes that a resolution of each of the ADCs and DACs is fixed. In example 793, the subject matter of any one or more of examples 791-792 optionally include means for varying a resolution of each of the ADCs and DACs dependent on the channel and signal characteristics of the mmWave signals. In example 794, the subject matter of any one or more of examples 790-793 optionally include when the analog beamforming architecture is selected, the apparatus further comprises means for phase shifting each of the mmWave signals to generate phase shifted signals and means for combining the phase shifted signals to form a combined signal to be quantized. In example 795, the subject matter of any one or more of examples 790-794 optionally include means for controlling selection of the analog or digital beamforming architecture based at least on which of a line of sight (LOS) or non-LOS (NLOS) channel is to be used to communicate the mmWave signals, which of a control or data signal the mmWave signals are, a signal to noise ratio (SNR), and a modulation scheme to be used to communicate the mmWave signals. In example 796, the subject matter of example 795 optionally includes that the analog beamforming architecture is selected in response to the channel type being LOS, a high order modulation scheme being used, and a high SNR and low mobility. In example 797, the subject matter of any one or more of examples 795-796 optionally include that the digital beamforming architecture is selected in response to at least one of: the signal type being a control signal and a low order modulation scheme being used; or the signal type being a data signal, the channel type is NLOS, and a low SNR is present. In example 798, the subject matter of any one or more of examples 790-797 optionally include means for sharing analog components between the analog and digital beamforming architecture. The shared analog components may comprise a low noise amplifier configured to amplify the mmWave signals, mixers configured to downconvert in-phase and quadrature-phase components of the mmWave signals to baseband, a variable gain connected to each mixer and a low pass filter configured to provide low pass filtering of an output from each variable gain. Example 799 is a computer-readable storage medium that stores instructions for execution by one or more processors of a communication device. The instructions may be configured to instruct the one or more processors to determine channel and signal characteristics of mmWave signals to be communicated. The instructions may be further configured to instruct the one or more processors to, based on a determination from the channel and signal characteristics of the mmWave signals that high-resolution quantization or conversion from digital to analog is to be used, select an analog beamforming architecture, of a hybrid beamforming architecture that comprises the analog beamforming architecture and a digital beamforming architecture, to use in communicating the mmWave signals. The instructions may be further configured to instruct the one or more processors to, based on a determination from the channel and signal characteristics of the mmWave signals that low-resolution quantization or conversion from digital to analog is to be used, select the digital beamforming architecture to use in communicating the mmWave signals. The instructions may be further configured to instruct the one or more processors to, communicate the mmWave signals via beamforming using the analog or digital beamforming architecture selected. A number of converters in the analog and digital beamforming architecture may be different. In example 800, the subject matter of example 799 optionally includes that the analog beamforming structure comprises either a single analog-to-digital converter (ADC) or a single digital-to-analog converter (DAC), and the digital beamforming structure comprises either a plurality of ADCs or a plurality of DACs. In example 801, the subject matter of example 800 optionally includes that a resolution of each of the ADCs and DACs is fixed. In example 802, the subject matter of any one or more of examples 800-801 optionally include wherein the instructions further instruct the one or more processors to vary a resolution of each of the ADCs and DACs dependent on the channel and signal characteristics of the mmWave signals. In example 803, the subject matter of any one or more of examples 799-802 optionally include when the analog beamforming architecture is selected, the instructions further instruct the one or more processors to phase shift each of the mmWave signals to produce phase shifted signals and combine the phase shifted signals to form a combined signal to be quantized. In example 804, the subject matter of any one or more of examples 799-803 optionally include that the instructions further instruct the one or more processors to control selection of the analog or digital beamforming architecture based at least on which of a line of sight (LOS) or non-LOS (NLOS) channel is to be used to communicate the mmWave signals, which of a control or data signal the mmWave signals are, a signal to noise ratio (SNR), and a modulation scheme to be used to communicate the mmWave signals. In example 805, the subject matter of example 804 optionally includes that the analog beamforming architecture is selected in response to the channel type being LOS, a high order modulation scheme being used, and a high SNR and low mobility. In example 806, the subject matter of any one or more of examples 804-805 optionally include that the digital beamforming architecture is selected in response to at least one of: the signal type being a control signal and a low order modulation scheme being used; or the signal type being a data signal, the channel type is NLOS, and a low SNR is present. In example 807, the subject matter of any one or more of examples 799-806 optionally include wherein the instructions further instruct the one or more processors to share analog components between the analog and digital beamforming architecture. The shared analog components may comprise a low noise amplifier configured to amplify the mmWave signals, mixers configured to downconvert in-phase and quadrature-phase components of the mmWave signals to baseband, a variable gain connected to each mixer and a low pass filter configured to provide low pass filtering of an output from each variable gain. Example 808 is an apparatus of a mmWave communication device. The apparatus may comprise a receiver beamforming architecture configured to receive mmWave beamformed signals and a transmitter beamforming architecture configured to transmitmmWave beamformed signals. The receiver beamforming architecture may comprise a variable resolution analog-to-digital converter (ADC). The transmitter beamforming architecture may comprise a variable resolution digital-to-analog converter (DAC). A resolution of the ADC or DAC may be adapted to limit power consumption to a predetermined transceiver power dissipation constraint free from reducing a number of ADCs or DACs used in the receiver or transmitter beamforming architecture. In example 809, the subject matter of example 808 optionally includes that the receiver beamforming architecture comprises a hybrid receiver beamforming architecture that comprises an analog receiver beamforming architecture and a digital receiver beamforming architecture. The transmitter beamforming architecture may comprise a hybrid transmitter beamforming architecture that comprises an analog transmitter beamforming architecture and a digital transmitter beamforming architecture. In example 810, the subject matter of example 809 optionally includes that the analog receiver and transmitter beamforming architecture comprises an ADC and an DAC, respectively. The digital receiver and transmitter beamforming architecture may comprise a plurality of ADCs and DACs, respectively. In example 811, the subject matter of example 810 optionally includes that the analog receiver beamforming architecture comprises a combiner configured to combine complex mmWave signals from a plurality of antennas into a combined signal. The combined signal may be supplied to the single ADC as an input. In example 812, the subject matter of any one or more of examples 808-811 optionally include that a resolution of the ADC or DAC is dependent on at least one of: a channel used for communication, interference in the channel, signal to noise ratio (SNR), or a number of users in communication with the mmWave communication device. In example 813, the subject matter of any one or more of examples 809-812 optionally include that a resolution of the ADC or DAC is dependent on at least one of: signal type of the mmWave beamformed signals, signal quality of the mmWave beamformed signals, modulation used by the mmWave beamformed signals or apparatus operation associated with the mmWave beamformed signals. In example 814, the subject matter of example 813 optionally includes that the resolution of the ADC or DAC is decreased when the mmWave beamformed signals comprise control plane signaling. In example 815, the subject matter of any one or more of examples 813-814 optionally include that the resolution of the ADC or DAC decreases with increasing signal to noise ratio (SNR). In example 816, the subject matter of any one or more of examples 813-815 optionally include that the resolution of the ADC or DAC decreases with increasing modulation order. In example 817, the subject matter of any one or more of examples 813-816 optionally include that the resolution of the ADC or DAC decreases with increasing modulation order. In example 818, the subject matter of any one or more of examples 813-817 optionally include that the resolution of the ADC or DAC decreases with decreasing numbers of user equipment (UEs) being serviced by the communication device and decreasing Peak-to-Average Power Ratio (PAPR). In example 819, the subject matter of any one or more of examples 813-818 optionally include that the resolution of the ADC or DAC decreases when a measured DC offset falls below a predetermined set point. In example 820, the subject matter of any one or more of examples 813-819 optionally include that the resolution of the ADC or DAC decreases when the mmWave beamformed signals are part of an evolved NodeB (eNB) search. In example 821, the subject matter of any one or more of examples 813-820 optionally include that the resolution of the ADC or DAC decreases when the mmWave beamformed signals are a preamble or mid-amble. In example 822, the subject matter of any one or more of examples 813-821 optionally include that the resolution of the ADC or DAC increases when at least one of in-band or adjacent channel interference is strong enough to increase a dynamic range of the ADC or DAC. In example 823, the subject matter of any one or more of examples 813-822 optionally include that the resolution of the ADC or DAC increases when the channel is a non-line-of-sight (NLOS) channel and a number of multipath increases. In example 824, the subject matter of any one or more of examples 808-823 optionally include a plurality of antennas configured to communicate the mmWave beamformed signals. Example 825 is a method of communicating beamformed mmWave signals. The method may comprise at least one of receiving a first set of mmWave beamformed signals at a plurality of antennas or transmitting a second set of mmWave beamformed signals from the antennas. The method may further comprise setting a resolution of an analog-to-digital converter (ADC) used in the receiving and digital-to-analog converter (DAC) used in the transmitting based on a transceiver power dissipation constraint and free from reducing a number of ADCs or DACs. The method may further comprise converting the first or second set of mmWave beamformed signals between analog and digital signals based on the resolution of the ADC or DAC. In example 826, the subject matter of example 825 optionally includes selecting which of an analog beamforming architecture and a digital beamforming architecture of a hybrid beamforming architecture to use to receive or transmit the mmWave beamformed signals. In example 827, the subject matter of example 826 optionally includes adjusting the resolution of the ADC and DAC based on which of the analog and digital beamforming architecture is selected. In example 828, the subject matter of any one or more of examples 826-827 optionally include that the analog beamforming architecture comprises a single ADC for reception and a single DAC for transmission. The digital beamforming architecture may further comprise a plurality of ADCs for reception and a plurality of DACs for transmission. In example 829, the subject matter of any one or more of examples 826-828 optionally include combining complex mmWave signals received from the antennas into a combined signal and supplying the combined signal to the single ADC as an input. In example 830, the subject matter of any one or more of examples 825-829 optionally include that a resolution of the ADC or DAC is dependent on at least one of: a channel used for communication, interference in the channel, signal to noise ratio (SNR), or a number of users in communication with the mmWave communication device. In example 831, the subject matter of any one or more of examples 825-830 optionally include that a resolution of the ADC or DAC is dependent on at least one of: signal type of the mmWave beamformed signals, signal quality of the mmWave beamformed signals, modulation used by the mmWave beamformed signals or operation associated with the mmWave beamformed signals. Example 832 is an apparatus of a communication device. The apparatus may comprise means for receiving a first set of mmWave beamformed signals at a plurality of antennas and means for transmitting a second set of mmWave beamformed signals from the antennas. The apparatus may further comprise means for setting a resolution of an analog-to-digital converter (ADC) used in the receiving and digital-to-analog converter (DAC) used in the transmitting based on a transceiver power dissipation constraint and free from reducing a number of ADCs or DACs. The apparatus may further comprise means for converting the first or second set of mmWave beamformed signals between analog and digital signals based on the resolution of the ADC or DAC. In example 833, the subject matter of example 832 optionally includes means for selecting which of an analog beamforming architecture and a digital beamforming architecture of a hybrid beamforming architecture to use to receive or transmit the mmWave beamformed signals. In example 834, the subject matter of example 833 optionally includes means for adjusting the resolution of the ADC and DAC based on which of the analog and digital beamforming architecture is selected. In example 835, the subject matter of any one or more of examples 833-834 optionally include that the analog beamforming architecture comprises a single ADC for reception and a single DAC for transmission. The digital beamforming architecture may comprise a plurality of ADCs for reception and a plurality of DACs for transmission. In example 836, the subject matter of any one or more of examples 833-835 optionally include means for combining complex mmWave signals received from the antennas into a combined signal and means for supplying the combined signal to the single DAC as an input. In example 837, the subject matter of any one or more of examples 832-836 optionally include that a resolution of the ADC or DAC is dependent on at least one of: a channel used for communication, interference in the channel, signal to noise ratio (SNR), or a number of users in communication with the mmWave communication device. In example 838, the subject matter of any one or more of examples 825-837 optionally include that a resolution of the ADC or DAC is dependent on at least one of: signal type of the mmWave beamformed signals, signal quality of the mmWave beamformed signals, modulation used by the mmWave beamformed signals or operation associated with the mmWave beamformed signals. Example 839 is a computer-readable storage medium that stores instructions for execution by one or more processors of a communication device. The instructions may be configured to instruct the one or more processors to receive a first set of mmWave beamformed signals at a plurality of antennas and transmit a second set of mmWave beamformed signals from the antennas. The instructions may be further configured to set a resolution of an analog-to-digital converter (ADC) used in the receiving and digital-to-analog converter (DAC) used in the transmitting based on a transceiver power dissipation constraint and free from reducing a number of ADCs or DACs. The instructions may be further configured to convert the first or second set of mmWave beamformed signals between analog and digital signals based on the resolution of the ADC or DAC. In example 840, the subject matter of example 839 optionally includes wherein the instructions further instruct the one or more processors to select which of an analog beamforming architecture and a digital beamforming architecture of a hybrid beamforming architecture to use to receive or transmit the mmWave beamformed signals. In example 841, the subject matter of example 840 optionally includes wherein the instructions further instruct the one or more processors to adjust the resolution of the ADC and DAC based on which of the analog and digital beamforming architecture is selected. In example 842, the subject matter of any one or more of examples 840-841 optionally include that the analog beamforming architecture comprises a single ADC for reception and a single DAC for transmission. The digital beamforming architecture may comprise a plurality of ADCs for reception and a plurality of DACs for transmission. In example 843, the subject matter of any one or more of examples 840-842 optionally include that the instructions further instruct the one or more processors to combine complex mmWave signals received from the antennas into a combined signal and supply the combined signal to the single ADC as an input. In example 844, the subject matter of any one or more of examples 839-843 optionally include that a resolution of the ADC or DAC is dependent on at least one of: a channel used for communication, interference in the channel, signal to noise ratio (SNR), or a number of users in communication with the mmWave communication device. Example 845 is an apparatus of a communication device. The apparatus may comprise an analog or hybrid beamforming architecture that comprises a plurality of phase shifters configured to set a steering angle for antennas configured to communicate beamformed signals. The apparatus may further comprise a processor configured to determine a codebook to provide beam steering for the antennas. The codebook may be limited to a subset of steering angles of the antennas. The processor may further provide inputs to the phase shifters to set a particular steering angle outside the subset of steering angles through a determination of a limited steering angle within the subset of steering angles and an integer shift value to shift the limited steering angle to the particular steering angle. In example 846, the subject matter of example 845 optionally includes that the analog or hybrid beamforming architecture comprises a plurality of primary phase shifters and a plurality of secondary phase shifters. Each secondary phase shifter may be associated with a set of the primary phase shifters. The codebook may be configured to control values of the primary and secondary phase shifters. In example 847, the subject matter of example 846 optionally includes that the primary and secondary phase shifters are low bit phase shifters. In example 848, the subject matter of any one or more of examples 846-847 optionally include that the codebook further comprises a unitary multiplier to indicate whether the particular steering angle is set directly by the limited steering angle and shift value or whether the particular steering angle is set by a reflection of the limited steering angle and shift value around shift value about 180º. In example 849, the subject matter of example 848 optionally includes that the codebook is limited to steering angles between arccos(1/2^(b_p ) )°<ϕ≤90°, where bp is a number of bits of each primary phase shifter. In example 850, the subject matter of example 849 optionally includes that primary phase shifter values are limited to between [0,0,0,…,0] and [0,1,2,…,L-1] π/2^(b_p ) , where L is a number of primary phase shifters. In example 851, the subject matter of any one or more of examples 845-850 optionally include that the codebook is limited to steering angles between arccos(1/2^(b_p-1) )°<ϕ≤90°, where bp is a number of bits of each primary phase shifter. In example 852, the subject matter of any one or more of examples 846-851 optionally include that the secondary phase shifters are radio frequency or baseband phase shifters and the primary phase shifters are intermediate frequency or digital phase shifters. In example 853, the subject matter of any one or more of examples 845-852 optionally include that a plurality of antennas configured to be steered by the phase shifters to communicate the beamformed signals. Example 854 is a method of providing beam steering in a communication device. The method may comprise limiting a size of a codebook used for beam steering of antennas to a subset of steering angles over which the antennas are to be steered. The method may further comprise determining a particular steering angle, outside the subset of steering angles, to which to steer the antennas. The method may further comprise determining a limited steering angle within the subset of steering angles corresponding to the particular steering angle. The method may further comprise determining a shift value to shift the limited steering angle to the particular steering angle. The method may further comprise steering the antennas by applying the limited steering angle and the shift value. In example 855, the subject matter of example 854 optionally includes that steering the antennas comprises applying a limited steering angle value to a plurality of primary phase shifters to steer the antennas to the limited steering angle. Steering the antennas may further comprise applying the shift value to a plurality of secondary phase shifters to shift the limited steering angle to the particular steering angle. Each secondary phase shifter may be connected with a set of the primary phase shifters. In example 856, the subject matter of example 855 optionally includes that steering the antennas further comprises applying a unitary multiplier that indicates whether the particular steering angle is set directly by the limited steering angle and shift value or whether the particular steering angle is set by a reflection of the limited steering angle and shift value around shift value about 180º. In example 857, the subject matter of example 856 optionally includes that the codebook is limited to steering angles between arccos(1/2^(b_p ) )°<ϕ≤90°, where bp is a number of bits of each primary phase shifter. In example 858, the subject matter of example 857 optionally includes that primary phase shifter values are limited to between [0,0,0,…,0] and [0,1,2,…,L-1] π/2^(b_p ) , where L is a number of primary phase shifters. In example 859, the subject matter of any one or more of examples 854-858 optionally include that the codebook is limited to steering angles between arccos(1/2^(b_p-1) )°<ϕ≤90°, where bp is a number of bits of each primary phase shifter. Example 860 is an apparatus of a communication device. The apparatus may comprise means for limiting a size of a codebook used for beam steering of antennas to a subset of steering angles over which the antennas are to be steered. The apparatus may further comprise means for determining a particular steering angle, outside the subset of steering angles, to which to steer the antennas. The apparatus may further comprise means for determining a limited steering angle within the subset of steering angles corresponding to the particular steering angle. The apparatus may further comprise means for determining a shift value to shift the limited steering angle to the particular steering angle. The apparatus may further comprise means for steering the antennas by applying the limited steering angle and the shift value. In example 861, the subject matter of example 860 optionally includes that the apparatus further comprises means for applying a limited steering angle value to a plurality of primary phase shifters to steer the antennas to the limited steering angle. The apparatus may further comprise means for applying the shift value to a plurality of secondary phase shifters to shift the limited steering angle to the particular steering angle. Each secondary phase shifter may be connected with a set of the primary phase shifters. In example 862, the subject matter of example 861 optionally includes wherein the apparatus further comprises means for applying a unitary multiplier that indicates whether the particular steering angle is set directly by the limited steering angle and shift value or whether the particular steering angle is set by a reflection of the limited steering angle and shift value around shift value about 180º. In example 863, the subject matter of example 862 optionally includes that the codebook is limited to steering angles between arccos(1/2^(b_p ) )°<ϕ≤90°, where bp is a number of bits of each primary phase shifter. In example 864, the subject matter of example 863 optionally includes that primary phase shifter values are limited to between [0,0,0,…,0] and [0,1,2,…,L-1] π/2^(b_p ) , where L is a number of primary phase shifters. In example 865, the subject matter of any one or more of examples 860-864 optionally include that the codebook is limited to steering angles between arccos(1/2^(b_p-1) )°<ϕ≤90°, where bp is a number of bits of each primary phase shifter. In example 866, the subject matter of any one or more of examples 861-865 optionally include that the secondary phase shifters are radio frequency or baseband phase shifters and the primary phase shifters are intermediate frequency or digital phase shifters. In example 867, the subject matter of any one or more of examples 861-866 optionally include that the primary and secondary phase shifters are low bit phase shifters. Example 868 is a computer-readable storage medium that stores instructions for execution by one or more processors of a communication device. The instructions may be configured to instruct the one or more processors to determine a particular steering angle, outside a subset of steering angles, to which to steer antennas. The instructions may be further configured to instruct the one or more processors to determine a limited steering angle within the subset of steering angles corresponding to the particular steering angle. The instructions may be further configured to instruct the one or more processors to determine a shift value to shift the limited steering angle to the particular steering angle. The instructions may be further configured to instruct the one or more processors to steer the antennas by applying the limited steering angle and the shift value. In example 869, the subject matter of example 868 optionally includes that the instructions further instruct the one or more processors to apply a limited steering angle value to a plurality of primary phase shifters to steer the antennas to the limited steering angle. The instructions may be further configured to instruct the one or more processors to apply the shift value to a plurality of secondary phase shifters to shift the limited steering angle to the particular steering angle. Each secondary phase shifter connected with a set of the primary phase shifters. In example 870, the subject matter of example 869 optionally includes that the instructions further instruct the one or more processors to apply a unitary multiplier that indicates whether the particular steering angle is set directly by the limited steering angle and shift value or whether the particular steering angle is set by a reflection of the limited steering angle and shift value around shift value about 180º. In example 871, the subject matter of example 870 optionally includes that the instructions further instruct the one or more processors to limit a codebook that contains values to steer the antennas to steering angles between arccos(1/2^(b_p ) )°<ϕ≤90°, where bp is a number of bits of each primary phase shifter. In example 872, the subject matter of example 871 optionally includes that primary phase shifter values are limited to between [0,0,0,…,0] and [0,1,2,…,L-1] π/2^(b_p ) , where L is a number of primary phase shifters. In example 873, the subject matter of any one or more of examples 868-872 optionally include wherein the instructions further instruct the one or more processors to: limit a codebook that contains values to steer the antennas to steering angles between arccos(1/2^(b_p-1) )°<ϕ≤90°, where bp is a number of bits of each primary phase shifter. Example 874 is an apparatus of a charge pump. The apparatus may comprise a plurality of switches controlled by a plurality of different control signals and an output capacitor to which the switches are connected. A voltage on the output capacitor may be controlled by leakage capacitances and subthreshold injection of the switches such that an output voltage of the charge pump is free from use of a current reference or charge accumulation device. In example 875, the subject matter of example 874 optionally includes that the switches comprise a first switch group configured to step up the voltage on the output capacitor by a predetermined amount and a second switch group configured to step down the voltage on the output capacitor by the predetermined amount. In example 876, the subject matter of example 875 optionally includes that each of the first and second switch groups comprises a dynamic switch connected to a different rail voltage and a subthreshold switch connected between the dynamic switch and the output capacitor. In example 877, the subject matter of example 876 optionally includes that the leakage capacitances of the dynamic switch control subthreshold injection of the subthreshold switch. In example 878, the subject matter of any one or more of examples 876-877 optionally include timing circuitry connected with the dynamic switch of each of the first and second switch groups. The timing circuitry may be configured to provide a first and second control signal of the plurality of different control signals respectively to the first and second switch groups. The first and second control signal may have a pulse width defined by a set of preset bits of the control signals. In example 879, the subject matter of example 878 optionally includes that each preset bit of the set of preset bits controls a different subthreshold switch. In example 880, the subject matter of any one or more of examples 878-879 optionally include that the output capacitor comprises an internal capacitor in parallel with a set of series-connected capacitor-switch combinations. Each switch of the set of series-connected capacitor-switch combinations may be controlled by a different preset bit of the set of preset bits. In example 881, the subject matter of any one or more of examples 876-880 optionally include that charge is injected through a gate-drain capacitance of each dynamic switch. In example 882, the subject matter of any one or more of examples 874-881 optionally include control logic connected with a pair of the switches and configured to trigger a voltage change of the output capacitor. Example 883 is an apparatus of a charge pump. The apparatus may comprise a first and second dynamic switch configured to be controlled by an UP and DOWN control signal, respectively. The first and second dynamic switch may be connected to different rail voltages. The apparatus may further comprise a first and second series of switches. The first and second series of switches may be respectively connected to the first and second dynamic switch. Each switch of the first and second series of switches may be configured to be controlled by a different bit of a plurality of bits. The apparatus may further comprise an output capacitor to which the first and second series of switches are connected and configured to provide an output voltage of the charge pump. In example 884, the subject matter of example 883 optionally includes that leakage capacitances of the first and second dynamic switch control subthreshold injection of the series of switches. In example 885, the subject matter of any one or more of examples 883-884 optionally include that the series of switches comprises between 1 and 5 switches. In example 886, the subject matter of any one or more of examples 883-885 optionally include first and second timing circuitry respectively connected with the first and second dynamic switch. The first and second timing circuitry may be configured to control a pulse width of the UP and DOWN control signal, respectively, and thereby control a voltage step of the output voltage. In example 887, the subject matter of example 886 optionally includes that each of the first and second timing circuitry comprises an AND gate to which the UP or DOWN control signal and a delayed inverted copy of the UP or DOWN control signal are provided as inputs. The delayed inverted copy of the UP or DOWN control signal may be formed by the UP or DOWN control signal being delayed by a delay line connected to an inverter that is connected to the AND gate. In example 888, the subject matter of example 887 optionally includes that the pulse width is defined by a set of preset bits supplied to the delay line. In example 889, the subject matter of example 888 optionally includes that each preset bit of the set of preset bits controls a different switch of the first and second series of switches. In example 890, the subject matter of any one or more of examples 888-889 optionally include that the output capacitor comprises an internal capacitor in parallel with a set of series-connected capacitor-switch combinations. Each switch of the set of series-connected capacitor-switch combinations controlled by a different preset bit of the set of preset bits. Example 891 is a method of injecting charge in a charge pump. The method may comprise injecting charge across a gate-drain capacitance of a dynamic switch during a charge injection phase. The method may further comprise after injection of the charge, transferring the charge across a subthreshold switch to an output capacitance of the charge pump using subthreshold drain current during a charge transfer phase. The method may further comprise after transfer of the charge, terminating the charge transfer and current flow in the output capacitance to stop a voltage change of an output voltage during a shutdown phase. In example 892, the subject matter of example 891 optionally includes that the charge injection occurs across a gate-drain capacitance of the dynamic switch on a positive edge of a control signal supplied to the dynamic switch. The dynamic switch may be configured to turn off at the positive edge. In example 893, the subject matter of any one or more of examples 891-892 optionally include that the termination occurs on a negative edge of the control signal supplied to the dynamic switch. The dynamic switch may be configured to turn on at the negative edge. In example 894, the subject matter of example 893 optionally includes that during the termination phase, a voltage at a net between the dynamic switch and the subthreshold switch returns to a rail voltage to which the dynamic switch is connected. In example 895, the subject matter of any one or more of examples 891-894 optionally include controlling a pulse width of a control signal during the charge injection phase, and consequently controlling the voltage change. In example 896, the subject matter of example 895 optionally includes that controlling the pulse width of the control signal comprises supplying the control signal and a delayed inverted copy of the control signal to an AND gate, and a set of preset bits to control an amount of delay of the delayed inverted copy of the control signal. In example 897, the subject matter of example 896 optionally includes that during the charge transfer phase, the charge is transferred to the output capacitance across a number of subthreshold switches equal to a number of preset bit of the set of preset bits, each preset bit controlling a different subthreshold switch. In example 898, the subject matter of any one or more of examples 896-897 optionally include controlling incorporation of a number of parallel internal capacitors to form the output capacitor. The number of parallel internal capacitors may be equal to a number of preset bit of the set of preset bits. Each internal capacitor may be incorporated by a different preset bit. Example 899 is an apparatus of a charge pump. The apparatus may comprise means for injecting charge across a gate-drain capacitance of a dynamic switch. The apparatus may further comprise means for transferring the charge across a subthreshold switch to an output capacitance of the charge pump using subthreshold drain current after injection of the charge. The apparatus may further comprise means for terminating the charge transfer and current flow in the output capacitance to stop a voltage change of an output voltage after transfer of the charge. In example 900, the subject matter of example 899 optionally includes means for controlling a pulse width of a control signal during the charge injection phase, and consequently controlling the voltage change. In example 901, the subject matter of any one or more of examples 899-900 optionally include means for controlling the pulse width of the control signal comprises means for supplying the control signal and a delayed inverted copy of the control signal to an AND gate, and a set of preset bits to control an amount of delay of the delayed inverted copy of the control signal. In example 902, the subject matter of example 901 optionally includes means for transferring the charge to the output capacitance across a number of subthreshold switches equal to a number of preset bit of the set of preset bits. Each preset bit may control a different subthreshold switch. In example 903, the subject matter of any one or more of examples 901-902 optionally include means for controlling incorporation of a number of parallel internal capacitors to form the output capacitor. The number of parallel internal capacitors may be equal to a number of preset bit of the set of preset bits. Each internal capacitor may be incorporated by a different preset bit. Example 904 is a computer-readable storage medium that stores instructions for execution by one or more processors of a communication device. The instructions may be configured to instruct the one or more processors to control a first and second dynamic switch by an UP and DOWN control signal, respectively. The first and second dynamic switch may be connected to different rail voltages. The instructions may be further configured to instruct the one or more processors to control each switch of a first and second series of switches by a different bit of a plurality of bits. The first and second series of switches may be respectively connected to the first and second dynamic switch. The instructions may be further configured to instruct the one or more processors to adjust an output voltage of an output capacitor of the charge pump to which the first and second series of switches are connected. In example 905, the subject matter of example 904 optionally includes wherein the instructions configured to instruct the one or more processors to control a pulse width of the UP and DOWN control signal via first and second timing circuitry respectively connected with the first and second dynamic switch. In example 906, the subject matter of example 905 optionally includes that each of the first and second timing circuitry comprises an AND gate to which the UP or DOWN control signal and a delayed inverted copy of the UP or DOWN control signal are provided as inputs. The instructions may be further configured to instruct the one or more processors to control a delay of a delay line connected to an inverter that is connected to the AND gate. The UP or DOWN control signal may be delayed by the delay line to form the delayed inverted copy of the UP or DOWN control signal. In example 907, the subject matter of example 906 optionally includes that the pulse width is defined by a set of preset bits supplied to the delay line. In example 908, the subject matter of example 907 optionally includes wherein the instructions configured to instruct the one or more processors to control a different switch of the first and second series of switches using a different preset bit. In example 909, the subject matter of any one or more of examples 907-908 optionally include that the output capacitor comprises an internal capacitor in parallel with a set of series-connected capacitor-switch combinations. The instructions may be further configured to instruct the one or more processors to control each switch of the set of series-connected capacitor-switch combinations by a different preset bit. Example 910 is an apparatus of a communication device. The apparatus may comprise receiver circuitry. The receiver circuitry may comprise a plurality of first quantizers configured to receive beamformed signals. The receiver circuitry may further comprise a feedforward loop configured to provide analog compensation signals to the beamformed signals, prior to the beamformed signals being supplied to the quantizers, to form compensated beamformed signals. The beamformed signals may comprise a signal from a transmitter and an interferer signal. The analog compensation signals may be configured to compensate for the interferer signal. In example 911, the subject matter of example 910 optionally includes that the feedforward loop comprises a plurality of second quantizers configured to convert the beamformed signals to coarsely quantized signals. The feedforward loop may further comprise a plurality of digital to analog converters (DACs) configured to convert to the analog compensation signals. In example 912, the subject matter of example 911 optionally includes that a resolution of the second quantizers is less than resolution of the first quantizers. In example 913, the subject matter of any one or more of examples 911-912 optionally include that the feedforward loop further comprises a digital filter disposed between the second quantizers and the DACs. The digital filter may be configured to provide cross-correlated interference compensation for the coarsely quantized signals and produce digital versions of the analog compensation signals. In example 914, the subject matter of example 913 optionally includes a plurality of combiners configured to combine the digital versions of the analog compensation signals and digital versions of the compensated beamformed signals to provide signal quality used to adjust the receiver circuitry. In example 915, the subject matter of any one or more of examples 913-914 optionally include that the digital filter is configured to estimate interference from each direction from (i_k ) ̂[n]=a_r^H (θ_k )y[n], where y[n] is a coarsely quantized signal at a particular second quantizer, and a_r (θ_k )is an estimation vector of interference from direction θ_k, and subsequently determine an interference vector as: i[n]=(i_1 ) ̂[n] a_r (θ_1 )+⋯+(i_I ) ̂[n] a_r (θ_I ). In example 916, the subject matter of any one or more of examples 911-915 optionally include that the feedforward loop further comprise: a plurality of combiners configured to add dithering noise to the beamformed signals prior to the beamformed signals being provided to the second quantizers. The dithering noise may be dependent on an estimate of the interference. In example 917, the subject matter of any one or more of examples 911-916 optionally include a plurality of analog delay lines configured to add sufficient delay to the beamformed signals to permit the beamformed signals to be combined with the analog compensation signals supplied through the feedforward circuitry. In example 918, the subject matter of any one or more of examples 911-917 optionally include a plurality of combiners configured to add dithering noise to the compensated beamformed signals. The dithering noise may be dependent on a measure of receiver performance. In example 919, the subject matter of any one or more of examples 911-918 optionally include a plurality of first combiners configured to add first dithering noise to the beamformed signals prior to the beamformed signals being provided to the second quantizers. A plurality of second combiners may be configured to add second dithering noise to the compensated beamformed signals. The first and second dithering noise may be dependent on different qualities of the beamformed signal. In example 920, the subject matter of any one or more of examples 910-919 optionally include a plurality of antennas configured to provide the beamformed signals. Example 921 is a method of compensating for interferers in a receiver. The method may comprise receiving beamformed signals from a plurality of antennas. Each beamformed signal may comprise a signal from a transmitter and an interferer signal. The method may further comprise forming compensated signals by feedforward compensating the beamformed signals for the interferer signals, prior to quantizing compensated signals for output. The compensated signals may be dependent on the beamformed signals. The method may further comprise quantizing the compensated signals to form quantized output signals. The method may further comprise supplying the quantized output signals to a baseband processor for processing. In example 921a, the subject matter of example 921 optionally includes quantizing the beamformed signals along a feedforward path to form quantized feedforward signals. The method may further comprise compensating for the interferer signals in the quantized feedforward signals to provide digital compensation signals. The method may further comprise converting the digital compensation signals to analog compensation signals. The method may further comprise combining the analog compensation signals with the beamformed signals to form the compensated signals. In example 922, the subject matter of example 921a optionally includes that resolution of quantization of the beamformed signals is lower than resolution of quantization of the compensated signals. In example 923, the subject matter of example 922 optionally includes adding first dithering noise to the beamformed signals prior to the quantizing the beamformed signals. The method may further comprise adding second dithering noise to the compensated signals. In example 924, the subject matter of example 923 optionally includes combining the digital compensation signals and digital versions of the compensated signals to provide a signal quality. The method may further comprise controlling, based on the signal quality, at least one of: quantization of the beamformed signals, quantization of the compensated signals, the first dithering noise or the second dithering noise. In example 925, the subject matter of any one or more of examples 921-924 (including 921a) optionally include that compensating for the interferer signals comprises estimating interference from each direction from: (i_k ) ̂[n]=a_r^H (θ_k )y[n], where y[n] is a coarsely quantized signal at a particular second quantizer, and a_r (θ_k )is an estimation vector of interference from direction θ_k, and subsequently determine an interference vector as: i[n]=(i_1 ) ̂[n] a_r (θ_1 )+⋯+(i_I ) ̂[n] a_r (θ_I ). In example 926, the subject matter of any one or more of examples 921-926 (including 921a) optionally include delaying the beamformed signals sufficiently to permit the beamformed signals to be combined with the analog compensation signals. Example 927 is an apparatus of a receiver. The apparatus may comprise means for receiving beamformed signals from a plurality of antennas. Each beamformed signal may comprise a signal from a transmitter and an interferer signal. The apparatus may further comprise means for forming compensated signals by feedforward compensating the beamformed signals for the interferer signals, prior to quantizing compensated signals for output. The compensated signals may be dependent on the beamformed signals. The apparatus may further comprise means for quantizing the compensated signals to form quantized output signals. In example 928, the subject matter of example 927 optionally includes means for quantizing the beamformed signals along a feedforward path to form quantized feedforward signals; means for compensating for the interferer signals in the quantized feedforward signals to provide digital compensation signals. The apparatus may further comprise means for converting the digital compensation signals to analog compensation signals. The apparatus may further comprise means for combining the analog compensation signals with the beamformed signals to form the compensated signals. In example 929, the subject matter of example 928 optionally includes that resolution of quantization of the beamformed signals is lower than resolution of quantization of the compensated signals. In example 930, the subject matter of example 929 optionally includes means for adding first dithering noise to the beamformed signals prior to the quantizing the beamformed signals; and means for adding second dithering noise to the compensated signals. In example 931, the subject matter of example 930 optionally includes means for combining the digital compensation signals and digital versions of the compensated signals to provide a signal quality. The apparatus may further comprise means for controlling, based on the signal quality, at least one of: quantization of the beamformed signals, quantization of the compensated signals, the first dithering noise or the second dithering noise. In example 932, the subject matter of any one or more of examples 928-931 optionally include means for estimating interference from each direction from: (i_k ) ̂[n]=a_r^H (θ_k )y[n], where y[n] is a coarsely quantized signal at a particular second quantizer, and a_r (θ_k )is an estimation vector of interference from direction θ_k, and subsequently determine an interference vector as: i[n]=(i_1 ) ̂[n] a_r (θ_1 )+⋯+(i_I ) ̂[n] a_r (θ_I ). In example 933, the subject matter of any one or more of examples 931-932 optionally include means for delaying the beamformed signals sufficiently to permit the beamformed signals to be combined with the analog compensation signals. Example 934 is a computer-readable storage medium that stores instructions for execution by one or more processors of a communication device. The instructions may be configured to instruct the one or more processors to receive beamformed signals from a plurality of antennas. Each beamformed signal may comprise a signal from a transmitter and an interferer signal. The instructions may be further configured to instruct the one or more processors to form compensated signals by feedforward compensating the beamformed signals for the interferer signals, prior to quantizing compensated signals for output. The compensated signals may be dependent on the beamformed signals. The instructions may be further configured to instruct the one or more processors to quantize the compensated signals to form quantized output signals. In example 935, the subject matter of example 934 optionally includes that the instructions further configure the one or more processors to quantize the beamformed signals along a feedforward path to form quantized feedforward signals. The instructions may be further configured to instruct the one or more processors to compensate for interference in the quantized feedforward signals to provide digital compensation signals. The instructions may be further configured to instruct the one or more processors to convert the digital compensation signals to analog compensation signals. The instructions may be further configured to instruct the one or more processors to combine the analog compensation signals with the beamformed signals to form the compensated signals. In example 936, the subject matter of example 935 optionally includes that resolution of quantization of the beamformed signals is lower than resolution of quantization of the compensated signals. In example 937, the subject matter of example 936 optionally includes that the instructions further configure the one or more processors to add first dithering noise to the beamformed signals prior to the quantizing the beamformed signals. The instructions may be further configured to instruct the one or more processors to add second dithering noise to the compensated signals. In example 938, the subject matter of example 937 optionally includes that the instructions further configure the one or more processors to combine the digital compensation signals and digital versions of the compensated signals to provide a signal quality. The instructions may be further configured to instruct the one or more processors to control, based on the signal quality, at least one of: quantization of the beamformed signals, quantization of the compensated signals, the first dithering noise or the second dithering noise. In example 939, the subject matter of any one or more of examples 934-938 optionally include that the instructions further configure the one or more processors to: estimate interference from each direction from: (i_k ) ̂[n]=a_r^H (θ_k )y[n], where y[n] is a coarsely quantized signal at a particular second quantizer, and a_r (θ_k )is an estimation vector of interference from direction θ_k, and subsequently determine an interference vector as: i[n]=(i_1 ) ̂[n] a_r (θ_1 )+⋯+(i_I ) ̂[n] a_r (θ_I ). In example 940, the subject matter of any one or more of examples 934-939 optionally include that the instructions further configure the one or more processors to delay the beamformed signals sufficiently to permit the beamformed signals to be combined with the analog compensation signals. Example 941 is an apparatus of a communication device. The apparatus may comprise a receiver that comprises compensation circuitry, a quantizer; and a baseband processor. The compensation circuitry may be configured to compensate, in an analog domain of the receiver, for interference in a radio frequency (RF) signal received at each of a plurality of beamforming antennas and produce an analog compensated signal. The quantizer may be configured to transform, to a quantized output, an analog input signal that is dependent on the compensation circuitry. The baseband processor may be configured to receive a baseband input signal that is dependent on the quantized output, apply an inversion of the compensation to the baseband input signal to reconstitute a digital version of the RF signal, and perform signal processing on the digital version of the RF signal. In example 942, the subject matter of example 941 optionally includes that the compensation circuitry comprises a feedback loop configured to provide the quantized output from the quantizer to the analog domain. The feedback loop may comprise a filter configured to filter the quantized output dependent on a direction of the interference and produce a filtered signal. The feedback loop may further comprise a digital to analog converter (DAC) configured to convert the filtered signal to an analog signal. The feedback loop may further comprise a combiner configured to combine the analog signal with a signal from the antenna used to generate the analog input signal to the quantizer and form a combined signal. In example 943, the subject matter of example 942 optionally includes that the quantizer and the digital to analog converter have different resolutions. In example 944, the subject matter of example 943 optionally includes that at least one of the resolutions is dependent on at least one of a desired bit error rate (BER) or filter characteristic. In example 945, the subject matter of any one or more of examples 942-944 optionally include a low pass filter (LPF) disposed between the combiner and the quantizer and configured to shape quantization noise in the combined signal to out-of-band. In example 946, the subject matter of example 945 optionally includes a gain disposed between the LPF and the quantizer and configured to adjust a gain input to a dynamic range of the quantizer and provide the analog input signal. In example 947, the subject matter of any one or more of examples 942-946 optionally include a low pass filter (LPF) disposed between the quantizer and the baseband processor and configured to eliminate harmonics introduced by the quantizer. In example 948, the subject matter of any one or more of examples 942-947 optionally include a gain disposed between the DAC and the combiner and configured to adjust the analog signal one of dependent on a channel quality or set to a fixed gain. In example 949, the subject matter of any one or more of examples 942-948 optionally include that the quantizer is configured to oversample the analog input signal. The receiver may further comprise a decimator disposed between the quantizer and the baseband processor and configured to down sample a decimator input signal to a Nyquist rate. In example 950, the subject matter of any one or more of examples 942-949 optionally include that coefficients of the filter are dependent on directionality of the interference. In example 951, the subject matter of example 950 optionally includes that the filter is defined as W∈C^((K-1)N_r×N_r ), where K is an oversampling rate and Nr is a number of the antennas. In example 952, the subject matter of example 951 optionally includes that a_r (θ_i )=〖1/√(N_r ) [1,e^(j 2π/λ d cos⁡〖θ_i 〗 ),e^(j 2π/λ d2 cos⁡〖θ_i 〗 ),…,e^(j 2π/λ d (N_r-1)cos⁡〖θ_i 〗 ) ]〗^T, W=[█(F_1@F_2@⋮)], L=[■(1&0@1&1)], and α=[■(2@3)] wherein d is an inter-antenna distance, and a filter coefficient matrix F∈C^(2N_r×N_r ) is: 〖F=[█(F_1@F_2 )]=[■(L⊗a_r^T (θ_1 )@⋮@L⊗a_r^T (θ_I ) )]〗^+ [■(α⊗a_r^T (θ_1 )@⋮@α⊗a_r^T (θ_I ) )]wherein [∙]^+ is a pseudoinverse operator, I is a total number of interference directions, and ⊗ represents a Kronecker product. In example 953, the subject matter of any one or more of examples 941-952 optionally include an antenna configured to transmit a signal dependent on the output oscillator signal. Example 954 is a method of using a reduced quantizer dynamic range in a receiver. The method may comprise receiving a plurality of beamformed signals from a plurality of beamforming antennas. The method may further comprise for each beamformed signal: reducing the dynamic range of a quantizer to which the beamformed signal is supplied by compensating the beamformed signal for interference from an interferer prior to the beamformed signal being provided to the quantizer and providing a compensated signal to the quantizer; quantizing the compensated signal; digitally inverting compensation applied to the beamformed signal to regenerate a digital version of the beamformed signal, and signal processing the digital version of the beamformed signal. In example 955, the subject matter of example 954 optionally includes filtering the quantized output using a filter whose coefficients are dependent on a direction of the interferer to produce a filtered signal. The method may further comprise converting the filtered signal to an analog signal. The method may further comprise combining the analog signal with the beamformed signal to generate the compensated signal. In example 956, the subject matter of example 955 optionally includes at least one of: using different resolutions in quantizing the compensated signal and converting the filtered signal, or at least one of the different resolutions is dependent on at least one of a desired bit error rate (BER) or a filter characteristic. In example 957, the subject matter of any one or more of examples 953-955 optionally include shaping quantization noise in the compensated signal to out-of-band using a low pass filter (LPF) to form a LPF signal. In example 958, the subject matter of example 957 optionally includes adjusting a gain of the LPF signal prior to quantizing the LPF signal to reduce the dynamic range of the quantizer. In example 959, the subject matter of any one or more of examples 954-958 optionally include that the compensated signal is oversampled during the quantizing. The method may further comprise eliminating harmonics introduced by the quantizer using a low pass filter (LPF) to generate a LPF signal and down sampling the LPF signal to a Nyquist rate. In example 960, the subject matter of any one or more of examples 953-959 optionally include that the filter is defined as W∈C^((K-1)N_r×N_r ), where K is an oversampling rate and Nr is a number of the antennas, a_r (θ_i )=〖1/√(N_r ) [1,e^(j 2π/λ d cos⁡〖θ_i 〗 ),e^(j 2π/λ d2 cos⁡〖θ_i 〗 ),…,e^(j 2π/λ d (N_r-1)cos⁡〖θ_i 〗 ) ]〗^T, W=[█(F_1@F_2@⋮)], L=[■(1&0@1&1)], and α=[■(2@3)] wherein d is an inter-antenna distance, and a filter coefficient matrix F∈C^(2N_r×N_r ) is: 〖F=[█(F_1@F_2 )]=[■(L⊗a_r^T (θ_1 )@⋮@L⊗a_r^T (θ_I ) )]〗^+ [■(α⊗a_r^T (θ_1 )@⋮@α⊗a_r^T (θ_I ) )]wherein [∙]^+ is a pseudoinverse operator, I is a total number of interference directions, and ⊗ represents a Kronecker product. Example 961 is an apparatus of a digital polar transmitter. The apparatus may comprise means for receiving a plurality of beamformed signals from a plurality of beamforming antennas. The apparatus may further comprise for each beamformed signal: means for reducing the dynamic range of a quantizer to which the beamformed signal is supplied by compensating the beamformed signal for interference from an interferer prior to the beamformed signal being provided to the quantizer and providing a compensated signal to the quantizer; means for quantizing the compensated signal; means for digitally inverting compensation applied to the beamformed signal to regenerate a digital version of the beamformed signal, and means for signal processing the digital version of the beamformed signal. In example 962, the subject matter of example 961 optionally includes means for filtering the quantized output using a filter whose coefficients are dependent on a direction of the interferer to produce a filtered signal. The apparatus may further comprise means for converting the filtered signal to an analog signal. The apparatus may further comprise means for combining the analog signal with the beamformed signal to generate the compensated signal. In example 963, the subject matter of example 962 optionally includes at least one of: different resolutions are used in quantizing the compensated signal and convert the filtered signal, or at least one of the different resolutions is dependent on at least one of a desired bit error rate (BER) or a filter characteristic. In example 964, the subject matter of any one or more of examples 961-963 optionally include means for shaping quantization noise in the compensated signal to out-of-band using a low pass filter (LPF) to form a LPF signal. In example 965, the subject matter of example 964 optionally includes means for adjusting a gain of the LPF signal prior to quantizing the LPF signal to reduce the dynamic range of the quantizer. In example 966, the subject matter of any one or more of examples 961-965 optionally include that the compensated signal is oversampled during the quantizing. The apparatus may further comprise means for eliminating harmonics introduced by the quantizer using a low pass filter (LPF) to generate a LPF signal. The apparatus may further comprise means for down sampling the LPF signal to a Nyquist rate. In example 967, the subject matter of any one or more of examples 961-966 optionally include that the filter is defined as W∈C^((K-1)N_r×N_r ), where K is an oversampling rate and Nr is a number of the antennas, a_r (θ_i )=〖1/√(N_r ) [1,e^(j 2π/λ d cos⁡〖θ_i 〗 ),e^(j 2π/λ d2 cos⁡〖θ_i 〗 ),…,e^(j 2π/λ d (N_r-1)cos⁡〖θ_i 〗 ) ]〗^T, W=[█(F_1@F_2@⋮)], L=[■(1&0@1&1)], and α=[■(2@3)] wherein d is an inter-antenna distance, and a filter coefficient matrix F∈C^(2N_r×N_r ) is: 〖F=[█(F_1@F_2 )]=[■(L⊗a_r^T (θ_1 )@⋮@L⊗a_r^T (θ_I ) )]〗^+ [■(α⊗a_r^T (θ_1 )@⋮@α⊗a_r^T (θ_I ) )]wherein [∙]^+ is a pseudoinverse operator, I is a total number of interference directions, and ⊗ represents a kronecker product. Example 968 is a computer-readable storage medium that stores instructions for execution by one or more processors of a communication device to configure the communication device to receive a plurality of beamformed signals from a plurality of beamforming antennas. The instructions may further configure the communication device to, for each beamformed signal: reduce the dynamic range of a quantizer to which the beamformed signal is supplied by compensating the beamformed signal for interference from an interferer prior to the beamformed signal being provided to the quantizer and providinga compensated signal to the quantizer; independently adjust an amplitude of each of the compensation and the compensated signal; quantize the compensated signal; digitally invert compensation applied to the beamformed signal to regenerate a digital version of the beamformed signal, and signal process the digital version of the beamformed signal. In example 969, the subject matter of example 968 optionally includes that the one or more processors further configure the communication device to filter the quantized output using a filter whose coefficients are dependent on a direction of the interferer to produce a filtered signal. The instructions may further configure the communication device to convert the filtered signal to an analog signal. The instructions may further configure the communication device to combine the analog signal with the beamformed signal to generate the compensated signal. In example 970, the subject matter of example 969 optionally includes at least one of: different resolutions are used in quantizing the compensated signal and convert the filtered signal, or at least one of the different resolutions is dependent on at least one of a desired bit error rate (BER) or a filter characteristic. In example 971, the subject matter of any one or more of examples 968-970 optionally include that the one or more processors further configure the communication device to: shape quantization noise in the compensated signal to out-of-band using a low pass filter (LPF) to form a LPF signal. In example 972, the subject matter of any one or more of examples 968-971 optionally include that the compensated signal is oversampled during the quantizing. The instructions may further configure the communication device to eliminate harmonics introduced by the quantizer using a low pass filter (LPF) to generate a LPF signal and down sample the LPF signal to a Nyquist rate. In example 973, the subject matter of any one or more of examples 968-972 optionally include that the filter is defined as W∈C^((K-1)N_r×N_r ), where K is an oversampling rate and Nr is a number of the antennas, a_r (θ_i )=〖1/√(N_r ) [1,e^(j 2π/λ d cos⁡〖θ_i 〗 ),e^(j 2π/λ d2 cos⁡〖θ_i 〗 ),…,e^(j 2π/λ d (N_r-1)cos⁡〖θ_i 〗 ) ]〗^T, W=[█(F_1@F_2@⋮)], L=[■(1&0@1&1)], and α=[■(2@3)] wherein d is an inter-antenna distance, and a filter coefficient matrix F∈C^(2N_r×N_r ) is: 〖F=[█(F_1@F_2 )]=[■(L⊗a_r^T (θ_1 )@⋮@L⊗a_r^T (θ_I ) )]〗^+ [■(α⊗a_r^T (θ_1 )@⋮@α⊗a_r^T (θ_I ) )]wherein [∙]^+ is a pseudoinverse operator, I is a total number of interference directions, and ⊗ represents a kronecker product. Example 974 is an apparatus of a communication device. The apparatus may comprise an analog to digital converter system (ADCS) comprising an adjustable ADC configuration. The ADC configuration may comprise a plurality of core ADCs that are adjustable between parallel operation in an averaging mode and serial operation in a time-interleaved mode. The ADCS may be configured in the averaging mode for higher resolution, lower bandwidth operation of the communication device and configured in the time-interleaved mode for lower resolution, higher speed operation of the communication device. In example 975, the subject matter of example 974 optionally includes that the ADCS further comprises a plurality of timing units. Each timing unit may be connected with a different core ADC of the plurality of core ADCs. Each timing unit may be configured to provide a system clock signal to an associated core ADC based on a master clock signal supplied to the timing unit. The system clock signal may be dependent on which of the averaging or time-interleaved mode the ADCS is in. In example 976, the subject matter of example 975 optionally includes that each timing unit and core ADC is configured to receive a mode signal from a controller that indicates which of the averaging or time-interleaved mode the ADCS is in and a set of configuration bits to tune the timing unit and core ADC to a desired setup in at least one of the averaging or time-interleaved mode. In example 977, the subject matter of example 976 optionally includes that the mode signal comprises a single bit that indicates which of the averaging or time-interleaved mode the ADCS is in and at least one additional bit that indicate how many of the core ADCs to use. In example 978, the subject matter of example 977 optionally includes that the at least one additional bit specifies which of the core ADCs to use. In example 979, the subject matter of any one or more of examples 976-978 optionally include that the mode signal consists of a single bit that indicates which of the averaging or time-interleaved mode the ADCS is in. In example 980, the subject matter of any one or more of examples 974-979 optionally include that the core ADCs are variable bit ADCs whose resolution changes dependent on which of the averaging or time-interleaved mode the ADCS is in. In example 981, the subject matter of any one or more of examples 974-980 optionally include that each core ADC comprises a sampling circuit to oversample and decimate an input signal to be quantized. In example 982, the subject matter of any one or more of examples 974-981 optionally include that the ADCS further comprises a processing circuit configured to receive quantized signals from the core ADCs and process the quantized signals differently dependent on which of the averaging or time-interleaved mode the ADCS is in. In example 983, the subject matter of example 982 optionally includes that the processing circuit is configured to operate as a buffer when the ADCS is in the averaging mode and as an equalizer when the ADCS is in the time-interleaved mode. In example 984, the subject matter of any one or more of examples 974-983 optionally include an antenna comprising antenna elements that provide input signals to the ADCS. Example 985 is a method of providing a flexible analog to digital converter (ADC) architecture. The method may comprise adjusting an ADC configuration between an averaging mode ADC configuration for higher resolution, lower bandwidth operation and a time-interleaved mode ADC configuration for lower resolution, higher speed operation in which the outputs from the core ADCs are averaged. The method may further comprise averaging outputs from core ADCs in the averaging mode ADC configuration to produce an averaged ADC output. The method may further comprise combining outputs from core ADCs in the time-interleaved mode ADC configuration to produce a time-interleaved ADC output. In example 986, the subject matter of example 985 optionally includes providing a system clock signal and a local master clock signal to each core ADC based on a master clock signal supplied to the timing unit. The method may further comprise adjusting the system clock signal dependent on the ADC configuration. In example 987, the subject matter of example 986 optionally includes that the system clock signal is adjusted based on a mode signal that indicates the ADC configuration. The mode signal may comprise a single bit that indicates the ADC configuration and at least one additional bit that indicate how many of the core ADCs to use. In example 988, the subject matter of any one or more of examples 986-987 optionally include that the system clock signal is adjusted based on a mode signal that indicates the ADC configuration. The mode signal may consist of a single bit that indicates the ADC configuration. In example 989, the subject matter of any one or more of examples 986-988 optionally include that the system clock signal is adjusted based on a mode signal that indicates the ADC configuration. The method may further comprise tuning the ADC configuration to a desired setup based on a set of configuration bits. In example 990, the subject matter of any one or more of examples 985-989 optionally include adjusting a resolution of the core ADCs dependent on the ADC configuration. In example 991, the subject matter of any one or more of examples 985-990 optionally include oversampling and decimating an input signal to each of the core ADCs prior to quantizing the input signal to produce a quantized signal. In example 992, the subject matter of any one or more of examples 985-991 optionally include processing the quantized signals differently dependent on the ADC configuration. The processing may comprise buffering the quantized signals from each of the core ADCs in the averaging mode ADC configuration and equalizing the quantized signals from each of the core ADCs in the time-interleaved mode ADC configuration. Example 993 is an apparatus of a communication device. The apparatus may comprise means for adjusting an analog to digital converter (ADC) configuration between an averaging mode ADC configuration for higher resolution, lower bandwidth operation and a time-interleaved mode ADC configuration for lower resolution, higher speed operation in which the outputs from the core ADCs are averaged. The apparatus may further comprise means for averaging outputs from core ADCs in the averaging mode ADC configuration to produce an averaged ADC output. The apparatus may further comprise means for combining outputs from core ADCs in the time-interleaved mode ADC configuration to produce a time-interleaved ADC output. In example 994, the subject matter of example 993 optionally includes means for providing a system clock signal and a local master clock signal to each core ADC based on a master clock signal supplied to the timing unit. The apparatus may further comprise means for adjusting the system clock signal dependent on the ADC configuration. In example 995, the subject matter of example 994 optionally includes that the system clock signal is adjusted based on a mode signal that indicates the ADC configuration. The mode signal may comprise a single bit that indicates the ADC configuration and at least one additional bit that indicate how many of the core ADCs to use. In example 996, the subject matter of any one or more of examples 994-995 optionally include that the system clock signal is adjusted based on a mode signal that indicates the ADC configuration. The mode signal may consist of a single bit that indicates the ADC configuration. In example 997, the subject matter of any one or more of examples 994-996 optionally include that the system clock signal is adjusted based on a mode signal that indicates the ADC configuration. The mode signal may comprise a single bit that indicates which of the averaging or time-interleaved mode the ADCS is in and at least one additional bit that indicate how many of the core ADCs to use. In example 998, the subject matter of any one or more of examples 994-997 optionally include means for adjusting a resolution of the core ADCs dependent on the ADC configuration. In example 999, the subject matter of any one or more of examples 994-998 optionally include means for oversampling and decimating an input signal to each of the core ADCs prior to quantizing the input signal to produce a quantized signal. Example 1000 is a computer-readable storage medium that stores instructions for execution by one or more processors of a communication device. The instructions may be configured to instruct the one or more processors to adjust an analog to digital converter (ADC) configuration of a plurality of core ADCs between an averaging mode and a time-interleaved mode. The averaging mode may be configured for higher resolution, lower bandwidth operation and the time-interleaved mode may be configured for lower resolution, higher speed operation. The instructions may be configured to instruct the one or more processors to process quantized signals from the core ADCs differently dependent on the ADC configuration. The processing may comprise buffering the quantized signals from each of the core ADCs in the averaging mode ADC configuration and equalizing the quantized signals from each of the core ADCs in the time-interleaved mode ADC configuration. In example 1001, the subject matter of example 1000 optionally includes that the instructions further instruct the one or more processors to configure each of a plurality of timing units to provide a system clock signal to a different core ADC based on a master clock signal supplied to the timing unit. The system clock signal may be dependent on the ADC configuration. In example 1002, the subject matter of example 1001 optionally includes that each timing unit and core ADC is configured to receive a mode signal that indicates which of the ADC configuration. The mode signal may comprise mode signal comprises a single bit that indicates the ADC configuration and at least one additional bit that indicate how many of the core ADCs to use. In example 1003, the subject matter of example 1002 optionally includes that the at least one additional bit specifies which of the core ADCs to use. In example 1004, the subject matter of example 1003 optionally includes that each timing unit and core ADC is configured to receive a mode signal that indicates which of the ADC configuration. The mode signal may comprise consist of a single bit that indicates the ADC configuration. In example 1005, the subject matter of any one or more of examples 1000-1004 optionally include that the core ADCs are variable bit ADCs whose resolution changes dependent on which of the averaging or time-interleaved mode the ADCS is in. In example 1006, the subject matter of any one or more of examples 1000-1005 optionally include that each core ADC comprises a sampling circuit to oversample and decimate an input signal to be quantized. Example 1007 is an apparatus of a communication device. The apparatus may comprise receiver circuitry comprising a plurality of analog to digital converters (ADCs) configured to receive beamformed signals. The receiver circuitry may be configured to provide analog compensation to the beamformed signals prior to the beamformed signals being supplied to the ADCs. The beamformed signals may comprise a desired signal and an interferer signal. The compensation may be configured to compensate for the interferer signal and reduce dynamic gains of the ADCs. In example 1008, the subject matter of example 1007 optionally includes that the receiver circuitry further comprises a baseband processor configured to receive digital signals from the ADCs. The baseband processor may be further configured to provide an inverse of the analog compensation prior to a determination of a direction of the desired signal. In example 1009, the subject matter of any one or more of examples 1007-1008 optionally include a radio frequency (RF) front end configured to output the beamformed signals as a plurality of analog outputs. The receiver circuitry may further comprise a combiner for each analog output. The combiner may be configured to combine a weighted copy of each of the analog outputs. In example 1010, the subject matter of example 1009 optionally includes that an analog summation weight matrix that describes weightings of the analog outputs is an invertible matrix, the weightings being fixed. In example 1011, the subject matter of any one or more of examples 1009-1010 optionally include that an analog summation weight matrix that describes weightings of the analog outputs is an invertible matrix. The weightings may be adaptively dependent on conditions of the desired and interferer signal to maximize signal-to-interference-plus-noise (SINR) of the desired signal. In example 1012, the subject matter of example 1011 optionally includes that the analog summation weight matrix comprises a Hadamard matrix. In example 1013, the subject matter of any one or more of examples 1009-1012 optionally include that the receiver circuitry further comprises, for each combiner, a variable gain comprising an input to which an output of the combiner is supplied and an output connected with an input of a corresponding ADC. A gain of the variable gain may be set to normalize a power level of a beamformed signal supplied to the corresponding ADC. In example 1014, the subject matter of any one or more of examples 1009-1013 optionally include that the combiner is implemented with current mode summation. In example 1015, the subject matter of any one or more of examples 1008-1014 optionally include that the baseband processor is further configured to enable a number of the ADCs for use during a particular operation. In example 1016, the subject matter of any one or more of examples 1008-1015 optionally include that the baseband processor is further configured to select a dynamic range of each ADC dependent on a desired array interference rejection and angle resolution. In example 1017, the subject matter of any one or more of examples 1007-1016 optionally include an antenna comprising antenna elements that provide the beamformed signals. Example 1018 is a method of reducing dynamic gain of analog to digital converters (ADCs) in a receiver. The method may comprise receiving beamformed signals from a plurality of antenna elements of an antenna. Each beamformed signal may comprise a desired signal and an interferer signal. The method may further comprise compensating for the interferer signal, prior to providing the beamformed signals to the ADCs, to form compensated signals. Each compensated signal may be provided to a different ADC; quantizing the compensated signals at the ADCs to form quantized signals. The method may further comprise reversing the compensating prior to processing the quantized signals. In example 1019, the subject matter of example 1018 optionally includes that the processing of the quantized signals comprises at least one of determining a direction of at least one of the desired or interfering signal or channel sounding. In example 1020, the subject matter of any one or more of examples 1018-1019 optionally include that the compensating for the interferer signal comprises, for each compensated signal, combining a weighted copy of each of the beamformed signals. In example 1021, the subject matter of example 1020 optionally includes that an analog summation weight matrix that describes weightings of the beamformed signals is an invertible matrix. The weightings may be fixed. In example 1022, the subject matter of any one or more of examples 1020-1021 optionally include that an analog summation weight matrix that describes weightings of the beamformed signals is an invertible matrix. The weightings may be dependent on conditions of the desired and interferer signal to maximize signal-to-interference-plus-noise (SINR) of the desired signal. In example 1023, the subject matter of example 1022 optionally includes that the analog summation weight matrix comprises a Hadamard matrix. In example 1024, the subject matter of any one or more of examples 1018-1023 optionally include adjusting a variable gain of each compensated signal to normalize a power level of a signal supplied to a corresponding ADC of the ADCs. In example 1025, the subject matter of any one or more of examples 1018-1024 optionally include adjusting a number of the ADCs to use during a particular operation. In example 1026, the subject matter of any one or more of examples 1018-1025 optionally include selecting a dynamic range of each ADC dependent on a desired array interference rejection and angle resolution. Example 1027 is an apparatus of a communication device. The apparatus may comprise means for receiving beamformed signals from a plurality of antenna elements of an antenna. Each beamformed signal may comprise a desired signal and an interferer signal. The apparatus may further comprise means for compensating for the interferer signal, prior to providing the beamformed signals to analog-to-digital converters (ADCs), to form compensated signals. Each compensated signal may be provided to a different ADC. The apparatus may further comprise means for quantizing the compensated signals at the ADCs to form quantized signals. The apparatus may further comprise means for reversing the compensating prior to processing the quantized signals. In example 1028, the subject matter of example 1027 optionally includes at least one of means for determining a direction of at least one of the desired or interfering signal or channel sounding during processing of the quantized signals. In example 1029, the subject matter of any one or more of examples 1027-1028 optionally include that the means for compensating for the interferer signal comprises, for each compensated signal, means for combining a weighted copy of each of the beamformed signals. In example 1030, the subject matter of example 1029 optionally includes that an analog summation weight matrix that describes weightings of the beamformed signals is an invertible matrix. The weightings may be fixed. In example 1031, the subject matter of any one or more of examples 1029-1030 optionally include that an analog summation weight matrix that describes weightings of the beamformed signals is an invertible matrix. The weightings may be dependent on conditions of the desired and interferer signal to maximize signal-to-interference-plus-noise (SINR) of the desired signal. In example 1032, the subject matter of example 1031 optionally includes that the analog summation weight matrix comprises a Hadamard matrix. In example 1033, the subject matter of any one or more of examples 1027-1032 optionally include means for adjusting a variable gain of each compensated signal to normalize a power level of a signal supplied to a corresponding ADC of the ADCs. In example 1034, the subject matter of any one or more of examples 1027-1033 optionally include means for adjusting a number of the ADCs to use during a particular operation. In example 1035, the subject matter of any one or more of examples 1027-1034 optionally include means for selecting a dynamic range of each ADC dependent on a desired array interference rejection and angle resolution. Example 1036 is a computer-readable storage medium that stores instructions for execution by one or more processors of a communication device. The instructions may be configured to instruct the one or more processors to invert analog compensation of beamformed signals that have been quantized to form quantized signals prior to inversion of the analog compensation. Each beamformed signal may comprise a desired signal and an interferer signal. Each quantized signal may be provided on a different signal path. The instructions may further be configured to process the quantized signals after the inversion of the analog compensation to at least one of: determine a direction of at least one of the desired or interfering signal, or perform channel sounding. In example 1037, the subject matter of example 1036 optionally includes that the analog compensation comprises, for each signal path, combining a weighted copy of each of the beamformed signals. In example 1038, the subject matter of example 1037 optionally includes that an analog summation weight matrix that describes weightings of the beamformed signals is an invertible matrix. The weightings may be fixed. In example 1039, the subject matter of any one or more of examples 1037-1038 optionally include that an analog summation weight matrix that describes weightings of the beamformed signals is an invertible matrix. The instructions may be configured to instruct the one or more processors to adjust the weightings dependent on conditions of the desired and interferer signal to maximize signal-to-interference-plus-noise (SINR) of the desired signal. In example 1040, the subject matter of example 1039 optionally includes that the analog summation weight matrix comprises a Hadamard matrix. In example 1041, the subject matter of any one or more of examples 1036-1040 optionally include that the instructions configured to instruct the one or more processors to adjust a variable gain of each analog compensated beamformed signal to normalize a power level of the analog compensated beamformed signal prior to quantization of the analog compensated beamformed signal to form the quantized signal. In example 1042, the subject matter of any one or more of examples 1036-1041 optionally include that the instructions configured to instruct the one or more processors to adjust a number of simultaneous quantizations active during a particular operation. In example 1043, the subject matter of any one or more of examples 1036-1042 optionally include wherein the instructions configured to instruct the one or more processors to select a dynamic range of each quantization dependent on a desired array interference rejection and angle resolution of the beamformed signals. Example 1044 is a loopback-based time skew calibration circuit for a time-interleaved analog-to-digital converter (ADC) that may comprise a plurality of signal channels, each channel comprising a digital-to-analog converter (DAC) in a transmit path of a radio-frequency transceiver and an ADC driven by a clock in a receive path of the transceiver, a reference signal generator to generate a reference signal in the transmit path of at least one signal channel, a loopback connection to transmit the reference signal to the receive path corresponding to the transmit path of the at least one signal channel, a phase estimator to determine an estimated time skew associated with the reference signal, and a delay correction circuit to control the clock timing to compensate for the estimated time skew and that comprises an input at which the estimated time skew is provided. In example 1045, the subject matter of example 1044 optionally includes that the reference signal generator generates the reference signal in the transmit path of all signal channels. In example 1046, the subject matter of any one or more of examples 1044-1045 optionally include a transmit path intermediate-frequency (IF) amplifier, and a receive path IF amplifier, and the loopback connection is connected adjacent to both the transmit path IF amplifier and the receive path IF amplifier. In example 1047, the subject matter of any one or more of examples 1044-1046 optionally include that the at least one signal channel comprises an in-phase (I) sub-channel and a quadrature (Q) sub-channel, the reference signal is provided in an I transmit sub-path and a Q transmit sub-path, the phase estimator comprises an I phase estimator and a Q phase estimator, and the delay correction circuit comprises an I delay correction circuit and a Q delay correction circuit. In example 1048, the subject matter of any one or more of examples 1044-1047 optionally include that the reference signal is a sinusoidal signal of a predefined frequency. In example 1049, the subject matter of example 1048 optionally includes that the reference signal has a form s(t) = Asin(2πft + θ), where f predefined sinusoid frequency, θ phase of the sinusoid, and A amplitude of the sinusoid. In example 1050, the subject matter of any one or more of examples 1044-1049 optionally include that the reference signal is a complex exponential signal. In example 1051, the subject matter of example 1050 optionally includes that the reference signal has a form sI(t) = AIcos(2πft + θ), sQ(t) = AQsin(2πft + θ), where f predefined sinusoid frequency, θ phase of the sinusoid, AI amplitude of the in-phase sinusoid, and AQ amplitude of the quadrature sinusoid. In example 1052, the subject matter of any one or more of examples 1044-1051 optionally include that the ADCs are combined to form a time-interleaved analog-to-digital converter (TI-ADC). In example 1053, the subject matter of example 1052 optionally includes that the ADCs operate with a common sampling frequency. In example 1054, the subject matter of any one or more of examples 1044-1053 optionally include that the circuit is integrated with modem circuitry for the radio-frequency transceiver. In example 1055, the subject matter of example 1054 optionally includes that the modem circuitry is integrated with the radio-frequency transceiver. Example 1056 is a method for operating a loopback-based time skew calibration circuit for a time-interleaved analog-to-digital converter (ADC), that may comprise generating, by a reference signal generator, a reference signal that is provided to at least one of a plurality of signal channels, each signal channel comprising a digital-to-analog converter (DAC) in a transmit path of the transceiver and an analog-to-digital converter (ADC) driven by a clock in a receive path of the transceiver, communicating the reference signal from the transmit path to the receive path corresponding to the transmit path of the at least one signal channel, calculating, with a phase estimator, an estimated time skew based on the reference signal, and correcting clock timing with a delay correction circuit to control the clock timing to compensate for the estimated time skew. Example 1057 is a computer program product comprising one or more computer readable storage media comprising computer-executable instructions operable to, when executed by processing circuitry of a device, configure the device to generate, by a reference signal generator, a reference signal that is provided to at least one of a plurality of signal channels, each signal channel comprising a digital-to-analog converter (DAC) in a transmit path of the transceiver and an analog-to-digital converter (ADC) driven by a clock in a receive path of the transceiver, communicate the reference signal from the transmit path to the receive path corresponding to the transmit path of the at least one signal channel, calculate, with a phase estimator, an estimated time skew based on the reference signal, and correct clock timing with a delay correction circuit to control the clock timing to compensate for the estimated time skew. In example 1058, the subject matter of example 1057 optionally includes that the reference signal generator generates the reference signal in the transmit path of all signal channels. Example 1059 is a system comprising means to perform method Example 1056. Example 1060 is an apparatus for operating a loopback-based time skew calibration circuit for a time-interleaved analog-to-digital converter (ADC), that may comprise means for generating, by a reference signal generator, a reference signal that is provided to at least one of a plurality of signal channels, each signal channel comprising a digital-to-analog converter (DAC) in a transmit path of the transceiver and an analog-to-digital converter (ADC) driven by a clock in a receive path of the transceiver, means for communicating the reference signal from the transmit path to the receive path corresponding to the transmit path of the at least one signal channel, means for calculating, with a phase estimator, an estimated time skew based on the reference signal, and means for correcting clock timing with a delay correction circuit to control the clock timing to compensate for the estimated time skew. In example 1061, the subject matter of example 1060 optionally includes that the reference signal generator generates the reference signal in the transmit path of all signal channels. In example 1062, the subject matter of any one or more of examples 1060-1061 optionally include means for amplifying an intermediate-frequency signal in a transmit path, and means for amplifying an IF signal in a receive path, that the loopback connection is connected adjacent to both the transmit path amplifier and the receive path amplifier. In example 1063, the subject matter of any one or more of examples 1060-1062 optionally include that the reference signal is a sinusoidal signal of a predefined frequency. In example 1064, the subject matter of example 1063 optionally includes that the reference signal has a form s(t) = Asin(2πft + θ), where f predefined sinusoid frequency, θ phase of the sinusoid, and A amplitude of the sinusoid. In example 1065, the subject matter of any one or more of examples 1060-1064 optionally include that the reference signal is a complex exponential signal. In example 1066, the subject matter of example 1065 optionally includes that the reference signal has a form sI(t) = AIcos(2πft + θ), sQ(t) = AQsin(2πft + θ), where f predefined sinusoid frequency, θ phase of the sinusoid, AI amplitude of the in-phase sinusoid, and AQ amplitude of the quadrature sinusoid. In example 1067, the subject matter of any one or more of examples 1060-1066 optionally include that the ADCs are combined to form a time-interleaved analog-to-digital converter (TI-ADC). In example 1068, the subject matter of example 1067 optionally includes that the ADCs operate with a common sampling frequency. In example 1069, the subject matter of any one or more of examples 1060-1068 optionally include that the apparatus is integrated with modem circuitry for the radio-frequency transceiver. In example 1070, the subject matter of example 1069 optionally includes that the modem circuitry is integrated with the radio-frequency transceiver. Example 1071 is a time-interleaved analog-to-digital converter (TI-ADC) with a gain correction device, that may comprise a switch to switch between a device input in a normal operation mode and a reference voltage input in a calibration mode, and to output a switched signal, a plurality of signal channels, each comprising an analog-to-digital converter (ADC) to receive a slice of the switched signal and provide a digital output signal, a multiplexer to produce a combined output signal from the digital output signals of the ADCs, a measure and correction unit to adjust, or support the adjustment of, a signal when operating in the normal mode to produce a gain adjusted output signal and to provide a measurement signal when operating in the calibration mode, and a controller to control the switch and the measure and correction unit to operate in the normal operation mode or the calibration mode, store measurement signal related data in a memory for the adjustment of the combined output signal, and control an interleave timing of the signal channels. In example 1072, the subject matter of example 1071 optionally includes that the plurality of signal channels each further comprise a track or sample and hold circuit before the ADC that are collectively controlled by the controller to provide interleave timing and operation of the ADCs in a cascaded manner. In example 1073, the subject matter of example 1072 optionally includes that the switch is provided between the channel track or sample and hold circuits and respective ADCs. In example 1074, the subject matter of any one or more of examples 1071-1073 optionally include that the measurement signal related data are gain values that are used for the adjustment in respective channels. In example 1075, the subject matter of example 1074 optionally includes that the gain values are gain offsets. In example 1076, the subject matter of any one or more of examples 1074-1075 optionally include that the gain values are based on multiple reference voltage values provided by the reference voltage input. In example 1077, the subject matter of example 1076 optionally includes that the multiple reference voltage values are waveform signal values. In example 1078, the subject matter of example 1077 optionally includes that the waveform signal values are provided from a feedback signal derived from the gain adjusted output signal. In example 1079, the subject matter of any one or more of examples 1077-1078 optionally include that the waveform signal values are based on a complex exponential signal. In example 1080, the subject matter of any one or more of examples 1076-1079 optionally include that the gain values are stored in a look-up table (LUT) in the memory. In example 1081, the subject matter of any one or more of examples 1076-1080 optionally include that a gain value calculator utilizes linear interpolation for values between calibration values. In example 1082, the subject matter of any one or more of examples 1071-1081 optionally include that the controller is to make an analog adjustment within the signal channels based on the measurement signal related data. In example 1083, the subject matter of example 1082 optionally includes that the analog adjustment is made by a control of the ADCs. In example 1084, the subject matter of any one or more of examples 1071-1083 optionally include a temperature reference to provide temperature-related information to associate and store with the measurement signal related data. Example 1085 is a method for operating a time-interleaved analog-to-digital converter (TI-ADC) with gain correction device, that may comprise switching between a device input in a normal operation mode and a reference voltage input in a calibration mode, and outputting a switched signal, receiving, with a plurality of signal channels, each comprising an analog-to-digital converter (ADC), a slice of the switched signal and provide a digital output signal, producing, with a multiplexer, a combined output signal from the digital output signals of the ADCs, adjusting or supporting the adjustment of a signal when operating in the normal mode to produce a gain adjusted output signal and to provide a measurement signal when operating in the calibration mode, and controlling the switch and the measure and correction unit to operate in the normal operation mode or the calibration mode, store measurement signal related data in a memory for the adjustment of the combined output signal, and control an interleave timing of the signal channels. Example 1086 is a computer program product comprising one or more computer readable storage media comprising computer-executable instructions operable to, when executed by processing circuitry of a device, configure the device to switch between a device input in a normal operation mode and a reference voltage input in a calibration mode, and outputting a switched signal, receive, with a plurality of signal channels, each comprising an analog-to-digital converter (ADC), a slice of the switched signal and provide a digital output signal, produce, with a multiplexer, a combined output signal from the digital output signals of the ADCs, adjust or support the adjustment of a signal when operating in the normal mode to produce a gain adjusted output signal and to provide a measurement signal when operating in the calibration mode, and control the switch and the measure and correction unit to operate in the normal operation mode or the calibration mode, store measurement signal related data in a memory for the adjustment of the combined output signal, and control an interleave timing of the signal channels. In example 1087, the subject matter of example 1086 optionally includes that the plurality of signal channels each further comprise a track or sample and hold circuit before the ADC that are collectively controlled by the controller to provide interleave timing and operation of the ADCs in a cascaded manner. Example 1088 is a system comprising means to perform the method of example 1087. Example 1089 is a device for operating a time-interleaved analog-to-digital converter (TI-ADC) with a gain correction device, that may comprise means for switching between a device input in a normal operation mode and a reference voltage input in a calibration mode, and outputting a switched signal, means for receiving, with a plurality of signal channels, each comprising an analog-to-digital converter (ADC), a slice of the switched signal and provide a digital output signal, means for producing, with a multiplexer, a combined output signal from the digital output signals of the ADCs, means for adjusting or supporting the adjustment of a signal when operating in the normal mode to produce a gain adjusted output signal and to provide a measurement signal when operating in the calibration mode, and means for controlling the switch and the measure and correction unit to operate in the normal operation mode or the calibration mode, store measurement signal related data in a memory for the adjustment of the combined output signal, and control an interleave timing of the signal channels. In example 1090, the subject matter of example 1089 optionally includes that the plurality of signal channels each further comprise a track or sample and hold circuit before the ADC that are collectively controlled by the means for controlling to provide interleave timing and operation of the ADCs in a cascaded manner. In example 1091, the subject matter of example 1090 optionally includes that the means for switching is provided between the channel track or sample and hold circuits and respective ADCs. In example 1092, the subject matter of example 1091 optionally includes, that the measurement signal related data are gain values that are used for the means for adjusting in respective channels. In example 1093, the subject matter of example 1092 optionally includes that the gain values are gain offsets. In example 1094, the subject matter of any one or more of examples 1092-1094 optionally include that the gain values are based on multiple reference voltage values provided by the reference voltage input. In example 1095, the subject matter of example 1094 optionally includes that the multiple reference voltage values are waveform signal values. In example 1096, the subject matter of example 1095 optionally includes that the waveform signal values are provided from a feedback signal derived from the gain adjusted output signal. In example 1097, the subject matter of any one or more of examples 1095-1096 optionally include that the waveform signal values are based on a complex exponential signal. In example 1098, the subject matter of any one or more of examples 1094-1097 optionally include that the gain values are stored in a look-up table (LUT) in the memory. In example 1099, the subject matter of any one or more of examples 1094-1098 optionally include that a gain value calculator utilizes linear interpolation for values between calibration values. In example 1100, the subject matter of example 1099 optionally includes that the means for controlling makes an analog adjustment within the signal channels based on the measurement signal related data. In example 1101, the subject matter of example 1100 optionally includes that the analog adjustment is made by a control of the ADCs. In example 1102, the subject matter of example 1101 optionally includes, further comprising a means to provide temperature-related information to associate and store with the measurement signal related data. Example 1103 is a phased array transmitter, that may comprise a plurality of transmission channels, each comprising an antenna and a transmit amplifier connected to the antenna, a transmission power splitter to split an output signal into a plurality of output channel signals that are provided to the transmit amplifiers in the transmission channels, baseband to RF transmission circuitry to convert digital transmission data into the output signal, an external non-linear data processor to determine non-linearity characteristics of a signal regarding a power transmission signal characteristic of an external phased array transceiver (EPAT) and to provide non-linearity data usable for correcting non-linearities in the EPAT to the IF transmitter stage for transmission to the EPAT. In example 1104, the subject matter of example 1103 optionally includes a radio frequency (RF) modulation stage to provide the output signal to the transmission power splitter, and an intermediate frequency (IF) modulation stage comprising a digital-to-analog converter (DAC) to convert a digital baseband output signal into an IF output signal. In example 1105, the subject matter of example 1104 optionally includes that the non-linearity data comprises polynomial coefficients of a curve that compensates the non-linearity of a characteristic curve of an input power versus and output power for the EPAT. In example 1106, the subject matter of example 1105 optionally includes that the polynomial coefficients of the curve are of a fifth order or less. In example 1107, the subject matter of any one or more of examples 1104-1106 optionally include that the non-linearity data comprises look-up table (LUT) values that correspond to compensate the non-linearity of a characteristic curve of an input power versus and output power for the EPAT. In example 1108, the subject matter of any one or more of examples 1104-1107 optionally include that the transmitter is a transceiver, further that may comprise a phased array receiver, that may comprise a plurality of reception channels, each comprising an antenna and a receiver amplifier connected to the antenna, a reception power combiner to combine a plurality of input channel signals provided by the receive amplifiers in the reception channels into an input signal, a radio frequency (RF) demodulation stage to convert the RF signal into an intermediate frequency (IF) signal, and an intermediate frequency (IF) demodulation stage comprising an analog-to-digital converter (ADC) to convert the IF signal into a digital baseband input signal, an internal non-linear data processor to process non-linearity data contained within the digital baseband input signal, a digital pre-distortion (DPD) processor that may comprise a control input for receiving control signals based on the processed non-linearity data, and a data input comprising a baseband digital data signal for transmission, and a data output to provide an output signal that has been modified by the DPD to output a signal that will extend a collective linear output of the transmit amplifiers within the transmission channels based on the non-linearity data. Example 1109 is a method for calibrating a phased array transceiver, that may comprise splitting a transmission signal into signals provided to a plurality of transmission channels, each comprising an antenna and a transmit amplifier connected to the antenna, transmitting an output signal via the antennas of the channels to an external phased array transceiver (EPAT), the output signal having a combined power output that is a sum of power outputs of the channels of the phased antenna array, receiving, at an input of the transceiver, non-linearity data that is inversely related to an antenna characteristic curve of the sum of the power outputs of the individual channels of the phased antenna array, translating the non-linearity data into control data of a digital pre-distortion (DPD) processor such that the DPD processor modifies the output signal to extend a collective linear output of the transmit amplifiers within the transmission channels based on the non-linearity data, and transmitting the DPD processor modified output signals via the antennas of the channels. Example 1110 is a computer program product comprising one or more computer readable storage media comprising computer-executable instructions operable to, when executed by processing circuitry of a device, configure the device to split a transmission signal into signals provided to a plurality of transmission channels, each comprising an antenna and a transmit amplifier connected to the antenna, transmit an output signal via the antennas of the channels to an external phased array transceiver (EPAT), the output signal having a combined power output that is a sum of power outputs of the channels of the phased antenna array, receive, at an input of the transceiver, non-linearity data that is inversely related to an antenna characteristic curve of the sum of the power outputs of the individual channels of the phased antenna array, translate the non-linearity data into control data of a digital pre-distortion (DPD) processor such that the DPD processor modifies the output signal to extend a collective linear output of the transmit amplifiers within the transmission channels based on the non-linearity data, and transmit the DPD processor modified output signals via the antennas of the channels. In example 1111, the subject matter of example 1110 optionally includes that the instructions are further operable to provide the output signal to the transmission power splitter, and convert a digital baseband output signal into an IF output signal. Example 1112 is a means for transmitting a radio frequency signal, that may comprise means for splitting a transmission signal into signals provided to a plurality of transmission channels, each comprising an antenna and a transmit amplifier connected to the antenna, means for transmitting an output signal via the antennas of the channels to an external phased array transceiver (EPAT), the output signal having a combined power output that is a sum of power outputs of the channels of the phased antenna array, means for receiving, at an input of the transceiver, non-linearity data that is inversely related to an antenna characteristic curve of the sum of the power outputs of the individual channels of the phased antenna array, means for translating the non-linearity data into control data of a digital pre-distortion (DPD) processor such that the DPD processor modifies the output signal to extend a collective linear output of the transmit amplifiers within the transmission channels based on the non-linearity data, and means for transmitting the DPD processor modified output signals via the antennas of the channels. In example 1113, the subject matter of example 1112 optionally includes that the non-linearity data comprises polynomial coefficients of a curve that compensates the non-linearity of a characteristic curve of an input power versus and output power for the EPAT. In example 1114, the subject matter of example 1113 optionally includes that the polynomial coefficients of the curve are of a fifth order or less. In example 1115, the subject matter of any one or more of examples 1112-1114 optionally include that the non-linearity data comprises look-up table (LUT) values that correspond to compensate the non-linearity of a characteristic curve of an input power versus and output power for the EPAT. In example 1116, the subject matter of any one or more of examples 1112-1115 optionally include that the transmitter is a transceiver, further that may comprise a phased array receiver, that may comprise a plurality of reception channels, each comprising an antenna and a receiver amplifier connected to the antenna, a reception power combiner to combine a plurality of input channel signals provided by the receive amplifiers in the reception channels into an input signal, a radio frequency (RF) demodulation stage to convert the RF signal into an intermediate frequency (IF) signal, and an intermediate frequency (IF) demodulation stage comprising an analog-to-digital converter (ADC) to convert the IF signal into a digital baseband input signal, an internal non-linear data processor to process non-linearity data contained within the digital baseband input signal, a digital pre-distortion (DPD) processor that may comprise a control input for receiving control signals based on the processed non-linearity data, and a data input comprising a baseband digital data signal for transmission, and a data output to provide an output signal that has been modified by the DPD to output a signal that will extend a collective linear output of the transmit amplifiers within the transmission channels based on the non-linearity data. In example 1117, the subject matter of any one or more of examples 1112-1116 optionally include a radio frequency (RF) modulation stage to provide the output signal to the transmission power splitter, and an intermediate frequency (IF) modulation stage comprising a digital-to-analog converter (DAC) to convert a digital baseband output signal into an IF output signal. Example 1118 is a gain control device for a receiver, comprising a processor and a memory, the processor configured to in a dithering operation mode receive a first input signal at a first signal power level, separately apply, using a switch, a first and second AGC gain setting to the input signal and respectively measure a first and second signal quality measure (SQM) for the first and second AGC gain settings, and determine and store an optimal threshold value representing a power level used to switch between using the first AGC gain setting and the second AGC gain setting based on the first and second SQMs, in a normal operation mode determine whether to use the first or second AGC gain setting for a second input signal at the first signal power level based on the optimal threshold value. In example 1119, the subject matter of example 1118 optionally includes that the first input signal is at least one of a radio frequency input signal, an intermediate frequency input signal, or a baseband signal. In example 1120, the subject matter of any one or more of examples 1118-1119 optionally include that the switch is to operate on a plurality of input signals for a given input frame. In example 1121, the subject matter of any one or more of examples 1118-1120 optionally include that the SQM is an error vector magnitude (EVM). In example 1122, the subject matter of any one or more of examples 1118-1121 optionally include that the optimal threshold value is stored in a look-up table (LUT). In example 1123, the subject matter of any one or more of examples 1118-1122 optionally include that the processor is further configured to in the dithering operation mode, determine and store a further condition value associated with the optimum threshold value, and in the normal operation mode, determine whether to use the first or second AGC gain setting additionally based on the further condition value. In example 1124, the subject matter of example 1123 optionally includes that the further condition value is at least one of a temperature, a channel, an operating frequency, or a voltage. In example 1125, the subject matter of any one or more of examples 1118-1124 optionally include a power level detector located in a modem of the receiver that is utilized to determine the power level of the input signal. In example 1126, the subject matter of any one or more of examples 1118-1125 optionally include that the processor is further configured to place the device in the dithering operation mode based on a pre-defined condition. In example 1127 the subject matter of example 1126 optionally includes that the pre-defined condition is the expiration of a timer. In example 1128, the subject matter of example 1127 optionally includes that the determination of the optimal threshold value utilizes a difference between the first and second SQM for the determined value. In example 1129, the subject matter of example 1128 optionally includes that the determination of the optimal threshold value further utilizes stored power vs. SQM curve shapes for the determined value. In example 1130, the subject matter of any one or more of examples 1118-1129 optionally include that the receiver is a phased array receiver. Example 1131 is a method for operating a gain control device for a receiver, that may comprise in a dithering operation mode receiving a first input signal at a first signal power level, separately applying, using a switch, a first and second AGC gain setting to the input signal and respectively measuring a first and second signal quality measure (SQM) for the first and second AGC gain settings, and determining and storing an optimal threshold value representing a power level used to switch between using the first AGC gain setting and the second AGC gain setting based on the first and second SQMs, in a normal operation mode determining whether to use the first or second AGC gain setting for a second input signal at the first signal power level based on the optimal threshold value. In example 1132, the subject matter of example 1131 optionally includes that the first input signal is at least one of a radio frequency input signal, an intermediate frequency input signal, or a baseband signal. In example 1133, the subject matter of any one or more of examples 1131-1132 optionally include that the switch operates on a plurality of input signals for a given input frame. In example 1134, the subject matter of any one or more of examples 1131-1133 optionally include that the SQM is an error vector magnitude (EVM). In example 1135, the subject matter of any one or more of examples 1131-1134 optionally include that the optimal threshold value is stored in a look-up table (LUT). In example 1136, the subject matter of any one or more of examples 1131-1135 optionally include in the dithering operation mode, determining and storing a further condition value associated with the optimum threshold value, and in the normal operation mode, determining whether to use the first or second AGC gain setting additionally based on the further condition value. In example 1137, the subject matter of example 1136 optionally includes that the further condition value is at least one of a temperature, a channel, an operating frequency, or a voltage. In example 1138, the subject matter of any one or more of examples 1131-1137 optionally include determining, with a power level detector located in a modem of the receiver, the power level of the input signal. In example 1139, the subject matter of any one or more of examples 1131-1138 optionally include placing the device in the dithering operation mode based on a pre-defined condition. In example 1140, the subject matter of example 1139 optionally includes that the pre-defined condition is the expiration of a timer. In example 1141, the subject matter of example 1140 optionally includes that the determining of the optimal threshold value utilizes a difference between the first and second SQM for the determined value. In example 1142, the subject matter of example 1141 optionally includes that the determining of the optimal threshold value further utilizes stored power vs. SQM curve shapes for the determined value. In example 1143, the subject matter of any one or more of examples 1131-1142 optionally include that the receiver is a phased array receiver. Example 1144 is a computer program product comprising one or more computer readable storage media comprising computer-executable instructions operable to, when executed by processing circuitry of a device, configure the device to in a dithering operation mode receive a first input signal at a first signal power level, separately apply, using a switch, a first and second AGC gain setting to the input signal and respectively measuring a first and second signal quality measure (SQM) for the first and second AGC gain settings, and determine and store an optimal threshold value representing a power level used to switch between using the first AGC gain setting and the second AGC gain setting based on the first and second SQMs, in a normal operation mode determine whether to use the first or second AGC gain setting for a second input signal at the first signal power level based on the optimal threshold value. In example 1145, the subject matter of example 1144 optionally includes that the first input signal is at least one of a radio frequency input signal, an intermediate frequency input signal, or a baseband signal. Example 1146 is a computer program product comprising one or more computer readable storage media comprising computer-executable instructions operable to, when executed by processing circuitry of a device, configure the device to perform any of the methods of the above method Examples. Example 1147 is a system comprising means to perform any of the methods of examples 1131-1143. Example 1148 is a gain control device for a receiver, that may comprise means for, in a dithering operation mode receiving a first input signal at a first signal power level, separately applying, using a switch, a first and second AGC gain setting to the input signal and respectively measuring a first and second signal quality measure (SQM) for the first and second AGC gain settings, and determining and storing an optimal threshold value representing a power level used to switch between using the first AGC gain setting and the second AGC gain setting based on the first and second SQMs, and means for, in a normal operation mode determining whether to use the first or second AGC gain setting for a second input signal at the first signal power level based on the optimal threshold value. In example 1149, the subject matter of example 1148 optionally includes that the first input signal is at least one of a radio frequency input signal, an intermediate frequency input signal, or a baseband signal. In example 1150, the subject matter of any one or more of examples 1148-1149 optionally include that the switch operates on a plurality of input signals for a given input frame. In example 1151, the subject matter of any one or more of examples 1148-1150 optionally include that the SQM is an error vector magnitude (EVM). In example 1152, the subject matter of any one or more of examples 1148-1151 optionally include that the optimal threshold value is stored in a look-up table (LUT). In example 1153, the subject matter of any one or more of examples 1148-1152 optionally include means for, in the dithering operation mode, determining and storing a further condition value associated with the optimum threshold value, and means for, in the normal operation mode, determining whether to use the first or second AGC gain setting additionally based on the further condition value. In example 1154, the subject matter of example 1153 optionally includes that the further condition value is at least one of a temperature, a channel, an operating frequency, or a voltage. In example 1155, the subject matter of any one or more of examples 1148-1154 optionally include means for determining, with a power level detector located in a modem of the receiver, the power level of the input signal. In example 1156, the subject matter of any one or more of examples 1148-1155 optionally include means for placing the device in the dithering operation mode based on a pre-defined condition. In example 1157, the subject matter of example 1156 optionally includes that the pre-defined condition is the expiration of a timer. In example 1158, the subject matter of example 1157 optionally includes that the means for determining of the optimal threshold value utilizes a difference between the first and second SQM for the determined value. In example 1159, the subject matter of example 1158 optionally includes that the means for determining of the optimal threshold value further utilizes stored power vs. SQM curve shapes for the determined value. In example 1160, the subject matter of any one or more of examples 1148-1159 optionally include that the receiver is a phased array receiver. Example 1161 is a phased array radio transceiver, that may comprise a plurality of tiled and interconnected transceiver cells, each that may comprise a transmitter, a receiver, a digital processing block, an input-output and phase-combining unit, and a multiplexer and demultiplexer on each of four cell edges to communication with adjacent similar cells, a bus that interconnects the cells and that carries an oscillator signal and control signals between the cells. In example 1162, the subject matter of example 1161 optionally includes that at least one of the transmitter comprises multiple transmitters or the receiver comprises multiple receivers is true. In example 1163, the subject matter of any one or more of examples 1161-1162 optionally include that the bus is an analog and digital bus. In example 1164, the subject matter of any one or more of examples 1161-1163 optionally include that a width of the bus is equal to a number of simultaneously supportable users. In example 1165, the subject matter of any one or more of examples 1161-1164 optionally include that each cell is only directly connectable to an adjacent cell element on each side of its cell edges. In example 1166, the subject matter of any one or more of examples 1161-1165 optionally include an antenna array that is combined with a wafer comprising the plurality of tiled transceiver cells. In example 1167, the subject matter of any one or more of examples 1161-1166 optionally include that each cell further comprises a self-configurable element that allow the cell to generate a unique, within the interconnected transceiver cells, identifier for itself. In example 1168, the subject matter of example 1167 optionally includes that a first cell self-identifies itself with a first identifier when a predefined criteria is met. In example 1169, the subject matter of example 1168 optionally includes that the predefined criteria is that the cell is a corner cell. In example 1170, the subject matter of example 1169 optionally includes that non-first cells identify themselves by receiving identifier-related information from an adjacent cell, and then send further identifier related information to another adjacent cell. In example 1171, the subject matter of any one or more of examples 1161-1170 optionally include that each cell further comprises a loopback to measure and calibrate out delay introduced by the cell. In example 1172, the subject matter of any one or more of examples 1161-1171 optionally include that each cell is operable in a digital phase array mode and further comprises a combining element to vector sum a digitized received signal with a received signal from a cell having an immediate predecessor cell, when present. In example 1173, the subject matter of example 1172 optionally includes that the vector sum between each cell is pipelined. In example 1174, the subject matter of any one or more of examples 1172-1173 optionally include that each cell contains k busses to support k users. In example 1175, the subject matter of any one or more of examples 1161-1174 optionally include that each cell is operable in a local oscillator (LO) phase combine mode, each cell receives its phase shift from a central control point, mixer outputs are summed in an analog domain, and only one analog-to-digital converter (ADC) converts the summed mixer outputs into a digital signal. In example 1176, the subject matter of any one or more of examples 1161-1175 optionally include that each cell is operable in a hybrid operation mode in which each row is tiled in a local oscillator phase shifting and shares a single analog-to-digital converter. In example 1177, the subject matter of any one or more of examples 1161-1176 optionally include that each cell is operable in an analog phased array combine operation mode in which a first complex function is applied to a received input signal by the cell and a result is combined with a further result of a second complex function applied to a received input from another cell. Example 1178 is a method for operating a phased array radio transceiver, that may comprise transmitting and receiving a signal with a plurality of tiled and interconnected transceiver cells, each that may comprise a transmitter, a receiver, a digital processing block, an input-output and phase-combining unit, and a multiplexer and demultiplexer on each of four cell edges to communication with adjacent similar cells, and communicating between the cells using a bus that interconnects the cells and that carries an oscillator signal and control signals between the cells. In example 1179, the subject matter of example 1178 optionally includes that at least one of the transmitter comprises multiple transmitters or the receiver comprises multiple receivers is true. In example 1180, the subject matter of any one or more of examples 1178-1179 optionally include that the bus is an analog and digital bus. In example 1181, the subject matter of any one or more of examples 1178-1180 optionally include that a width of the bus is equal to a number of simultaneously supportable users. In example 1182, the subject matter of any one or more of examples 1178-1181 optionally include that each cell is only directly connectable to an adjacent cell element on each side of its cell edges. In example 1183, the subject matter of any one or more of examples 1178-1182 optionally include an antenna array that is combined with a wafer comprising the plurality of tiled transceiver cells. In example 1184, the subject matter of any one or more of examples 1178-1183 optionally include generating, for each cell, a unique, within the interconnected transceiver cells, identifier for itself. In example 1185, the subject matter of example 1184 optionally includes that a first cell self-identifies itself with a first identifier when a predefined criteria is met. In example 1186, the subject matter of example 1185 optionally includes that the predefined criteria is that the cell is a corner cell. In example 1187, the subject matter of example 1186 optionally includes identifying, by non-first cells, themselves by receiving identifier-related information from an adjacent cell, and then sending further identifier related information to another adjacent cell. In example 1188, the subject matter of any one or more of examples 1178-1187 optionally include that each cell further comprises a loopback to measure and calibrate out delay introduced by the cell. In example 1189, the subject matter of any one or more of examples 1178-1188 optionally include vector summing, in a digital phase array mode, a digitized received signal from a cell having an immediate predecessor cell, when present. In example 1190, the subject matter of example 1189 optionally includes that the vector sum between each cell is pipelined. In example 1191, the subject matter of any one or more of examples 1189-1190 optionally include that each cell contains k busses to support k users. In example 1192, the subject matter of any one or more of examples 1178-1191 optionally include that each cell is operable in a local oscillator (LO) phase combine mode, each cell receives its phase shift from a central control point, mixer outputs are summed in an analog domain, and only one analog-to-digital converter (ADC) converts the summed mixer outputs into a digital signal. In example 1193, the subject matter of any one or more of examples 1178-1192 optionally include that each cell is operable in a hybrid operation mode in which each row is tiled in a local oscillator phase shifting and shares a single analog-to-digital converter. In example 1194, the subject matter of any one or more of examples 1178-1193 optionally include that each cell is operable in an analog phased array combine operation mode in which a first complex function is applied to a received input signal by the cell and a result is combined with a further result of a second complex function applied to a received input from another cell. Example 1195 is a computer program product comprising one or more computer readable storage media comprising computer-executable instructions operable to, when executed by processing circuitry of a device, configure the device to transmit and receive a signal with a plurality of tiled and interconnected transceiver cells, each that may comprise a transmitter, a receiver, a digital processing block, an input-output and phase-combining unit, and a multiplexer and demultiplexer on each of four cell edges to communication with adjacent similar cells, and communicate between the cells using a bus that interconnects the cells and that carries an oscillator signal and control signals between the cells. In example 1196, the subject matter of example 1195 optionally includes that each cell is only directly connectable to an adjacent cell element on each side of its cell edges. Example 1197 is a computer program product comprising one or more computer readable storage media comprising computer-executable instructions operable to, when executed by processing circuitry of a device, configure the device to perform any of the methods of examples 1178-1194. Example 1198 is a system comprising means to perform any of the methods of examples 1178-1194. Example 1199 is a phased array radio transceiver, that may comprise means for transmitting and receiving a signal with a plurality of tiled and interconnected transceiver cells, each that may comprise a transmitter, a receiver, a digital processing block, an input-output and phase-combining unit, and a multiplexer and demultiplexer on each of four cell edges to communication with adjacent similar cells, and means for communicating between the cells using a bus that interconnects the cells and that carries an oscillator signal and control signals between the cells. In example 1200, the subject matter of example 1199 optionally includes, that at least one of the transmitter comprises multiple transmitters or the receiver comprises multiple receivers is true. In example 1201, the subject matter of examples 1199-1200 optionally includes, that the bus is an analog and digital bus. In example 1202, the subject matter of examples 1199-1201 optionally includes, that a width of the bus is equal to a number of simultaneously supportable users. In example 1203, the subject matter of examples 1199-1202 optionally includes, that each cell is only directly connectable to an adjacent cell element on each side of its cell edges. In example 1204, the subject matter of examples 1199-1203 optionally includes, further comprising an antenna array that is combined with a wafer comprising the plurality of tiled transceiver cells. In example 1205, the subject matter of examples 1199-1204 optionally includes, generating, for each cell, a unique, within the interconnected transceiver cells, identifier for itself. In example 1206, the subject matter of example 1205 optionally includes that a first cell self-identifies itself with a first identifier when a predefined criteria is met. In example 1207, the subject matter of example 1206 optionally includes that the predefined criteria is that the cell is a corner cell. In example 1208, the subject matter of example 1207 optionally includes identifying, by non-first cells, themselves by receiving identifier-related information from an adjacent cell, and then sending further identifier related information to another adjacent cell. In example 1209, the subject matter of example 1208 optionally includes, that each cell further comprises a loopback to measure and calibrate out delay introduced by the cell. In example 1210, the subject matter of example 1209 optionally includes, vector summing, in a digital phase array mode, a digitized received signal from a cell having an immediate predecessor cell, when present. In example 1211, the subject matter of example 1210 optionally includes that the vector sum between each cell is pipelined. In example 1212, the subject matter of any one or more of examples 1210-1211 optionally include that each cell contains k busses to support k users. In example 1213, the subject matter of example 1212 optionally includes, that each cell is operable in a local oscillator (LO) phase combine mode, each cell receives its phase shift from a central control point, mixer outputs are summed in an analog domain, and only one analog-to-digital converter (ADC) converts the summed mixer outputs into a digital signal. In example 1214, the subject matter of example 1213 optionally includes, that each cell is operable in a hybrid operation mode in which each row is tiled in a local oscillator phase shifting and shares a single analog-to-digital converter. In example 1215, the subject matter of example 1214 optionally includes, that each cell is operable in an analog phased array combine operation mode in which a first complex function is applied to a received input signal by the cell and a result is combined with a further result of a second complex function applied to a received input from another cell. Example 1216 is an injection-locked modulation circuit for a phased array transceiver, that may comprise a tank circuit comprising an inductor connected to a capacitive digital-to-analog converter (CAP-DAC), a tank circuit frequency being modifiable by a data input signal, an injection circuit that provides a locking injection frequency to lock an output frequency of the tank circuit at an integer subharmonic N of an output carrier frequency, that data values of the data input signal modify a phase of the locked tank circuit output frequency by an amount of ± 180°/N, and a frequency multiplier that produces a carrier frequency by multiplying the locked tank circuit output frequency by N. In example 1217, the subject matter of example 1216 optionally includes that the injection circuit is a phase-locked loop (PLL). In example 1218, the subject matter of any one or more of examples 1216-1217 optionally include that the locking injection frequency is a second integer subharmonic M of the tank circuit frequency. In example 1219, the subject matter of example 1218 optionally includes that M=3. In example 1220, the subject matter of any one or more of examples 1216-1219 optionally include that N=3. In example 1221, the subject matter of any one or more of examples 1216-1220 optionally include that N=2, and the circuit further comprises a Gilbert quad/polarity switch connected between the frequency multiplier and an antenna. In example 1222, the subject matter of any one or more of examples 1216-1221 optionally include a digital power amplifier connected to the frequency multiplier, and an antenna connected to the power amplifier to transmit a wireless signal. Example 1223 is a method for operating an injection-locked modulation circuit for a phased array transceiver, that may comprise modifying a tank circuit frequency of a tank circuit comprising an inductor connected to a capacitive digital-to-analog converter (CAP-DAC) by a data input signal, providing a locking injection frequency by an injection circuit to lock an output frequency of the tank circuit at an integer subharmonic N of an output carrier frequency, that data values of the data input signal modify a phase of the locked tank circuit output frequency by an amount of ± 180°/N, and producing, with a frequency multiplier, a carrier frequency by multiplying the locked tank circuit output frequency by N. In example 1224, the subject matter of example 1223 optionally includes that the injection circuit is a phase-locked loop (PLL). In example 1225, the subject matter of any one or more of examples 1223-1224 optionally include that the locking injection frequency is a second integer subharmonic M of the tank circuit frequency. In example 1226, the subject matter of example 1225 optionally includes that M=3. In example 1227, the subject matter of any one or more of examples 1223-1226 optionally include that N=3. In example 1228, the subject matter of any one or more of examples 1223-1227 optionally include that N=2 and the method further comprises operating a Gilbert quad/polarity switch connected between the frequency multiplier and an antenna. In example 1229, the subject matter of any one or more of examples 1223-1228 optionally include transmitting a wireless signal with an antenna connected to a power amplifier. Example 1230 is a computer program product comprising one or more computer readable storage media comprising computer-executable instructions operable to, when executed by processing circuitry of a device, configure the device to modify a tank circuit frequency of a tank circuit comprising an inductor connected to a capacitive digital-to-analog converter (CAP-DAC) by a data input signal, provide a locking injection frequency by an injection circuit to lock an output frequency of the tank circuit at an integer subharmonic N of an output carrier frequency, that data values of the data input signal modify a phase of the locked tank circuit output frequency by an amount of ± 180°/N, and produce, with a frequency multiplier, a carrier frequency by multiplying the locked tank circuit output frequency by N. In example 1231, the subject matter of example 1230 optionally includes that the injection circuit is a phase-locked loop (PLL). Example 1232 is a computer program product comprising one or more computer readable storage media comprising computer-executable instructions operable to, when executed by processing circuitry of a device, configure the device to perform any of the methods of examples 1223-1229. Example 1233 is a system comprising means to perform any of the methods of examples 1223-1229. Example 1234 is an injection-locked modulation circuit for a phased array transceiver, that may comprise means for modifying a tank circuit frequency of a tank circuit comprising an inductor connected to a capacitive digital-to-analog converter (CAP-DAC) by a data input signal, means for providing a locking injection frequency by an injection circuit to lock an output frequency of the tank circuit at an integer subharmonic N of an output carrier frequency, that data values of the data input signal modify a phase of the locked tank circuit output frequency by an amount of ± 180°/N, and means for producing, with a frequency multiplier, a carrier frequency by multiplying the locked tank circuit output frequency by N. In example 1235, the subject matter of example 1234 optionally includes that the injection circuit is a phase-locked loop (PLL). In example 1236, the subject matter of any one or more of examples 1234-1235 optionally include that the locking injection frequency is a second integer subharmonic M of the tank circuit frequency. In example 1237, the subject matter of example 1236 optionally includes that M=3. In example 1238, the subject matter of any one or more of examples 1234-1237 optionally include that N=3. In example 1239, the subject matter of any one or more of examples 1234-1238 optionally include that N=2 and the circuitfurther comprises means for operating a Gilbert quad/polarity switch connected between the frequency multiplier and an antenna. In example 1240, the subject matter of any one or more of examples 1234-1239 optionally include means for transmitting a wireless signal with an antenna connected to a power amplifier. Example 1241 is an apparatus for performing clock and data recover (CDR) for a wireless quadrature amplitude modulation (QAM) signal in a wireless receiver, that may comprise in-phase (I) and quadrature (Q) channels to process QAM signals received by the receiver, a mode table in a memory of the apparatus that stores a plurality of mode values with adjustment indications, a mode unit comprising a processor to receive data from the I and Q channels, read a current mode from the mode table, and dependent on the current mode, adjust a current sampling phase of the signal consistent with the adjustment indication for the current mode. In example 1242, the subject matter of example 1241 optionally includes that the QAM supports at least four values. In example 1243, the subject matter of example 1242 optionally includes 16-QAM. In example 1244, the subject matter of any one or more of examples 1241-1243 optionally include that the current mode is dynamically adjusted during operation. In example 1245, the subject matter of any one or more of examples 1241-1244 optionally include that the mode table has modes that consider only the I channel or only the Q channel. In example 1246, the subject matter of example 1245 optionally includes that the processor is further configured to detect a communication problem in either the I channel or the Q channel and utilize a mode for a channel that the communication problem is not detected in. In example 1247, the subject matter of any one or more of examples 1241-1246 optionally include that the mode table has modes that consider both the I channel and the Q channel. In example 1248, the subject matter of any one or more of examples 1241-1247 optionally include that the mode table comprises at least eight modes defined as follows: Mode Early Out Late Out Sample Phase Decision 0 0 0 No Decision 1 1 0 Early 2 0 1 Late 3 1 1 No Decision 4 Early I Late I Bypass I 5 Early Q Late Q Bypass Q 6 Early I or Early Q Late I or Late Q I or Q 7 Early I and Early Q Late I and Late Q I and Q In example 1249, the subject matter of example 1248 optionally includes that the timing estimator determination is a function of a sign of a received data symbol and an error value. In example 1250, the subject matter of example 1249 optionally includes that the timing estimator determination is based on the following formula ZK = SIGN(DK) SIGN(DK-1) (EK - EK-1), ZK > 0 EARLY, ZK = 0 HOLD, ZK < 0 LATE. In example 1251, the subject matter of example 1250 optionally includes an estimator table used by the timing estimator comprising at least four data values, each having an associated sign and error value above and below the data value. In example 1252, the subject matter of example 1251 optionally includes that the error values above the highest data value and below the lowest data value are plus one, and all other error values are minus one. In example 1253, the subject matter of example 1252 optionally includes 16-QAM. In example 1254, the subject matter of example 1253 optionally includes that the estimator table comprises DK Sign(DK) EK +3 +1 +1 +1 -1 +1 +1 -1 -1 -1 -1 -1 -1 -1 -1 -3 -1 -1 -1 +1 that ZK is a timing estimator value, DK is a current data value, DK-1 is a previous data value, EK is a current error value, and EK-1 is a previous error value. In example 1255, the subject matter of any one or more of examples 1240-1254 optionally include a timing estimator that determines whether to adjust the sampling phase to an earlier point, hold it at its current point, or adjust it to a later point. Example 1256 is a method for performing clock and data recover (CDR) for a wireless quadrature amplitude modulation (QAM) signal in a wireless receiver, that may comprise processing in-phase (I) and quadrature (Q) channels of QAM signals received by the receiver, storing a plurality of mode values in a mode table memory of the apparatus with adjustment indications, receiving data from the I and Q channels, reading a current mode from the mode table, and dependent on the current mode, adjusting a current sampling phase of the signal consistent with the adjustment indication for the current mode. In example 1257, the subject matter of example 1256 optionally includes that the QAM supports at least four values. In example 1258, the subject matter of example 1257 optionally includes 16-QAM. In example 1259, the subject matter of any one or more of examples 1256-1258 optionally include dynamically adjusting the current mode during operation. In example 1260, the subject matter of any one or more of examples 1256-1259 optionally include that the mode table has modes that consider only the I channel or only the Q channel. In example 1261, the subject matter of example 1260 optionally includes detecting a communication problem in either the I channel or the Q channel and utilizing a mode for a channel that the communication problem is not detected in. In example 1262, the subject matter of any one or more of examples 1256-1261 optionally include that the mode table has modes that consider both the I channel and the Q channel. In example 1263, the subject matter of any one or more of examples 1256-1262 optionally include that the mode table comprises at least eight modes defined as follows: Mode Early Out Late Out Sample Phase Decision 0 0 0 No Decision 1 1 0 Early 2 0 1 Late 3 1 1 No Decision 4 Early I Late I Bypass I 5 Early Q Late Q Bypass Q 6 Early I or Early Q Late I or Late Q I or Q 7 Early I and Early Q Late I and Late Q I and Q In example 1264, the subject matter of example 1263 optionally includes that the timing estimator determination is a function of a sign of a received data symbol and an error value. In example 1265, the subject matter of example 1264 optionally includes that the timing estimator determination is based on the following formula ZK = SIGN(DK) SIGN(DK-1) (EK - EK-1), ZK > 0 EARLY, ZK = 0 HOLD, ZK < 0 LATE. In example 1266, the subject matter of example 1265 optionally includes an estimator table used by the timing estimator comprising at least four data values, each having an associated sign and error value above and below the data value. In example 1267, the subject matter of example 1266 optionally includes that the error values above the highest data value and below the lowest data value are plus one, and all other error values are minus one. In example 1268, the subject matter of example 1267 optionally includes 16-QAM. In example 1269, the subject matter of example 1268 optionally includes that the estimator table comprises DK Sign(DK) EK +3 +1 +1 +1 -1 +1 +1 -1 -1 -1 -1 -1 -1 -1 -1 -3 -1 -1 -1 +1 that ZK is a timing estimator value, DK is a current data value, DK-1 is a previous data value, EK is a current error value, and EK-1 is a previous error value. In example 1270, the subject matter of any one or more of examples 1256-1269 optionally include determining, with a timing estimator, whether to adjust the sampling phase to an earlier point, hold it at its current point, or adjust it to a later point. Example 1271 is a computer program product comprising one or more computer readable storage media comprising computer-executable instructions operable to, when executed by processing circuitry of a device, configure the device to process in-phase (I) and quadrature (Q) channels of QAM signals received by the receiver, store a plurality of mode values in a mode table memory of the apparatus with adjustment indications, receive data from the I and Q channels, read a current mode from the mode table, and dependent on the current mode, adjust a current sampling phase of the signal consistent with the adjustment indication for the current mode. In example 1272, the subject matter of example 1271 optionally includes that the QAM supports at least four values. Example 1273 is a computer program product comprising one or more computer readable storage media comprising computer-executable instructions operable to, when executed by processing circuitry of a device, configure the device to perform any of the methods of the above method examples. Example 1274 is an apparatus for performing clock and data recover (CDR) for a wireless quadrature amplitude modulation (QAM) signal in a wireless receiver, that may comprise processing in-phase (I) and quadrature (Q) channels of QAM signals received by the receiver, storing a plurality of mode values in a mode table memory of the apparatus with adjustment indications, receiving data from the I and Q channels, reading a current mode from the mode table, and dependent on the current mode, adjusting a current sampling phase of the signal consistent with the adjustment indication for the current mode. In example 1275, the subject matter of example 1274 optionally includes that the QAM supports at least four values. In example 1276, the subject matter of example 1275 optionally includes 16-QAM. In example 1277, the subject matter of any one or more of examples 1274-1276 optionally include dynamically adjusting the current mode during operation. In example 1278, the subject matter of any one or more of examples 1274-1277 optionally include that the mode table has modes that consider only the I channel or only the Q channel. In example 1279, the subject matter of example 1278 optionally includes detecting a communication problem in either the I channel or the Q channel and utilizing a mode for a channel that the communication problem is not detected in. In example 1280, the subject matter of any one or more of examples 1274-1279 optionally include that the mode table has modes that consider both the I channel and the Q channel. In example 1281, the subject matter of any one or more of examples 1274-1280 optionally include that the mode table comprises at least eight modes defined as follows: Mode Early Out Late Out Sample Phase Decision 0 0 0 No Decision 1 1 0 Early 2 0 1 Late 3 1 1 No Decision 4 Early I Late I Bypass I 5 Early Q Late Q Bypass Q 6 Early I or Early Q Late I or Late Q I or Q 7 Early I and Early Q Late I and Late Q I and Q In example 1282, the subject matter of example 1281 optionally includes that the timing estimator determination is a function of a sign of a received data symbol and an error value. In example 1283, the subject matter of example 1282 optionally includes that the timing estimator determination is based on the following formula ZK = SIGN(DK) SIGN(DK-1) (EK - EK-1), ZK > 0 EARLY, ZK = 0 HOLD, ZK < 0 LATE. In example 1284, the subject matter of example 1283 optionally includes an estimator table used by the timing estimator comprising at least four data values, each having an associated sign and error value above and below the data value. In example 1285, the subject matter of example 1284 optionally includes that the error values above the highest data value and below the lowest data value are plus one, and all other error values are minus one. In example 1286, the subject matter of example 1285 optionally includes -QAM. In example 1287, the subject matter of example 1286 optionally includes that the estimator table comprises DK Sign(DK) EK +3 +1 +1 +1 -1 +1 +1 -1 -1 -1 -1 -1 -1 -1 -1 -3 -1 -1 -1 +1 that ZK is a timing estimator value, DK is a current data value, DK-1 is a previous data value, EK is a current error value, and EK-1 is a previous error value. In example 1288, the subject matter of any one or more of examples 1274-1287 optionally include determining, with a timing estimator, whether to adjust the sampling phase to an earlier point, hold it at its current point, or adjust it to a later point. Example 1289 is an automatic gain control (AGC) circuit for a radio-frequency (RF) receiver, comprising a processor and a memory, the processor to receive a plurality of quantized signals from a quadrature modulated signal, assign the quantized signals into regions of a constellation map made up of in-phase (I) / quadrature (Q) quantization bins according to their quantized power level, determine a maximum likelihood estimator (MLE) based on the assigned quantized signals, estimate a power based on the MLE, and adjust a variable gain amplifier for further received signals based on the estimated power. In example 1290, the subject matter of example 1289 optionally includes that the MLE is computed with the equation P ̂=〖arg (max)┬P〗⁡〖1/N ∑_(i=1)^(2^(b-2) (2^(b-1)+1))▒〖n_(r_i ) log⁡(P(r_i |P)) 〗〗 where n_(r_i ) is the number of samples out of N quantized in region r_i, b=〖log〗_2⁡(2n)bits in each of the I/Q components of a received signal, and P is the average received signal power which is computed as P=E{|h|^2}1/M ∑_(m=1)^M▒|x_m |^2 .In example 1291, the subject matter of example 1290 optionally includes that the power is estimated by solving the equation ∑_(i=1)^(2^(b-2) (2^(b-1)+1))▒〖n_(r_i )/N log⁡(P(r_i |P)) 〗≤∑_(i=1)^(2^(b-2) (2^(b-1)+1))▒〖n_(r_i )/N log⁡(n_(r_i )/N) 〗 In example 1292, the subject matter of any one or more of examples 1289-1291 optionally include that the quantized signals are signals from a low-resolution analog-to-digital converter (ADC). In example 1293, the subject matter of example 1292 optionally includes that the low-resolution ADC produces three or fewer bits. In example 1294, the subject matter of any one or more of examples 1289-1293 optionally include that the processor is further to utilize all samples from all ADCs together to allow a latency reduction. In example 1295, the subject matter of any one or more of examples 1289-1294 optionally include that the processor is further to select regions having a monotonically increasing or decreasing conditional distributions P(r_i |P), chose a set of regions from the selected regions such that r_i=〖arg max┬(r_i )〗⁡〖|dP(r_i |P)/dP|,〗 over P of interest, and solve an optimization problem min┬P⁡∑_(i∈step 2)▒|P(r_i |P)-n_(r_i )/N| ⁡ In example 1296, the subject matter of any one or more of examples 1289-1295 optionally include that the processor is further to construct a look-up table (LUT) for estimated power to use for subsequent power estimates. In example 1297, the subject matter of any one or more of examples 1289-1296 optionally include that the processor is further to utilize a dithering algorithm to determine a best power estimate solution for a specified signal-to-noise ratio (SNR) value. Example 1298 is a radio receiver device that receives quadrature modulated radio frequency (RF) signals, that may comprise a plurality of channels, each channel that may comprise an antenna that receives the quadrature modulated RF signals, a mixer that converts the quadrature modulated RF signals into an intermediate frequency (IF) signal, a variable gain amplifier (VGA) that receives the IF signal, a sample and hold circuit that samples an output of the VGA and provides a sampled output signal, and an analog-to-digital converter (ADC) that receives the sampled output signal and quantizes it into a digital signal, a processor and a memory, the processor to receive a plurality of quantized signals from a quadrature modulated signal, assign the quantized signals into regions of a constellation map made up of in-phase (I) / quadrature (Q) quantization bins according to their quantized power level, determine a maximum likelihood estimator (MLE) based on the assigned quantized signals, estimate a power based on the MLE, and adjust a variable gain amplifier for further received signals based on the estimated power. In example 1299, the subject matter of example 1298 optionally includes that the ADCs are low-resolution ADCs producing three or fewer bits. Example 1300 is a method for automatic gain control (AGC) of a radio-frequency (RF) receiver, that may comprise receiving a plurality of quantized signals from a quadrature modulated signal, assigning the quantized signals into regions of a constellation map made up of in-phase (I) / quadrature (Q) quantization bins according to their quantized power level, determining a maximum likelihood estimator (MLE) based on the assigned quantized signals, estimating a power based on the MLE, and adjusting a variable gain amplifier for further received signals based on the estimated power. In example 1301, the subject matter of example 1300 optionally includes that the MLE is computed with the equation P ̂=〖arg (max)┬P〗⁡〖1/N ∑_(i=1)^(2^(b-2) (2^(b-1)+1))▒〖n_(r_i ) log⁡(P(r_i |P)) 〗〗 where n_(r_i ) is the number of samples out of N quantized in region r_i, b=〖log〗_2⁡(2n)bits in each of the I/Q components of a received signal, and P is the average received signal power which is computed as P=E{|h|^2}1/M ∑_(m=1)^M▒|x_m |^2 In example 1302, the subject matter of example 1301 optionally includes that the power is estimated by solving the equation ∑_(i=1)^(2^(b-2) (2^(b-1)+1))▒〖n_(r_i )/N log⁡(P(r_i |P)) 〗≤∑_(i=1)^(2^(b-2) (2^(b-1)+1))▒〖n_(r_i )/N log⁡(n_(r_i )/N) 〗 In example 1303, the subject matter of any one or more of examples 1330-1302 optionally include that the quantized signals are signals from a low-resolution analog-to-digital converter (ADC). In example 1304, the subject matter of example 1303 optionally includes that the low-resolution ADC produces three or fewer bits. In example 1305, the subject matter of any one or more of examples 1300-1304 optionally include utilizing all samples from all ADCs together to allow a latency reduction. In example 1306, the subject matter of any one or more of examples 1300-1305 optionally include selecting regions having a monotonically increasing or decreasing conditional distributions P(r_i |P), choosing a set of regions from the selected regions such that r_i=〖arg max┬(r_i )〗⁡〖|dP(r_i |P)/dP|,〗 over P of interest, and solving an optimization problem min┬P⁡∑_(i∈step 2)▒|P(r_i |P)-n_(r_i )/N| ⁡ In example 1307, the subject matter of any one or more of examples 1300-1306 optionally include constructing a look-up table (LUT) for estimated power to use for subsequent power estimates. In example 1308, the subject matter of any one or more of examples 1300-1307 optionally include utilizing a dithering algorithm to determine a best power estimate solution for a specified signal-to-noise ratio (SNR) value. Example 1309 is a computer program product comprising one or more computer readable storage media comprising computer-executable instructions operable to, when executed by processing circuitry of a device, configure the device to receive a plurality of quantized signals from a quadrature modulated signal, assign the quantized signals into regions of a constellation map made up of in-phase (I) / quadrature (Q) quantization bins according to their quantized power level, determine a maximum likelihood estimator (MLE) based on the assigned quantized signals, estimate a power based on the MLE, and adjust a variable gain amplifier for further received signals based on the estimated power. In example 1310, the subject matter of example 1309 optionally includes that the MLE is computed with the equation P ̂=〖arg (max)┬P〗⁡〖1/N ∑_(i=1)^(2^(b-2) (2^(b-1)+1))▒〖n_(r_i ) log⁡(P(r_i |P)) 〗〗 where n_(r_i ) is the number of samples out of N quantized in region r_i, b=〖log〗_2⁡(2n)bits in each of the I/Q components of a received signal, and P is the average received signal power which is computed as P=E{|h|^2}1/M ∑_(m=1)^M▒|x_m |^2 Another example is a computer program product comprising one or more computer readable storage media comprising computer-executable instructions operable to, when executed by processing circuitry of a device, configure the device to perform any of the methods of examples 1300-1308. Example 1311 is a system comprising means to perform any of the methods of examples 1300-1308. Example 1312 is an automatic gain control (AGC) circuit of a radio-frequency (RF) receiver, that may comprise means for receiving a plurality of quantized signals from a quadrature modulated signal, means for assigning the quantized signals into regions of a constellation map made up of in-phase (I) / quadrature (Q) quantization bins according to their quantized power level, means for determining a maximum likelihood estimator (MLE) based on the assigned quantized signals, means for estimating a power based on the MLE, and means for adjusting a variable gain amplifier for further received signals based on the estimated power. In example 1313, the subject matter of example 1312 optionally includes means for computing the MLE with the equation P ̂=〖arg (max)┬P〗⁡〖1/N ∑_(i=1)^(2^(b-2) (2^(b-1)+1))▒〖n_(r_i ) log⁡(P(r_i |P)) 〗〗 where n_(r_i ) is the number of samples out of N quantized in region r_i, b=〖log〗_2⁡(2n)bits in each of the I/Q components of a received signal, and P is the average received signal power which is computed as P=E{|h|^2}1/M ∑_(m=1)^M▒|x_m |^2 In example 1314, the subject matter of example 1313 optionally includes means for solving the power estimation equation ∑_(i=1)^(2^(b-2) (2^(b-1)+1))▒〖n_(r_i )/N log⁡(P(r_i |P)) 〗≤∑_(i=1)^(2^(b-2) (2^(b-1)+1))▒〖n_(r_i )/N log⁡(n_(r_i )/N) 〗. In example 1315, the subject matter of any one or more of examples 1312-1314 optionally include that the quantized signals are signals from a low-resolution analog-to-digital converter (ADC). In example 1316, the subject matter of example 1315 optionally includes that the low-resolution ADC produces three or fewer bits. In example 1317, the subject matter of any one or more of examples 1312-1316 optionally include means for utilizing all samples from all ADCs together to allow a latency reduction. In example 1318, the subject matter of any one or more of examples 1312-1317 optionally include means for selecting regions having a monotonically increasing or decreasing conditional distributions P(r_i |P), means for choosing a set of regions from the selected regions such that r_i=〖arg max┬(r_i )〗⁡〖|dP(r_i |P)/dP|,〗 over P of interest, and means for solving an optimization problem min┬P⁡∑_(i∈step 2)▒|P(r_i |P)-n_(r_i )/N| ⁡. In example 1319, the subject matter of any one or more of examples 1312-1318 optionally include means for constructing a look-up table (LUT) for estimated power to use for subsequent power estimates. In example 1320, the subject matter of any one or more of examples 1312-1319 optionally include means for utilizing a dithering algorithm to determine a best power estimate solution for a specified signal-to-noise ratio (SNR) value. Example 1321 is a device for controlling an antenna array in a phased array transceiver, that may comprise a plurality of transceiver slices, each that may comprise an antenna element forming a part of an antenna array of the device, a transmit and receive switch that is switchable between a transmit mode (TM) and a receive mode (RM) of operation, a receive path comprising a variable low noise amplifier and phase shifter, the receive path connectable to the antenna element in the RM, and, a transmit path comprising a variable power amplifier and phase shifter, the transmit path connectable to the antenna in the TM, a gain table that contains gain adjustment values that map to a number of or configuration of active antenna elements, a processor to configure the gain table for minimum current drain settings of the antenna array, and, in the RM perform automatic gain control using the gain table, and determine when an interferer is present, and when present, configure the gain table for a narrower beam width setting of the antenna array and return to perform the automatic gain control, when not present, return to configure the gain table for minimum current drain settings of the antenna array. In example 1322, the subject matter of example 1321 optionally includes that the processor is further to, in the TM perform a power control using the gain table, determine if co-existence with other signals or interference from other signals is present, when co-existence or interference is present, the processor is further to configure the gain table for narrower beam width settings of the antenna array, and return to perform the power control, when co-existence and interference are not present, the processor is further to determine when there is a network request for a narrower beam width, when the network request is true, the processor is further to return to the configure the gain table for narrower beam width settings of the antenna array, and when the network request is not true, the processor is further to return to the configure the gain table for minimum current drain settings of the antenna array. In example 1323, the subject matter of any one or more of examples 1321-1322 optionally include that the receive path is connectable to a combiner and the transmit path is connectable to a splitter. In example 1324, the subject matter of any one or more of examples 1321-1323 optionally include that the processor is further to determine if a received signal value exceeds a predefined value, when true, the processor is further to return to the configure the gain table for minimum current drain settings of the antenna array. In example 1325, the subject matter of example 1324 optionally includes that the received signal value is a received signal strength indicator (RSSI). In example 1326, the subject matter of any one or more of examples 1321-1325 optionally include that the determination of when an interference is present is made by the processor to perform a wideband and narrowband detection and compare respective results. In example 1327, the subject matter of any one or more of examples 1322-1326 optionally include that the processor is further configured to determine if a user proximity condition is satisfied, and when the condition is satisfied, return to configure the gain table for a narrower beam width setting of the antenna array. In example 1328, the subject matter of example 1327 optionally includes that the proximity condition is that the direction of communications is away from the user. In example 1329, the subject matter of example 1328 optionally includes that the proximity condition further includes a distance of the user from the device. In example 1330, the subject matter of any one or more of examples 1321-1329 optionally include that the processor is further configured to determine a speed of the device relative to another device it is communicating with, and when the speed is below a predefined threshold, return to configure the gain table for a narrower beam width setting of the antenna array. In example 1331, the subject matter of any one or more of examples 1321-1330 optionally include that the device is a base station in a cellular telephone network. In example 1332, the subject matter of any one or more of examples 1321-1331 optionally include an omni-directional antenna forming a part of the antenna array. In example 1333, the subject matter of any one or more of examples 1321-1332 optionally include that the antenna elements are arranged in a rectangular configuration. Example 1334 is a method for controlling an antenna array in a phased array transceiver, that may comprise switching a transmit and receive switch that is switchable between a transmit mode (TM) and a receive mode (RM) of operation, amplifying and phase shifting a signal in a receive path with a variable low noise amplifier and phase shifter, the receive path connectable to the antenna element in the RM, and, amplifying and phase shifting a signal in a transmit path comprising a variable power amplifier and phase shifter, the transmit path connectable to the antenna in the TM, storing gain adjustment values in a gain table that map to a number of or configuration of active antenna elements, configuring the gain table for minimum current drain settings of the antenna array, and, in the RM performing automatic gain control using the gain table, and determining when an interferer is present, and when present, configuring the gain table for a narrower beam width setting of the antenna array and returning to perform the automatic gain control, when not present, returning to configure the gain table for minimum current drain settings of the antenna array. In example 1335, the subject matter of example 1334 optionally includes that the processor is further to, in the TM performing a power control using the gain table, determining if co-existence with other signals or interference from other signals is present, when co-existence or interference is present configuring the gain table for narrower beam width settings of the antenna array, and returning to perform the power control, when co-existence and interference are not present determining when there is a network request for a narrower beam width, when the network request is true, returning to the configuring of the gain table for narrower beam width settings of the antenna array, and when the network request is not true, returning to the configuring the gain table for minimum current drain settings of the antenna array. In example 1336, the subject matter of any one or more of examples 1334-1335 optionally include that the receive path is connectable to a combiner and the transmit path is connectable to a splitter. In example 1337, the subject matter of any one or more of examples 1334-1336 optionally include determining if a received signal value exceeds a predefined value, when true, returning to the configure the gain table for minimum current drain settings of the antenna array. In example 1338, the subject matter of example 1337 optionally includes that the received signal value is a received signal strength indicator (RSSI). In example 1339, the subject matter of any one or more of examples 1334-1338 optionally include that the determination of when an interference is present is made by the processor to perform a wideband and narrowband detection and compare respective results. In example 1340, the subject matter of any one or more of examples 1335-1339 optionally include determining if a user proximity condition is satisfied, and when the condition is satisfied, returning to configure the gain table for a narrower beam width setting of the antenna array. In example 1341, the subject matter of example 1340 optionally includes that the proximity condition is that the direction of communications is away from the user. In example 1342, the subject matter of example 1341 optionally includes that the proximity condition further includes a distance of the user from the device. In example 1343, the subject matter of any one or more of examples 1334-1342 optionally include determining a speed of the device relative to another device it is communicating with, and when the speed is below a predefined threshold, returning to configure the gain table for a narrower beam width setting of the antenna array. In example 1344, the subject matter of any one or more of examples 1334-1343 optionally include that the device is a base station in a cellular telephone network. In example 1345, the subject matter of any one or more of examples 1334-1344 optionally include an omni-directional antenna forming a part of the antenna array. In example 1346, the subject matter of any one or more of examples 1334-1345 optionally include that the antenna elements are arranged in a rectangular configuration. Example 1347 is a computer program product comprising one or more computer readable storage media comprising computer-executable instructions operable to, when executed by processing circuitry of a device, configure the device to switch a transmit and receive switch that is switchable between a transmit mode (TM) and a receive mode (RM) of operation, amplify and phase shifting a signal in a receive path with a variable low noise amplifier and phase shifter, the receive path connectable to the antenna element in the RM, and, amplify and phase shifting a signal in a transmit path comprising a variable power amplifier and phase shifter, the transmit path connectable to the antenna in the TM, store gain adjustment values in a gain table that map to a number of or configuration of active antenna elements, configure the gain table for minimum current drain settings of the antenna array, and, in the RM perform automatic gain control using the gain table, and determine when an interferer is present, and when present, configure the gain table for a narrower beam width setting of the antenna array and return to perform the automatic gain control, when not present, return to configure the gain table for minimum current drain settings of the antenna array. In example 1348, the subject matter of example 1347 optionally includes that the instructions are further operable to, in the TM perform a power control using the gain table, determine if co-existence with other signals or interference from other signals is present, when co-existence or interference is present configure the gain table for narrower beam width settings of the antenna array, and return to perform the power control, when co-existence and interference are not present determine when there is a network request for a narrower beam width, when the network request is true, return to the configuring of the gain table for narrower beam width settings of the antenna array, and when the network request is not true, return to the configuring the gain table for minimum current drain settings of the antenna array. Example 1349 is a computer program product comprising one or more computer readable storage media comprising computer-executable instructions operable to, when executed by processing circuitry of a device, configure the device to perform any of the methods of examples 1334-1346. Example 1350 is a system comprising means to perform any of the methods of examples 1334-1346. Example 1351 is a digital-to-analog circuit device, that may comprise a first component comprising a current source and at least two switchable paths for the current source to drain, that a voltage reference at a voltage reference point associated with the paths is dependent upon a number of the paths switched on, and a second component comprising at least two switchable paths, that an output associated with the second component is dependent upon a second number of paths switch on and the voltage reference point, that the voltage reference point connects the first component to the second component. In example 1352, the subject matter of example 1351 optionally includes that the first component paths each comprise a transistor having their gates connected to the voltage reference point. In example 1353, the subject matter of example 1352 optionally includes that the first component paths each have a second transistor as a switch connected in series with the transistor between the current source and the transistor. In example 1354, the subject matter of any one or more of examples 1351-1353 optionally include that the voltage reference point comprises a switch that switchably connects the first component to the second component. In example 1355, the subject matter of any one or more of examples 1351-1354 optionally include that each path of the second component comprises a transistor having a gate connected to the voltage reference point. In example 1356, the subject matter of example 1355 optionally includes that each path of the second component further comprises a second transistor in series between the output and the transistor that acts as a switch to engage the path. In example 1357, the subject matter of any one or more of examples 1351-1356 optionally include that a voltage at the voltage reference point is V/N, where N is the number of paths in the first component and V is a voltage at the reference point when only one path is active. Example 1358 is a method of operating a digital-to-analog circuit device, that may comprise in a first component providing at least two switchable paths, running current from a current source through the at least two switchable paths to establish a reference voltage at a reference voltage point that is dependent upon a number of the paths switched on, and in a second component providing at least two switchable paths, that an output associated with the second component is dependent upon a second number of paths switch on and the voltage reference point, that the voltage reference point connects the first component to the second component. In example 1359, the subject matter of example 1358 optionally includes that the first component paths each comprise a transistor having their gates connected to the voltage reference point. In example 1360, the subject matter of example 1359 optionally includes that the first component paths each have a second transistor as a switch connected in series with the transistor between the current source and the transistor. In example 1361, the subject matter of any one or more of examples 1358-1360 optionally include that the voltage reference point comprises a switch that switchably connects the first component to the second component. In example 1362, the subject matter of any one or more of examples 1358-1361 optionally include that each path of the second component comprises a transistor having a gate connected to the voltage reference point. In example 1363, the subject matter of example 1362 optionally includes that each path of the second component further comprises a second transistor in series between the output and the transistor that acts as a switch to engage the path. In example 1364, the subject matter of any one or more of examples 1358-1363 optionally include that a voltage at the voltage reference point is V/N, where N is the number of paths in the first component and V is a voltage at the reference point when only one path is active. Example 1365 is a system comprising means to perform any of the methods of examples 1358-1364. Example 1366 is a method of operating a digital-to-analog circuit device, that may comprise in a first component providing at least two switchable paths, means for running current from a current source through the at least two switchable paths to establish a reference voltage at a reference voltage point that is dependent upon a number of the paths switched on, and in a second component providing at least two switchable paths, that an output associated with the second component is dependent upon a second number of paths switch on and the voltage reference point, that the voltage reference point connects the first component to the second component. In example 1367, the subject matter of example 1366 optionally includes that the first component paths each comprise a transistor having their gates connected to the voltage reference point. In example 1368, the subject matter of example 1367 optionally includes that the first component paths each have a second transistor as a switch connected in series with the transistor between the current source and the transistor. In example 1369, the subject matter of any one or more of examples 1366-1368 optionally include that the voltage reference point comprises a means that switchably connects the first component to the second component. In example 1370, the subject matter of any one or more of examples 1366-1369 optionally include that each path of the second component comprises a transistor having a gate connected to the voltage reference point. In example 1371, the subject matter of example 1370 optionally includes that each path of the second component further comprises a second transistor in series between the output and the transistor that acts as a means to engage the path. In example 1372, the subject matter of any one or more of examples 1366-1371 optionally include that a voltage at the voltage reference point is V/N, where N is the number of paths in the first component and V is a voltage at the reference point when only one path is active. Example 1373 is a mixed signal feedforward feedback polarizer equalizer (MSFFPE) device for a radio frequency receiver device, that may comprise inputs connectable to an in-phase (I) signal line and a quadrature (Q) signal line on a digital side of the receiver, filter and processing elements that operate on input signals at the inputs, and outputs connectable to an I signal line and a Q signal line on an analog side of the receiver. In example 1374, the subject matter of example 1373 optionally includes that the I and Q signal lines on the digital side and analog side of the receiver each comprise a vertical component VI and VQ, and a horizontal component. HI and HQ. In example 1375, the subject matter of example 1374 optionally includes that the filtering and processing elements comprise circuitry to reduce crosstalk between the VI and HI signal lines, between the VI and HQ signal lines, between the VQ and HI signal lines, and between the VQ and HQ signal lines. In example 1376, the subject matter of any one or more of examples 1373-1375 optionally include that the filtering and processing elements comprise circuitry to reduce crosstalk between the I and Q signal lines. In example 1377, the subject matter of any one or more of examples 1373-1376 optionally include that the filter and processing elements comprise a digital delay and summer circuitry. In example 1378, the subject matter of any one or more of examples 1373-1377 optionally include that the filter and processing elements comprise resettable capacitors having an output capacitor voltage is resettable by a reset clock signal. In example 1379, the subject matter of example 1378 optionally includes that the capacitors integrate charge during an integration clock period. In example 1380, the subject matter of any one or more of examples 1373-1379 optionally include that the filter and processing elements further comprise an op amp that provides common mode feedback related to boost device for bandwidth enhancement and offset cancelation. In example 1381, the subject matter of example 1380 optionally includes feedback taps and a decision feedback equalizer (DFE) input. Example 1382 is a method for operating a mixed signal feedforward feedback polarizer equalizer (MSFFPE) device for a radio frequency receiver device, that may comprise receiving digital signals to inputs connectable to an in-phase (I) signal line and a quadrature (Q) signal line on a digital side of the receiver, filtering and processing the received digital signals with filter and processing elements, and outputting analog signals at outputs connectable to an I signal line and a Q signal line on an analog side of the receiver. In example 1383, the subject matter of example 1382 optionally includes that the I and Q signal lines on the digital side and analog side of the receiver each comprise a vertical component VI and VQ, and a horizontal component. HI and HQ. In example 1384, the subject matter of example 1383 optionally includes utilizing the filtering and processing elements to reduce crosstalk between the VI and HI signal lines, between the VI and HQ signal lines, between the VQ and HI signal lines, and between the VQ and HQ signal lines. In example 1385, the subject matter of any one or more of examples 1382-1384 optionally include utilizing the filtering and processing elements to reduce crosstalk between the I and Q signal lines. In example 1386, the subject matter of any one or more of examples 1382-1385 optionally include that the filter and processing elements comprise a digital delay and summer circuitry. In example 1387, the subject matter of any one or more of examples 1382-1386 optionally include that the filter and processing elements comprise resettable capacitors having an output capacitor voltage is resettable by a reset clock signal. In example 1388, the subject matter of example 1387 optionally includes that the capacitors integrate charge during an integration clock period. In example 1389, the subject matter of any one or more of examples 1382-1388 optionally include that the filter and processing elements further comprise an op amp that provides common mode feedback related to boost device for bandwidth enhancement and offset cancelation. In example 1390, the subject matter of example 1389 optionally includes feedback taps and a decision feedback equalizer (DFE) input. Example 1391 is a system comprising means to perform any of the methods of examples 1382-1390. Example 1392 is a device for operating a mixed signal feedforward feedback polarizer equalizer (MSFFPE) device for a radio frequency receiver device, that may comprise means for receiving digital signals to inputs connectable to an in-phase (I) signal line and a quadrature (Q) signal line on a digital side of the receiver, means for filtering and processing the received digital signals with filter and processing elements, and means for outputting analog signals at outputs connectable to an I signal line and a Q signal line on an analog side of the receiver. In example 1393, the subject matter of example 1392 optionally includes that the I and Q signal lines on the digital side and analog side of the receiver each comprise a vertical component VI and VQ, and a horizontal component. HI and HQ. In example 1394, the subject matter of example 1393 optionally includes utilizing the filtering and processing elements to reduce crosstalk between the VI and HI signal lines, between the VI and HQ signal lines, between the VQ and HI signal lines, and between the VQ and HQ signal lines. In example 1395, the subject matter of any one or more of examples 1392-1394 optionally include utilizing the filtering and processing elements to reduce crosstalk between the I and Q signal lines. In example 1396, the subject matter of any one or more of examples 1392-1395 optionally include that the filter and processing elements comprise a digital delay and summer circuitry. In example 1397, the subject matter of any one or more of examples 1392-1396 optionally include that the filter and processing elements comprise resettable capacitors having an output capacitor voltage is resettable by a reset clock signal. In example 1398, the subject matter of example 1397 optionally includes that the capacitors integrate charge during an integration clock period. In example 1399, the subject matter of any one or more of examples 1392-1398 optionally include that the filter and processing elements further comprise means for common mode feedback related to boost device for bandwidth enhancement and offset cancelation. In example 1400, the subject matter of example 1399 optionally includes feedback taps and a decision feedback equalizer (DFE) input. Example 1401 includes an apparatus comprising a bidirectional amplifier, the bidirectional amplifier comprising a first amplifier to amplify a Transmit (Tx) signal to provide an amplified Tx signal at a Tx mode; a second amplifier to amplify a Receive (Rx) signal to provide an amplified Rx signal at an Rx mode; a first transformer to provide the Tx signal from a first input/output to the first amplifier at the Tx mode, and to output the amplified Rx signal from the second amplifier at the first input/output at the Rx mode; a second transformer to provide the Rx signal from a second input/output to the second amplifier at the Rx mode, and to output the amplified Tx signal from the first amplifier at the second input/output at the Tx mode; and a plurality of switches to, at the Tx mode, switch a plurality of activating voltages to the first amplifier and a plurality of deactivating voltages to the second amplifier, the plurality of switches to, at the Rx mode, switch the plurality of activating voltages to the second amplifier and the plurality of deactivating voltages to the first amplifier. In one example, the apparatus of Example 1401 may include, for example, one or more additional elements, for example, a bi-directional splitter/combiner, a bi-directional mixer, PA, an LNA, one or more switches, one or more mixers, an I/Q generator, and/or one or more phase shifters, e.g., as described below with respect to Examples 1422, 1440, 1454, 1465, 1476, 1487, 1500, 1513, 1526, 1538, and/or 1551. Example 1402 includes the subject matter of Example 1401, and optionally, wherein the plurality of activating voltages comprises a drain voltage to be applied to at least one drain of the first amplifier at the Tx mode, and to be applied to at least one drain of the second amplifier at the Rx mode. Example 1403 includes the subject matter of Example 1402, and optionally, wherein the plurality of deactivating voltages comprises a source voltage to be applied to the at least one drain of the second amplifier at the Tx mode, and to be applied to the at least one drain of the first amplifier at the Rx mode. Example 1404 includes the subject matter of Example 1402 or 1403, and optionally, wherein the plurality of switches comprises a first switch to switch the at least one drain of the second amplifier between the drain voltage at the Tx mode, and a source voltage at the Rx mode; and a second switch to switch the at least one drain of the first amplifier between the source voltage at the Tx mode and the drain voltage at the Rx mode. Example 1405 includes the subject matter of any one of Examples Example 1402-1404, and optionally, wherein the bidirectional amplifier comprises a first capacitor to provide the Tx signal from the first transformer to a first input of the first amplifier; a second capacitor to provide the Tx signal from the first transformer to a second input of the first amplifier; a third capacitor to provide the Rx signal from the second transformer to a first input of the second amplifier; and a fourth capacitor to provide the Rx signal from the second transformer to a second input of the second amplifier Example 1406 includes the subject matter of any one of Examples 1402-1405, and optionally, wherein at least one amplifier of the first and second amplifiers comprises a common source Negative Metal Oxide Semiconductor (NMOS) Field Effect Transistor (FET). Example 1407 includes the subject matter of Example 1401, and optionally, wherein the plurality of activating voltages comprises a drain voltage to be applied to at least one drain of the first amplifier at the Tx mode, and to be applied to at least one drain of the second amplifier at the Rx mode; a bias voltage to be applied to at least one gate of the first amplifier at the Tx mode, and to be applied to at least one gate of the second amplifier at the Rx mode; and a source voltage to be applied to at least one source of the of the first amplifier at the Tx mode, and to be applied to at least one source of the of the second amplifier at the Rx mode. Example 1408 includes the subject matter of Example 1407, and optionally, wherein the plurality of deactivating voltages comprises the drain voltage to be applied to the at least one gate of the second amplifier at the Tx mode, and to be applied to the at least one gate of the first amplifier at the Rx mode; and the bias voltage to be applied to the at least one source of the second amplifier at the Tx mode, and to be applied to the at least one source of the first amplifier at the Rx mode. Example 1409 includes the subject matter of Example 1407 or 1408, and optionally, wherein the plurality of switches comprises a first switch to switch the at least one drain of the second amplifier and the at least one gate of the first amplifier between the drain voltage at the Tx mode and the bias voltage at the Rx mode; a second switch to switch the at least one source of the first amplifier between the bias voltage at the Tx mode and the source voltage at the Rx mode; a third switch to switch the at least one source of the second amplifier between the source voltage at the Tx mode and the bias voltage at the Rx mode; and a fourth switch to switch the at least one drain of the second amplifier and the at least one gate of the first amplifier between the bias voltage at the Tx mode, and the drain voltage at the RX mode. Example 1410 includes the subject matter of Example 1401, and optionally, wherein the plurality of activating voltages comprises a drain voltage to be applied to at least one source of the first amplifier at the Tx mode, and to be applied to at least one drain of the second amplifier at the Rx mode; a source voltage to be applied to at least one drain of the first amplifier at the Tx mode, and to be applied to at least one source of the second amplifier at the Rx mode; a first bias voltage to be applied to at least one gate of the first amplifier at the Tx mode; and a second bias voltage to be applied to at least one gate of the second amplifier at the Rx mode. Example 1411 includes the subject matter of Example 1410, and optionally, wherein the plurality of deactivating voltages comprises the first bias voltage to be applied to the at least one drain of the second amplifier and to the at least one source of the second amplifier at the Tx mode; and the second bias voltage to be applied to the at least one drain of the first amplifier at the Tx mode, and to the at least one source of the first amplifier at the Rx mode. Example 1412 includes the subject matter of any one of Example 1410 or 1411, and optionally, wherein the plurality of switches comprises a first switch to switch the at least one drain of the second amplifier and the at least one gate of the first amplifier between a source voltage at the Tx mode and the second bias voltage at the Rx mode; a second switch to switch the at least one source of the first amplifier between the first bias voltage at the Tx mode and the source voltage at the Rx mode; a third switch to switch the at least one source of the second amplifier between the drain voltage at the Tx mode and the second bias voltage at the Rx mode; and a fourth switch to switch the at least one drain of the first amplifier and the at least one gate of the second amplifier between the first bias voltage at the Tx mode and the drain voltage at the Rx mode. Example 1413 includes the subject matter of any one of Examples 1410-1412, and optionally, wherein the first amplifier comprises one or more Positive Metal Oxide Semiconductor (PMOS) FETs, and the second amplifier comprises one or more Negative Metal Oxide Semiconductor (NMOS) FET. Example 1414 includes the subject matter of any one of Examples 1401-1413 comprising control circuitry to provide a plurality of control signals to controllably switch the plurality of switches between the first amplifier and the second amplifier based on the Tx mode or the Rx mode. Example 1415 includes the subject matter of any one of Examples 1401-1414, and optionally, wherein the first amplifier comprises a Power Amplifier (PA), and the second amplifier comprises a Low Noise Amplifier (LNA). Example 1416 includes the subject matter of any one of Examples 1401-1415, and optionally, wherein the first amplifier comprises a first common source Filed Effect Transistor (FET) pair, and the second amplifier comprises a second common source Filed Effect Transistor (FET) pair. Example 1417 includes the subject matter of any one of Examples 1401-1416 comprising a transceiver configured to transmit the Tx signal and to receive the Rx signal. Example 1418 includes the subject matter of Example 1417, and optionally, wherein the transceiver comprises a fifth generation (5G) cellular transceiver. Example 1419 includes the subject matter of Example 1417, and optionally, wherein the transceiver comprises a 60 Gigahertz (GHz) transceiver configured to transmit the Tx signal and to receive the Rx signal over a 60 GHz frequency band. Example 1420 includes the subject matter of any one of Examples 1417-1419, and optionally, wherein the transceiver comprises a half-duplex transceiver. Example 1421 includes the subject matter of any one of Examples 1401-1420 comprising one or more phase array antennas. Example 1422 includes an apparatus comprising an active bi-directional splitter/combiner (ABDSC) switchable between a combiner mode and a splitter mode, the ABDSC comprising a plurality of antenna interfaces to receive, at the combiner mode, a plurality of Receive (Rx) signals from a respective plurality of antenna ports, and to output, at the splitter mode, a plurality of Transmit (Tx) signals to the respective plurality of antenna ports; and a transformer to operably couple the ABDSC to amplification circuitry, the transformer configured to transfer, at the splitter mode, a Tx signal from the amplification circuitry to the plurality of antenna interfaces, and to combine, at the combiner mode, the plurality of Rx signals into a combined Rx signal and provide the combined Rx signal to the amplification circuitry. In one example, the apparatus of Example 1422 may include, for example, one or more additional elements, for example, a bi-directional amplifier, a bi-directional mixer, PA, an LNA, one or more switches, one or more mixers, an I/Q generator, and/or one or more phase shifters, e.g., as described with respect to Examples 1401, 1440, 1454, 1465, 1476, 1487, 1501, 1513, 1526, 1538, and/or 1551. Example 1423 includes the subject matter of Example 1422 comprising controller circuitry to controllably switch the ABDSC between the splitter mode and the combiner mode. Example 1424 includes the subject matter of Example 1422 or 1423, and optionally, wherein an antenna interface of the plurality of antenna interfaces comprises a first transistor pair in a cascode connection to be activated at the splitter mode and deactivated at the combiner mode, by a transistor of the first transistor pair; and a second transistor pair in a cascode connection to be activated at the combiner mode and deactivated at the splitter mode, by a transistor of the second transistor pair. Example 1425 includes the subject matter of Example 1424, and optionally, wherein the first transistor pair comprises a first pair of Field Effect Transistors (FETs), and the second transistor pair comprises a second pair of FETs. Example 1426 includes the subject matter of Example 1422 or 1423, and optionally, wherein an antenna interface of the plurality of antenna interfaces comprises a first transistor having a common source connection to be activated at the combiner mode and to be deactivated at the splitter mode; and a second transistor having a common source connection to be activated at the splitter mode and to be deactivated at the combiner mode. Example 1427 includes the subject matter of Example 1426, and optionally, wherein the first transistor and the second transistor comprise Field Effect Transistors (FETs). Example 1428 includes the subject matter of Example 1422 or 1423, and optionally, wherein an antenna interface of the plurality of antenna interfaces comprises a transistor having a common gate connection to receive, at the splitter mode, a source voltage (Vs) at a source of the transistor and a gate voltage (Vg) at a gate of the transistor, and to receive, at the combiner mode, a drain voltage (Vd) at the source of the transistor and the source voltage Vs at the gate of the transistor. Example 1429 includes the subject matter of Example 1428, and optionally, wherein the transistor comprises a Field Effect Transistor (FET). Example 1430 includes the subject matter of Example 1422 or 1423, and optionally, wherein an antenna interface of the plurality of antenna interfaces comprises a first transistor having a common gate connection to be activated at the combiner mode and to be deactivated at the splitter mode; and a second transistor having a common source connection to be activated at the splitter mode and to be deactivated at the combiner mode. Example 1431 includes the subject matter of Example 1430, and optionally, wherein the first transistor and the second transistor comprise Field Effect Transistors (FETs). Example 1432 includes the subject matter of any one of Examples 1422-1431, and optionally, wherein the plurality of antenna interfaces comprises at least four antenna interfaces. Example 1433 includes the subject matter of any one of Examples 1422-1432 comprising the amplification circuitry, the amplification circuitry comprising a bidirectional amplifier to amplify the combined Rx signal into an amplified Rx signal, and to generate the Tx signal by amplifying an upconverted Tx signal; a mixer to upconvert an Intermediate Frequency (IF) Tx signal into the upconverted Tx signal, and to downconvert the amplified Rx signal into an IF Rx signal; and an IF sub-system to generate a first digital signal based on the IF Rx signal, and to generate the IF Tx signal based on a second digital signal. Example 1434 includes the subject matter of Example 1433 comprising controller circuitry to controllably switch the ABDSC between the splitter mode and the combiner mode, the controller circuitry to control, cause and/or trigger the bidirectional amplifier to amplify the upconverted Tx signal, when the ABDSC is at the splitter mode, and to control, cause and/or trigger the bidirectional amplifier to amplify the combined Rx signal, when the ABDSC is at the combiner mode. Example 1435 includes the subject matter of any one of Examples 1422-1434 comprising a transceiver configured to transmit the Tx signals and to receive the Rx signals. Example 1436 includes the subject matter of Example 1435, and optionally, wherein the transceiver comprises a 60 Gigahertz (GHz) transceiver configured to transmit the Tx signals and to receive the Rx signals over a 60 GHz frequency band. Example 1437 includes the subject matter of Example 1435 or 1436, and optionally, wherein the transceiver comprises a half-duplex transceiver. Example 1438 includes the subject matter of any one of Examples 1435-1437 comprising a fifth generation (5G) cellular transceiver. Example 1439 includes the subject matter of any one of Examples 1422-1438 comprising one or more phase array antennas. Example 1440 includes an apparatus comprising a digital power amplifier (PA) to controllably amplify and modulate an input signal based on a digital control signal, the digital PA comprising a plurality of stacked gate controlled amplifiers, controllable by the digital control signal, to provide a plurality of amplified modulated signals, a stacked gate control amplifier of the plurality of stacked gate controlled amplifiers comprising a first input to receive the input signal, a second input to receive the digital control signal, and an output to provide an amplified modulated signal of the plurality of amplified modulated signals; and a combiner to combine the plurality of amplified modulated signals into a combiner output signal having an output power level and a modulation, which are based on the digital control signal. In one example, the apparatus of Example 1440 may include, for example, one or more additional elements, for example, a bi-directional amplifier, a bi-directional mixer, a bi-directional splitter/combiner, a PA, an LNA, one or more switches, one or more mixers, an I/Q generator, and/or one or more phase shifters, e.g., as described with respect to Examples 1401, 1422, 1454, 1465, 1476, 1487, 1500, 1513, 1526, 1538, and/or 1551. Example 1441 includes the subject matter of one Example 1440, and optionally, wherein the stacked gate controlled amplifier comprises a first transistor to provide the amplified modulated signal by amplifying and modulating the input signal based on the digital control signal; and a second transistor to digitally control a gate of the first transistor based on the digital control signal. Example 1442 includes the subject matter of Example 1440 or 1441, and optionally, wherein the second transistor is configured to switch the stacked gate controlled amplifier between an On state and an Off state based on a bit value of the digital control signal. Example 1443 includes the subject matter of any one of Examples 1440-1442, and optionally, wherein the first transistor comprises a first filed effect transistor (FET), and the second transistor comprises a second FET. Example 1444 includes the subject matter of any one of Examples 1440-1443, and optionally, wherein the first transistor is configured to amplify the input signal by a factor of two based on a bit of the digital control signal. Example 1445 includes the subject matter of any one of Examples 1440-1444, and optionally, wherein the digital PA is to modulate the input signal based on the digital control signal according to a modulation scheme. Example 1446 includes the subject matter of any one of Examples 1440-1445, and optionally, wherein the modulation scheme comprises a Quadrature amplitude modulation (QAM) scheme. Example 1447 includes the subject matter of Example 1446, and optionally, wherein the QAM scheme comprises a 64 QAM scheme. Example 1448 includes the subject matter of any one of Examples 1440-1447, and optionally, wherein the digital signal comprises 6 bits. Example 1449 includes the subject matter of any one of Examples 1440-1448, and optionally, wherein the plurality of stacked gate controlled amplifiers comprises six stacked gate controlled amplifiers. Example 1450 includes the subject matter of any one of Examples 1440-1449 comprising a phase modulator to provide the input signal to the digital PA based on phase data; and a baseband to provide the digital control signal to the digital PA based on the phase data. Example 1451 includes the subject matter of any one of Examples 1440-1450 comprising a millimeter wave transmitter to transmit the combiner output signal. Example 1452 includes the subject matter of any one of Examples 1440-1451 comprising one or more phase array antennas operably coupled to the digital PA. Example 1453 includes the subject matter of any one of Examples 1440-1452 comprising one or more antennas operably coupled to the digital PA. Example 1454 includes an apparatus comprising a two-stage Doherty amplifier, the two-stage Doherty amplifier comprising at least one driver amplifier to amplify a driver amplified input signal to provide a driver radio frequency (RF) signal at a first stage; at least one main amplifier to amplify the driver RF signal to provide a main amplifier signal at a second stage; at least one controllable peaking amplifier to be turned to an On state based on a level of the driver RF signal and, at the On state, to amplify the driver RF signal to provide a peaking amplifier signal; and a sub-quarter wavelength (SQWL) balun to combine the main amplifier signal with the peaking amplifier signal, the SQWL balun comprising a first transmission line to match an impedance between at least one output of the at least one driver amplifier, at least one input of the at least one main amplifier, and at least one input of the at least one controllable peaking amplifier, the SQWL balun comprising a second transmission line to match an impedance between at least one output of the at least one main amplifier and at least one output of the at least one controllable peaking amplifier. In one example, the apparatus of Example 1454 may include, for example, one or more additional elements, for example, a bi-directional amplifier, a bi-directional mixer, a bi-directional splitter/combiner, a PA, an LNA, one or more switches, one or more mixers, an I/Q generator, and/or one or more phase shifters, e.g., as described with respect to Examples 1401, 1422, 1440, 1465, 1476, 1487, 1500, 1513, 1526, 1538, and/or 1551. Example 1455 includes the subject matter of Example 1454, and optionally, wherein the SQWL balun comprises a third transmission line having a first impedance, and a plurality of stubs, each stub of the plurality of stubs having a second impedance, the plurality of stubs to operably couple at least one input of the at least one driver amplifier to the third transmission line, to operably couple the at least one output of the at least one driver amplifier to the first transmission line, to operably couple the at least one input of the at least one main amplifier to the first transmission line, to operably couple at least one input of the at least one controllable peaking amplifier to the first transmission line, to operably couple at least one output of the at least one main amplifier to the second transmission line, and to operably couple at least one output of the at least one controllable peaking amplifier to the second transmission line. Example 1456 includes the subject matter of Example 1455, and optionally, wherein the first impedance is about 50 Ohm and the second impedance is about 25 Ohm. Example 1457 includes the subject matter of Example 1455 or 1456, and optionally, wherein a length of the stub is based on about one eighth of a wavelength of the driver RF signal. Example 1458 includes the subject matter of any one of Examples 1455-1457, and optionally, wherein the second transmission line and the plurality of stubs are configured to provide a serial load at the at least one output of the at least one main amplifier, and at the at least one output of the at least one controllable peaking amplifier. Example 1459 includes the subject matter of any one of Examples 1455-1458, and optionally, wherein the at least one driver amplifier comprises a first matching network comprising a first input operably coupled to a first stub of the plurality of stubs; a second matching network comprising a second input operably coupled to a second stub of the plurality of stubs, the first matching network and the second matching network to match impedances of the first stub and second stubs with an impedance of the third transmission line; a first power amplifier comprising a first input operably coupled to a first output of the first matching network and a first output operably coupled to a third stub of the plurality of stubs; and a second power amplifier comprising a second input operably coupled to a second output of the second matching network, and a second output operably coupled to a fourth stub of the plurality of stubs, the third and fourth stubs to match an impedance between the first and second outputs of the first and second power amplifiers and the first transmission line. Example 1460 includes the subject matter of any one of Examples 1455-1459, and optionally, wherein the at least one main amplifier comprises a first matching network comprising a first input operably coupled to a first stub of the plurality of stubs; a second matching network comprising a second input operably coupled to a second stub of the plurality of stubs, the first matching network and the second matching network to match impedances of the first and second stubs with an impedance of the first transmission line; and a first power amplifier comprising a first input operably coupled to a first output of the first matching network and a first output operably coupled to a third stub of the plurality of stubs; and a second power amplifier comprising a second input operably coupled to a second output of the second matching network, and a second output operably coupled to a fourth stub of the plurality of stubs, the third and fourth stubs to match an impedance between the first and second outputs of the first and second power amplifiers and the second transmission line. Example 1461 includes the subject matter of any one of Examples 1455-1460, and optionally, wherein the at least one controllable peaking amplifier comprises a first matching network comprising a first input operably coupled to a first stub of the plurality of stubs; a second matching network comprising a second input operably coupled to a second stub of the plurality of stubs, the first and second matching networks to match impedances of the first and second stubs with an impedance of the first transmission line; a first power amplifier comprising a first input operably coupled to a first output the first matching network and a first output operably coupled to a third stub of the plurality of stubs; and a second power amplifier comprising a second input operably coupled to a second output of the second matching network, and a second output operably coupled to a fourth stub of the plurality of stubs, the third and fourth stubs to match an impedance between the first and second outputs of the first and second power amplifiers and the second transmission line. Example 1462 includes the subject matter of any one of Examples 1454-1461 comprising a local oscillator (LO) to generate a LO signal; In-phase (I) mixer circuitry to generate an I signal based on the LO signal; Quadrature-phase mixer circuitry to generate a Q signal based on the LO signal; and combiner circuitry to combine the I signal and the Q signal into the driver amplified input signal Example 1463 includes the subject matter of any one of Examples 1454-1462 comprising one or more phase array antennas operably coupled to the two-stage Doherty amplifier. Example 1464 includes the subject matter of any one of Examples 1454-1463 comprising one or more antennas operably coupled to the two-stage Doherty amplifier. Example 1465 includes an apparatus comprising an in phase (I) quadrature phase (Q) (I/Q) generator, the I/ Q generator comprising a local oscillator (LO) to generate a LO signal; a first controllable phase modulation chain to, at a Transmit (Tx) mode, generate a phase modulated Tx signal based on the LO signal, and to, at a Receive (Rx) mode, generate a phase modulated I signal based on the LO signal; a second controllable phase modulation chain to generate, at the Rx mode, a phase modulated Q signal based on the LO signal; and mixer circuitry to, at the Rx mode, downconvert a Rx signal from one or more antenna ports into an I-phase modulated downconverted signal based on the phase modulated I signal, and into a Q-phase modulated downconverted signal based on the phase modulated Q signal. In one example, the apparatus of Example 1465 may include, for example, one or more additional elements, for example, a bi-directional amplifier, a bi-directional mixer, a bi-directional splitter/combiner, a PA, an LNA, one or more switches, one or more mixers, and/or one or more phase shifters, e.g., as described with respect to Examples 1401, 1422, 1440, 1454, 1476, 1487, 1500, 1513, 1526, 1538, and/or 1551. Example 1466 includes the subject matter of Example 1465, and optionally, wherein the mixer circuitry comprises a first mixer to downconvert the received signal at the Rx mode into the I-phase modulated downconverted signal based on the phase modulated I signal; and a second mixer to downconvert the received signal at the Rx mode into the Q-phase modulated downconverted signal based on the phase modulated Q signal. Example 1467 includes the subject matter of Example 1466, and optionally, wherein the I/Q generator comprises a first switch to connect the first controllable phase modulation chain to the first mixer at the Rx mode; and a second switch to connect the first controllable phase modulation chain to a power amplifier at the Tx mode. Example 1468 includes the subject matter of Example 1465 comprising a Low Noise Amplifier (LNA) to generate the received signal based on a signal received from one or more phase array antennas. Example 1469 includes the subject matter of Example 1465, and optionally, wherein the I-phase modulated downconverted signal and the Q-phase modulated downconverted signal comprise baseband signals. Example 1470 includes the subject matter of Example 1465, and optionally, wherein the I/Q generator comprises a first phase modulator to shift a phase of the local oscillator signal by a first phase shift to be applied to an element of a phase array antenna; and a second phase modulator to shift a phase of the local oscillator signal by a second phase shift, which comprises a 90 degree rotation of the first phase shift. Example 1471 includes the subject matter of Example 1470, and optionally, wherein the first controllable phase modulation chain comprises the first phase modulator; and a tripler to triple a phase and a frequency of the phase modulated Tx signal at the Tx mode, and to triple a phase and a frequency of the phase modulated Q signal at the Rx mode. Example 1472 includes the subject matter of Example 1470, and optionally, wherein the second controllable phase modulation chain comprises the second phase modulator; and a tripler to triple a phase and a frequency of the phase modulated Q signal at the Rx mode. Example 1473 includes the subject matter of Example 1465, and optionally, wherein a frequency of the local oscillator signal is a third of a carrier frequency (fcarier/3). Example 1474 includes the subject matter of Example 1465 comprising one or more of phase array antennas. Example 1475 includes the subject matter of Example 1465 comprising a half-duplex transceiver. Example 1476 includes an apparatus comprising a Radio Frequency (RF) amplifier, the RF amplifier comprising first outphasing amplifier circuitry to provide a first in-phase (I) signal based on a first input signal, and a first Quadrature phase (Q) signal based on a second input signal; second outphasing amplifier circuitry to provide a second I signal based on the first input signal, and a second Q signal based on the second input signal; third outphasing amplifier circuitry to provide a third I signal based on a third input signal, and a third Q signal based on a fourth input signal; fourth outphasing amplifier circuitry to provide a fourth I signal based on the third input signal, and a fourth Q signal based on the fourth input signal; and a sub-quarter wavelength (SQWL) four-way combiner balun comprising a first inductive stub to couple the first I signal and the second I signal to a first transmission line, a second inductive stub to couple the third I signal and the fourth I signal to a second transmission line, a first capacitive stub to couple the first Q signal and the second Q signal to the first transmission line, and a second capacitive stub to couple the third Q signal and the fourth Q signal to the second transmission line, the first transmission line to provide a first RF signal based on a combination of the first I signal, the second I signal, the first Q signal, and the second Q signal, the second transmission line to provide a second RF signal based on a combination of the third I signal, the fourth I signal, the third Q signal, and the fourth Q signal. In one example, the apparatus of Example 1476 may include, for example, one or more additional elements, for example, a bi-directional amplifier, a bi-directional mixer, a bi-directional splitter/combiner, a PA, an LNA, one or more switches, one or more mixers, an I/Q generator, and/or one or more phase shifters, e.g., as described with respect to Examples 1401, 1422, 1440, 1454, 1465, 1487, 1500, 1513, 1526, 1538, and/or 1551. Example 1477 includes the subject matter of Example 1476, and optionally, wherein the first outphasing amplifier circuitry comprises a first outphasing amplifier operably coupled to the first inductive stub and the first capacitive stub, the second outphasing amplifier circuitry comprises a second outphasing amplifier operably coupled to the first inductive stub and the first capacitive stub, the third outphasing amplifier circuitry comprises a third outphasing amplifier operably coupled to the second inductive stub and the second capacitive stub, and the fourth outphasing amplifier circuitry comprises a fourth outphasing amplifier operably coupled to the second inductive stub and the second capacitive stub. Example 1478 includes the subject matter of Example 1477, and optionally, wherein each outphasing amplifier of the first, second, third, and fourth outphasing amplifiers comprises an I/Q generator to generate an initial I signal based on a local oscillator (LO) I signal, and to generate an initial Q signal based on a LO Q signal; phase modulator circuitry to generate a phase-modulated I signal by modulating the initial I signal based on a first input of the outphasing amplifier, and to generate a phase-modulated Q signal by modulating the initial Q signal based on a second input of the outphasing amplifier; a first amplifier to output an amplified I signal by amplifying the phase-modulated I signal; and a second amplifier to output an amplified Q signal by amplifying the phase-modulated Q signal. Example 1479 includes the subject matter of Example 1478, and optionally, wherein the first inductive stub is to apply a 25 Ohm impedance to an output of the first amplifier of the outphasing amplifier, and the first capacitive stub is to apply a 25 Ohm impedance to an output of the second amplifier of the outphasing amplifier. Example 1480 includes the subject matter of Example 1478 or 1479, and optionally, wherein the second inductive stub is to apply a 25 Ohm impedance to an output of the first amplifier of the outphasing amplifier, and the second capacitive stub to apply a 25 Ohm impedance to an output of the second amplifier of the outphasing amplifier. Example 1481 includes the subject matter of any one of Examples 1478-1480 comprising a LO to generate the LO I signal and the LO Q signal. Example 1482 includes the subject matter of any one of Examples 1476-1481, and optionally, wherein the SQWL four-way combiner balun comprises a Chireix combiner. Example 1483 includes the subject matter of any one of Examples 1476-1481, and optionally, wherein the SQWL four-way combiner balun comprises a non-isolating combiner. Example 1484 includes the subject matter of any one of Examples 1476-1483 comprising a half-duplex transceiver. Example 1485 includes the subject matter of any one of Examples 1476-1484 comprising one or more antennas operably coupled to the RF amplifier. Example 1486 includes the subject matter of any one of Examples 1476-1485 comprising one or more phased-array antennas operably coupled to the RF amplifier. Example 1487 includes an apparatus comprising a controllable phase-shifter, the controllable phase-shifter comprising In-phase (I) phase shifting circuitry to provide a phase shifted I signal based on an I signal and a Quadrature-phase (Q) signal, the I phase shifting circuitry configured to provide a first shifted I signal by shifting a phase of the I signal according to a first control signal, to provide a first shifted Q signal by shifting a phase of the Q signal according to a second control signal, and to provide the phase shifted I signal by combining the first shifted I signal with the first shifted Q signal; and Q phase shifting circuitry to provide a phase shifted Q signal based on the Q signal and the I signal, the Q phase shifting circuitry configured to provide a second shifted I signal by shifting the phase of the I signal according to a third control signal, to provide a second shifted Q signal by shifting the phase of the Q signal according to a fourth control signal, and to provide the phase shifted Q signal by combining the second shifted I signal with the second shifted Q signal. In one example, the apparatus of Example 1487 may include, for example, one or more additional elements, for example, a bi-directional amplifier, a bi-directional mixer, a bi-directional splitter/combiner, a PA, an LNA, one or more switches, one or more mixers, and/or an I/Q generator, e.g., as described with respect to Examples 1401, 1422, 1440, 1454, 1465, 1476, 1500, 1513, 1526, 1538, and/or 1551. Example 1488 includes the subject matter of Example 1487, and optionally, wherein the I phase shifting circuitry comprises a first voltage digital to analog convertor (VDAC) to convert the first control signal into an I control voltage, the I phase shifting circuitry to shift the phase of the I signal according to the I control voltage; and a second VDAC to convert the second control signal into a Q control voltage, the I phase shifting circuitry to shift the phase of the Q signal according to the Q control voltage. Example 1489 includes the subject matter of Example 1488, and optionally, wherein the I phase-shifting circuitry comprises a first plurality of transistors in a cascode gate arrangement to generate the first shifted I signal according to the I control voltage; and a second plurality of transistors in a cascode gate arrangement to generate the first shifted Q signal according to the Q control voltage. Example 1490 includes the subject matter of any one of Examples 1487-1489, and optionally, wherein the Q phase shifting circuitry comprises a first voltage digital to analog convertor (VDAC) to convert the third control signal into an I control voltage, the Q phase shifting circuitry to shift the phase of the I signal according to the I control voltage; and a second VDAC to convert the fourth control signal into a Q control voltage, the Q phase shifting circuitry to shift the phase of the Q signal according to the Q control voltage. Example 1491 includes the subject matter of Example 1490, and optionally, wherein the Q phase-shifting circuitry comprises a first plurality of transistors in a cascode gate arrangement to generate the second shifted I signal according to the I control voltage; and a second plurality of transistors in a cascode gate arrangement to generate the second shifted Q signal according to the Q control voltage. Example 1492 includes the subject matter of any one of Examples 1487-1491 comprising a Low Noise Amplifier (LNA) to provide a Receive (Rx) signal by amplifying a Radio Frequency (RF) signal from one or more antennas; a first mixer operably coupled to the first input of the controllable phase-shifter, the first mixer to generate the I signal by mixing the Rx signal according to a sine signal; and a second mixer operably coupled to the second input of the voltage-controlled phase shifter, the second mixer to generate the Q signal by mixing the Rx signal according to a cosine signal. Example 1493 includes the subject matter of any one of Examples 1487-1492 comprising a first mixer operably coupled to a first output of the controllable phase-shifter, the first mixer to generate a first Radio Frequency (RF) signal by mixing the phase shifted I signal according to a sine signal; a second mixer operably coupled to a second output of the controllable phase shifter, the second mixer to generate a second RF signal by mixing the phase shifted Q signal according to a cosine signal; and a Power Amplifier (PA) to provide a Transmit (Tx) signal to one or more antennas by amplifying the first RF signal and the second RF signal. Example 1494 includes the subject matter of Example 1487 comprising a calibration sub-system configured to calibrate linearity and resolution of the controllable phase-shifter based on a predefined constellation-point map. Example 1495 includes the subject matter of Example 1494, and optionally, wherein the calibration sub-system is to generate a Look Up Table (LTU) comprising a plurality of pairs of voltage values corresponding to a respective plurality of constellation points according to the predetermined constellation-point map, a pair of voltage values comprising a first I voltage value to be applied to the first control signal, a first Q voltage value to be applied to the second control signal, a second I voltage value to be applied to the third control signal and a second Q voltage value to be applied to the fourth control signal. Example 1496 includes the subject matter of Example 1494 or 1495, and optionally, wherein the first control signal comprises a first digital signal to apply first data to the I phase shifting circuitry based on the predefined constellation-point map, the second control signal comprises a second digital signal to apply second data to the I phase shifting circuitry based on the predefined constellation-point map, the third control signal comprises a third digital signal to apply third data to the Q phase shifting circuitry based on the predefined constellation-point map, and the fourth control signal comprises a fourth digital signal to apply fourth data to the Q phase shifting circuitry based on the predefined constellation-point map. Example 1497 includes the subject matter of one of Examples 1487-1495 comprising a transceiver to be operably coupled to one or more phased-array antennas. Example 1498 includes the subject matter of Example 1497, and optionally, wherein the transceiver comprises a half-duplex transceiver. Example 1499 includes the subject matter of Example 1497, and optionally, wherein the transceiver comprises a full-duplex transceiver Example 1500 includes an apparatus comprising a power amplifier (PA) Low Noise Amplifier (LNA) (PA-LNA) interface to interface an antenna terminal with a PA and an LNA, the PA-LNA interface comprising a sensor to provide a sensed signal based on a transmit (Tx) signal from the PA; a phase rotator to provide a phase rotated signal by rotating a phase of the sensed signal; a variable gain amplifier (VGA) to provide a Tx leakage cancelation signal by amplifying the phase rotated signal based on an amplitude of the Tx signal; and a combiner to combine a first combiner input signal with a second combiner input signal, the first combiner input signal comprising the Tx leakage cancellation signal, the second combiner input signal comprising a Tx leakage from the Tx signal to the LNA. In one example, the apparatus of Example 1500 may include, for example, one or more additional elements, for example, a bi-directional amplifier, a bi-directional mixer, a bi-directional splitter/combiner, a PA, an LNA, one or more switches, one or more mixers, an I/Q generator, and/or one or more phase shifters, e.g., as described with respect to Examples 1401, 1422, 1440, 1454, 1465, 1476, 1487, 1513, 1526, 1538, and/or 1551. Example 1501 includes the subject matter of Example 1500, and optionally, wherein, at a Receive (Rx) mode, the second combiner input signal comprises a combination of a Receive (Rx) signal from the antenna terminal, and the Tx leakage from the Tx signal to the LNA. Example 1502 includes the subject matter of Example 1501, and optionally, wherein, at the Rx mode, the combiner is to provide to the LNA a sum of the first combiner input signal and the second combiner input signal. Example 1503 includes the subject matter of any one of Example 1500-1502, and optionally, wherein the phase rotator is configured to rotate the phase of the sensed signal by 180 degrees. Example 1504 includes the subject matter of any one of Examples 1500-1503, and optionally, wherein the combiner comprises a Wilkinson combiner. Example 1505 includes the subject matter of any one of Examples 1500-1504, and optionally, wherein the sensor comprises a capacitive sensor. Example 1506 includes the subject matter of any one of Examples 1500-1505, and optionally, wherein the PA-LNA interface is configured to provide the Tx signal from the PA to the antenna terminal at a Tx mode, and to provide a receive (Rx) signal from the antenna terminal to the LNA at an Rx mode. Example 1507 includes the subject matter of Example 1506, and optionally, wherein the PA-LNA interface is to apply a high impedance to an input of the LNA at the Tx mode. Example 1508 includes the subject matter of Example 1506 or 1507, and optionally, wherein the PA-LNA interface is to apply a high impedance at an output of the PA at the Rx mode. Example 1509 includes the subject matter of any one of Examples 1500-1508 comprising a half-duplex transceiver. Example 1510 includes the subject matter of any one of Examples 1500-1509 comprising a full-duplex transceiver. Example 1511 includes the subject matter of any one of Examples 1500-1510 comprising one or more antennas operably coupled to the antenna terminal. Example 1512 includes the subject matter of any one of Examples 1500-1511 comprising transmitter circuitry to transmit the Tx signal at a Tx mode, and receiver circuitry to receive the Rx signal at a Receive (Rx) mode. Example 1513 includes an apparatus comprising local oscillator (LO) distribution network circuitry comprising at least one In-phase (I) Quadrature phase (Q) (IQ) generator, the I/Q generator comprising phase shifting circuitry to generate a first phase shifted signal and a second phase shifted signal based on a LO signal having a first frequency, a phase of the second phase shifted signal is shifted by 30 degrees from a phase of the first phase shifted signal; first tripler circuitry to generate an I signal having a second frequency, by tripling the phase of the first phase shifted signal and tripling a frequency of the first phase shifted signal; and second tripler circuitry to generate a Q signal having the second frequency, by tripling the phase of the second phase shifted signal and tripling a frequency of the second phase shifted signal. In one example, the apparatus of Example 1513 may include, for example, one or more additional elements, for example, a bi-directional amplifier, a bi-directional mixer, a bi-directional splitter/combiner, a PA, an LNA, one or more switches, one or more mixers, and/or one or more phase shifters, e.g., as described with respect to Examples 1401, 1422, 1440, 1454, 1465, 1476, 1487, 1500, 1526, 1538, and/or 1551. Example 1514 includes the subject matter of Example 1513 or 1514, and optionally, wherein the first phase shifted signal comprises a first I phase shifted signal and a second I phase shifted signal, and the second phase shifted signal comprises a first Q phase shifted signal and a second Q phase shifted signal. Example 1515 includes the subject matter of Example 1514, and optionally, wherein the first tripler circuitry comprises imbalance and amplitude circuitry to balance an amplitude of the first I phase shifted signal according to the second Q phase shifted signal, and to balance an amplitude of the second I phase shifted signal according to the first Q phase shifted signal. Example 1516 includes the subject matter of Example 1514 or 1515, and optionally, wherein the second tripler circuitry comprises imbalance and amplitude circuitry to balance an amplitude of the first Q phase shifted signal according to the second I phase shifted signal, and to balance an amplitude of the second Q phase shifted signal according to the first I phase shifted signal. Example 1517 includes the subject matter of any one of Examples 1513-1515, and optionally, wherein the phase shifting circuitry comprises passive phase shifting circuitry. Example 1518 includes the subject matter of any one of Examples 1513-1517, and optionally, wherein the phase shifting circuitry comprises first injection LO (ILO) circuitry to generate the first phase shifted signal; and second ILO circuitry to generate the second phase shifted signal. Example 1519 includes the subject matter of any one of Examples 1513-1518, and optionally, wherein the at least one IQ generator comprises a Receive (Rx) IQ generator, the apparatus comprising one or more low noise amplifiers (LNAs) to generate an amplified Rx signal based on an Rx signal; and Rx mixer circuitry to downconvert the amplified Rx signal into a downconverted I signal based on the I signal and the amplified Rx signal, and to downconvert the amplified Rx signal into a downconverted Q signal based on the Q signal and the amplified Rx signal. Example 1520 includes the subject matter of Example 1519, and optionally, wherein the Rx mixer circuitry comprises a first mixer to downconvert the Rx signal into the downconverted I signal; and a second mixer to downconvert the Rx signal into the downconverted Q signal. Example 1521 includes the subject matter of any one of Examples 1513-1520, and optionally, wherein the at least one IQ generator comprises a Transmit (Tx) IQ generator, the apparatus comprising Tx mixer circuitry to upconvert an intermediate frequency (IF) I signal into an upconverted I signal based on the I signal, and to upconvert an IF Q signal into an upconverted Q signal based on the Q signal; a combiner to combine the upconverted I signal and the upconverted Q signal into a Tx signal; and a power amplifier (PA) to amplify the Tx signal. Example 1522 includes the subject matter of Example 1521, and optionally, wherein the Tx mixer circuitry comprises a first mixer to upconvert the IF I signal into the upconverted I signal; and a second mixer to upconvert the IF Q signal into the upconverted Q signal. Example 1523 includes the subject matter of any one of Examples 1521-1522, and optionally, wherein the at least one IQ generator comprises a first IQ generator to generate a first I signal and a first Q signal, and a second IQ generator to generate a second I signal and a second Q signal. Example 1524 includes the subject matter of any one of Examples 1513-1523 comprising a transceiver operably coupled to one or more antennas. Example 1525 includes the subject matter of Example 1524, and optionally, wherein the transceiver comprises a half-duplex transceiver. Example 1526 includes an apparatus comprising wideband amplifier circuitry, the wideband amplifier circuitry comprising a splitter to split a radio frequency (RF) input signal into a high frequency band signal and a low frequency band signal, the splitter comprising first circuitry to filter the low frequency band signal from the RF input signal, and second circuitry to filter the high frequency band signal from the RF input signal; a high band amplifier to amplify the high frequency band signal to provide a first amplified signal; a low band amplifier to amplify the low frequency band signal to provide a second amplified signal; and a combiner to combine the first amplified signal and the second amplified signal into an amplified RF signal. In one example, the apparatus of Example 1526 may include, for example, one or more additional elements, for example, a bi-directional amplifier, a bi-directional mixer, a bi-directional splitter/combiner, a PA, an LNA, one or more switches, one or more mixers, an I/Q generator, and/or one or more phase shifters, e.g., as described with respect to Examples 1401, 1422, 1440, 1454, 1465, 1476, 1487, 1500, 1513, 1538, and/or 1551. Example 1527 includes the subject matter of Example 1526, and optionally, wherein the wideband amplifier circuitry comprises a first switch to activate the low band amplifier when the RF input signal is at least over a first frequency band; and a second switch to activate the high band amplifier when the RF input signal is at least over a second frequency band, higher than the first frequency band. Example 1528 includes the subject matter of Example 1526 or Example 1527 comprising baseband circuitry to controllably activate the first switch and the second switch based on one or more frequency bands of the RF input signal. Example 1529 includes the subject matter of any one of Examples 1526-1528, and optionally, wherein the combiner comprises a transformer to receive the first amplified signal from the high band amplifier at a first section of the transformer and to match an impedance between the first section of the transformer and the high band amplifier and the transformer to receive the second amplified signal from the low band amplifier at a second section of the transformer, and to match an impedance between the second section of the transformer and the low band amplifier, the transformer comprising a third section to combine the first amplified signal from the first section of the transformer with the second amplified signal from the second section of the transformer into the amplified RF signal. Example 1530 includes the subject matter of Example 1529, and optionally, wherein a physical size of the first section of the transformer is larger than a physical size of the second section of the transformer. Example 1531 includes the subject matter of any one of Examples 1526-1530, and optionally, wherein the splitter comprises a transformer to receive the RF input signal, at a first section of the transformer, to provide, by a second section of the transformer, the low frequency band signal to the low band amplifier and to match an impedance between the second section of the transformer and the low band amplifier, and to provide, by a third section of the transformer, the high frequency band to the high band amplifier and to match impedance between the third section of the transformer and the high band amplifier. Example 1532 includes the subject matter of Example 1531, and optionally, wherein the first circuitry comprises the second section of the transformer and at least part of the first section of the transformer, and the second circuitry comprises the third section of the transformer and at least part of the first section of the transformer. Example 1533 includes the subject matter of any one of Examples 1526-1532 comprising baseband circuitry to generate an intermediate frequency (IF) input signal; and RF circuitry to generate the RF input signal by upconverting the IF input signal. Example 1534 includes the subject matter of Example 1533, and optionally, wherein the baseband circuitry and the RF circuitry are operably coupled by an RF cable. Example 1535 includes the subject matter of Example of any one of Examples 1526-1534 comprising a transmitter to be operably coupled to one or more phased-array antennas. Example 1536 includes the subject matter of any one of Examples 1526-1535 comprising one or more phased-array antennas operably coupled to the wideband amplifier. Example 1537 includes the subject matter of any one of Examples 1526-1536, and optionally, wherein the wideband amplifier comprises a 60 GHZ band amplifier. Example 1538 includes an apparatus comprising a plurality of impedance matching switches to switchably couple a modem core to one or more radio cores of a plurality of radio cores, an impedance matching switch of the plurality of impedance matching switches comprising a first terminal to be operably coupled to the modem core; a second terminal to be operably coupled to a respective radio core of the plurality of radio cores; and impedance matching circuitry to controllably match an impedance between the radio core and the modem core, based on a count of the one or more radio cores to be coupled to the modem core by the plurality of impedance matching switches. In one example, the apparatus of Example 1538 may include, for example, one or more additional elements, for example, a bi-directional amplifier, a bi-directional mixer, a bi-directional splitter/combiner, a PA, an LNA, one or more mixers, an I/Q generator, and/or one or more phase shifters, e.g., as described with respect to Examples 1401, 1422, 1440, 1454, 1465, 1476, 1487, 1500, 1513, 1526, and/or 1551. Example 1539 includes the subject matter of Example 1538, and optionally, wherein the impedance matching circuitry is switchable between a plurality of impedance matching modes according to a control signal from the modem core, the plurality of impedance matching modes corresponding to a respective plurality of different radio core counts to be coupled to the modem core. Example 1540 includes the subject matter of Example 1539, and optionally, wherein the impedance matching circuitry is configured to, at an impedance matching mode of the plurality of impedance matching modes, match an impedance between the radio core and the modem core based on a radio core count corresponding to the impedance matching mode. Example 1541 includes the subject matter of Example 1539 or 1540, and optionally, wherein the plurality of impedance matching modes comprises a first impedance matching mode, in which the impedance matching circuitry is to match the impedance between the modem core and one radio core; a second impedance matching mode, in which the impedance matching circuitry is to match the impedance between the modem core and two radio cores; and a third impedance matching mode, in which the impedance matching circuitry is to match the impedance between the modem core and three radio cores. Example 1542 includes the subject matter of any one of Examples 1538-1541, and optionally, wherein the impedance matching circuitry comprises a plurality of transistors to couple the modem core to the one or more radio cores. Example 1543 includes the subject matter of any one of Examples 1538-1542 comprising a plurality of Radio Frequency (RF) cables, an RF cable of the plurality of RF cables to connect a respective impedance matching switch of the plurality of impedance matching switches to a respective radio core of the plurality of radio cores. Example 1544 includes the subject matter of Example 1543, and optionally, wherein at least one RF cable of the plurality of RF cables comprises a coax cable. Example 1545 includes the subject matter of any one of Examples 1538-1544, and optionally, wherein the impedance matching switch is to maintain about 50 Ohm impedance between the radio core and the one or more radio cores. Example 1546 includes the subject matter of any one of Examples 1538-1545 comprising the plurality of radio cores. Example 1547 includes the subject matter of Example 1546, and optionally, wherein at least one radio core of the plurality of radio cores comprises a half-duplex transceiver. Example 1548 includes the subject matter of any one of Examples 1538-1547 comprising baseband circuitry comprising the modem core. Example 1549 includes the subject matter of any one of Examples 1538-1548 comprising one or more antennas. Example 1550 includes the subject matter of any one of Examples 1538-1549 comprising one or more phase-array antennas. Example 1551 includes an apparatus comprising bi-directional mixer, the bi-directional mixer comprising a radio frequency (RF) terminal; an intermediate frequency (IF) terminal; a first voltage terminal; a second voltage terminal; and mixing circuitry configured to operate at an upconversion mode when a first bias voltage is to be applied to the first voltage terminal and a second bias voltage is to be applied to the second voltage terminal, and to operate at a downconversion mode when the second bias voltage is to be applied to the first voltage terminal and the first bias voltage is to be applied to the second voltage terminal, the mixing circuitry to, at the downconversion mode, downconvert a first RF signal at the RF terminal into a first IF signal at the IF terminal, and, at the upconversion mode, upconvert a second IF signal at the IF terminal into a second RF signal at the RF terminal. In one example, the apparatus of Example 1551 may include, for example, one or more additional elements, for example, a bi-directional amplifier, a bi-directional splitter/combiner, a PA, an LNA, one or more switches, one or more mixers, an I/Q generator, and/or one or more phase shifters, e.g., as described with respect to Examples 1401, 1422, 1440, 1454, 1465, 1476, 1487, 1500, 1513, 1526, and/or 1538. Example 1552 includes the subject matter of Example 1551, and optionally, wherein the mixing circuitry comprises a Gilbert-cell comprising a plurality of transistors, the plurality of transistors to upconvert the second IF signal into the second RF signal at the upconversion mode, and to downconvert the first RF signal into the first IF signal at the downconversion mode. Example 1553 includes the subject matter of Example 1552, and optionally, wherein the mixing circuitry comprises a first transformer to couple drains of the plurality of transistors to the RF terminal and to the first voltage terminal; a second transformer to couple sources of the plurality of transistors to the IF terminal and to the second voltage terminal; and a local oscillator (LO) terminal to couple a LO signal to gates of the plurality of transistors. Example 1554 includes the subject matter of Example 1553, and optionally, wherein, at the upconversion mode, the second transformer is to provide the second IF signal and the second bias voltage to the sources of the plurality of transistors, and the Gilbert cell is to mix the second IF signal with the LO signal to provide a mixed RF signal to the drains of the plurality of transistors. Example 1555 includes the subject matter of Example 1554, and optionally, wherein the first transformer is to combine the mixed IF signal at the drains of the plurality of transistors into the first RF signal. Example 1556 includes the subject matter of any one of Examples 1553-1555, and optionally, wherein, at the downconversion mode, the first transformer is to provide the first RF signal and the second bias voltage to the drains of the plurality of transistors, and the Gilbert cell is to mix the first RF signal with the LO signal to provide a mixed IF signal to the sources of the plurality of transistors. Example 1557 includes the subject matter of Example 1556, and optionally, wherein the second transformer is to combine the mixed RF signal at the sources of the plurality of transistors into the second IF signal. Example 1558 includes the subject matter of any one of Examples 1552-1557, and optionally, wherein the mixing circuitry comprises a first switch operably coupled to the first voltage terminal to, at the upconversion mode, couple the first bias voltage to the drains of the plurality of transistors, and to, at the downconversion mode, couple the second bias voltage to the drains of the plurality of transistors; and a second switch operably coupled to the second voltage terminal to, at the upconversion mode, couple the second bias voltage to the sources of the plurality of transistors, and to, at the downconversion mode, couple the first bias voltage to the sources of the plurality of transistors. Example 1559 includes the subject matter of any one of Examples 1552-1558 comprising a controller to switch the bi-directional mixer to the upconversion mode by applying the first bias voltage to drains of the plurality of transistors, and by applying the second bias voltage to sources of the plurality of transistors. Example 1560 includes the subject matter of Example 1559, and optionally, wherein the controller is to switch the bi-directional mixer to the downconversion mode by applying the first bias voltage to the sources of the plurality of transistors, and by applying the second bias voltage to the drains of the plurality of transistors. Example 1561 includes the subject matter of any one of Examples 1552-1560, and optionally, wherein the plurality of transistors comprises one or more field effect transistors (FETs). Example 1562 includes the subject matter of any one of Examples 1551-1561 comprising a bi-directional RF amplifier to, at a Transmit (Tx) mode, amplify the second RF signal from the bi-directional mixer into a Tx RF signal, and to, at a Receive (Rx) mode, amplify an Rx RF signal to provide the first RF signal to the first terminal; and a bi-directional IF amplifier to, at the Tx mode, amplify a first baseband signal into the second IF signal, and to, at the Rx mode, amplify the first IF signal from the second terminal of the bi-directional mixer into a second baseband signal. Example 1563 includes the subject matter of any one of Examples 1551-1561 comprising a first RF amplifier to, at a Transmit (Tx) mode, amplify the second RF signal from the bi-directional mixer into a Tx RF signal; a second RF amplifier to, at a Receive (Rx) mode, amplify an Rx RF signal into the first RF signal to be provided to the bi-directional mixer; a first IF amplifier to, at the Tx mode, amplify a first baseband signal into the second IF signal to be provided to the bi-directional mixer; and a second IF amplifier to, at the Rx mode, amplify the first IF signal from the bi-directional mixer into a second baseband signal. Example 1564 includes the subject matter of Example 1563, and optionally, wherein the first RF amplifier comprises a power amplifier, and the second RF amplifier comprises a Low Noise Amplifier (LNA). Example 1565 includes the subject matter of Example 1563 or 1564, and optionally, wherein the first IF amplifier comprises a Tx IF amplifier and the second IF amplifier comprises an Rx IF amplifier. Example 1566 includes the subject matter of any one of Examples 1551-1565 comprising a half-duplex transceiver. Example 1567 includes the subject matter of Example 1566 comprising one or more antennas operably coupled to the transceiver. Example 1568 includes the subject matter of Example 1567, and optionally, wherein the one or more antennas comprise one or more phased-array antennas. In Example 1569, the subject matter of Example 1 optionally includes an apparatus for a mobile device, the apparatus comprising: a circuit board comprising a plurality of parallel layers that include a top layer and a bottom layer; a radio front end module attached to the circuit board and comprising an integrated circuit (IC); a grounded shield attached to the circuit board, the grounded shield configured to shield the IC from interference; a stacked patch directional antenna that comprises a radiating element and a parasitic element, at least the parasitic element situated adjacent the grounded shield, and the radiating element situated on one of the layers of the circuit board other than the top layer and the bottom layer, and fed by a feed mechanism comprising a feed strip coupled to the IC; wherein the grounded shield is configured as a reflector and as a ground plane for the stacked patch directional antenna, and wherein the stacked patch directional antenna is configured to propagate signals of a first polarization in an endfire direction and signals of a second polarization a broadside direction, and wherein the first and second polarizations are orthogonal polarizations. The first polarization comprises signals having an electric field that is parallel to the layers of circuit board and the second polarization comprises signals that are perpendicular to the layers of circuit board. In Example 1570, the subject matter of Example 1569 optionally includes wherein the first polarization is a horizontal polarization and the second polarization is vertical polarization. In Example 1571, the subject matter of any one or more of Examples 1569–1570 optionally include wherein the feed mechanism further comprises a via that couples the feed line and the radiating element. In Example 1572, the subject matter of any one or more of Examples 1569-1571 optionally include wherein when transmission is in endfire direction the stacked patch directional antenna is configured to operate as a monopole antenna. In Example 1573, the subject matter of any one or more of Examples 1569-1572 optionally include wherein the grounded shield is rectilinear and has a plurality of first sides, and a second side orthogonal to the plurality of first sides, wherein a plurality of the stacked directional patch antennas comprises an antenna array situated at one of the first sides of the shield within the apparatus. In Example 1574, the subject matter of any one or more of Examples 1569-1573 optionally include wherein the grounded shield is rectilinear and has a plurality of first sides, and a second side orthogonal to the plurality of first sides, and a plurality of the stacked patch antennas comprises a plurality of antenna arrays, at least a first of the plurality of antenna arrays is situated at a first one of the first sides of the grounded shield within the apparatus, and at least a second of the plurality of antenna arrays is situated at a second one of the first sides of the grounded shield within the apparatus. In Example 1575, the subject matter of any one or more of Examples 1569-1574 optionally include wherein the feed mechanism includes a feed point into the stacked directional patch antenna and the feed point is configured to impedance match the stacked directional patch antenna. Example 1576 is an apparatus of a mobile device, the apparatus comprising: a printed circuit board comprising a top side and a bottom side; a radio front end module attached to the top side of the circuit board and comprising an integrated circuit (IC); a conductive shield that covers the IC and is attached to the top side of the circuit board, wherein the conductive shield comprises four sides and a top, and is configured to protect the IC from radio frequency interference; and at least one directional antenna formed by at least one cut out section of the shield, wherein the at least one directional antenna is fed by at least one feed mechanism that is part of the circuit board and is coupled to the IC, wherein the circuit board comprises a ground plane for the at least one directional antenna, and wherein the at least one directional antenna is configured to radiate in a direction outward from the IC. In Example 1577, the subject matter of Example 1576 optionally includes wherein the at least one directional antenna comprises a planar inverted F antenna (PIFA) that terminates at the feed mechanism, and is configured to resonate at a quarter wavelength. In Example 1578, the subject matter of any one or more of Examples 1576-1577 optionally include wherein the at least one antenna comprises a notch antenna, a slot antenna or a patch antenna. In Example 1579, the subject matter of any one or more of Examples 1576-1578 optionally include wherein the at least one antenna comprises an array of two antennas, wherein each antenna of the array is situated on the shield orthogonal to each other, and the at least one feed mechanism comprises two feed mechanisms that each respectively feeds one of the two antennas and wherein the antenna array is configured to support two different polarizations. In Example 1580, the subject matter of Example 1579 optionally includes wherein each of the two antennas of the array is configured on different sides of the shield or wherein one of the two antennas is configured on one of the four sides of the shield and a second of the two antennas is configured on the top of the shield. In Example 1581, the subject matter of any one or more of Examples 1576-1580 optionally include wherein the at least one antenna comprises an array of two antennas, wherein each antenna of the array is situated on the shield orthogonal to each other, wherein the at least one feed mechanism comprises two feed mechanisms that each respectively feeds one of the two antennas, and wherein the radio front-end module is configured to provide each of the feed mechanisms with a same signal to create a new vector summation, or to provide each of the feed mechanisms with different signals for Multiple In Multiple Out (MIMO) modes of operation. In Example 1582, the subject matter of any one or more of Examples 1579-1581 optionally include wherein each of the two feed mechanisms is configured to activate the two antennas at different times to provide a first of the two different polarizations for a first of the two antennas and a second of the two different polarizations for a second of the two antennas. In Example 1583, the subject matter of Example 1582 optionally includes wherein the radio front end module is configured to be activated by algorithmic control, the activation is dependent on the orientation of a receiving device, the apparatus receives, from the receiving device, feedback information that designates whether the first polarization or the second polarization provides better reception at a given one of the different times, and the feedback information comprises the algorithmic control of the activation of the feedlines. Example 1584 is apparatus of a mobile device, the apparatus comprising: a transceiver situated on a substrate within the apparatus; a phased array of antenna elements coupled to the transceiver and configured to transmit radio waves within a first angle of coverage when the phased array is scanned; and a lens placed adjacent the phased array and configured to deflect the transmitted radio waves to a second angle of coverage that is larger than the first angle of coverage. In Example 1585, the subject matter of Example 1584 optionally includes wherein the lens comprises a prism. Example 1586 is an antenna system comprising: a radio front end module configured to generate radio waves; a reflector; and a plurality of phased arrays of antenna elements each array located at different positions adjacent the reflector and configured to transmit the generated radio waves toward the reflector to irradiate a focus of the reflector with the radio waves, wherein the location of each array at different positions causes radio frequency radiation from the reflector in a plurality of narrow beams, each beam tilted in a different direction for scanning a different beam-scanning sector, and wherein adding an additional phased array to the plurality of phased arrays causes formation of an additional beam-scanning sector. In Example 1587, the subject matter of Example 1586 optionally includes wherein each phased array is located at one of a side of, or at the bottom of, the reflector. In Example 1588, the subject matter of any one or more of Examples 1586-1587 optionally include wherein each phased array antenna element has two feed mechanisms, a first of the two feed mechanisms configured to provide generated radio waves to the antenna element at a first polarization and a second of the two feed mechanisms configured to provide generated radio waves to the antenna element at a second polarization that is orthogonal to the first polarization. Example 1589 is apparatus of a mobile device, the apparatus comprising: a chassis; a substrate within the chassis; a conformably shielded integrated circuit (IC) die comprising a transceiver configured to generate radio frequency (RF) signals, the IC die connected to the substrate within the chassis; one or more antenna directors on or within the chassis external to the substrate; and an antenna array coupled to the transceiver and configured to transmit the RF signals to interact with the one or more antenna directors, wherein the antenna array is within a first side of the substrate, on a surface mounted device (SMD) that is mounted on a second side of the substrate, or within the SMD that is mounted on the second side of the substrate, and wherein the one or more antenna directors is configured to direct the RF signals. In Example 1590, the subject matter of Example 1589 optionally includes wherein the conformable shield comprises a ground plane for the antenna array. In Example 1591, the subject matter of any one or more of Examples 1589-1590 optionally include further comprising a heat conducting mechanism configured to conduct heat from the IC die onto a surface external to the die. In Example 1592, the subject matter of any one or more of Examples 1589-1591 optionally include wherein the heat conducting mechanism is a heat spreader coupled to the IC die. Example 1593 is an apparatus of a mobile device, the apparatus comprising: a substrate; an integrated circuit (IC) that comprises a transceiver configured to generate radio frequency (RF) signals, the IC being connected to the substrate; a dipole antenna that has two horizontal arms and is configured within the substrate; and a surface mounted device (SMD) that comprises a vertical metallic via, wherein the SMD is mounted on the substrate adjacent the dipole antenna, wherein the vertical metallic via contacts one of the two horizontal arms of the dipole antenna, wherein the vertical metallic via comprises a vertical arm of a monopole antenna, and wherein when fed with the RF signals, the dipole antenna is configured to exhibit a first polarization and when fed with the RF signals the vertical arm of the monopole antenna is configured to exhibit a second polarization. In Example 1594, the subject matter of Example 1593 optionally includes wherein the vertical metallic via comprises a metal trace. In Example 1595, the subject matter of any one or more of Examples 1593-1594 optionally include wherein the vertical metallic via extends to the top of the SMD and the monopole antenna further comprises a horizontal metal trace configured on the top of the SMD, wherein the horizontal metal trace contacts, and is perpendicular to, the vertical metallic via and comprises part of the vertical arm of the monopole antenna. Example 1596 is an L-shaped dipole antenna comprising: a substrate that comprises a horizontal arm of a dipole antenna; an integrated circuit (IC) shield that covers an IC die and is connected to the substrate; and a surface mounted device (SMD) that is mounted on the substrate adjacent the IC shield, wherein the SMD comprises a vertical arm of the dipole antenna, wherein the vertical arm is at least partly internal to the SMD, wherein the IC shield functions as a reflector for the dipole antenna, wherein the dipole antenna is fed by a feed line from the IC die, and wherein the configuration of the horizontal arm of the dipole antenna and the vertical arm of the dipole antenna comprises an L-shape. In Example 1597, the subject matter of Example 1596 optionally includes wherein at least part of the vertical arm is internal to the substrate. In Example 1598, the subject matter of Example 1597 optionally includes wherein the at least part of the vertical arm that is internal to the substrate comprises a metallized via. In Example 1599, the subject matter of Example 1598 optionally includes wherein the metalized via comprises a metal trace. In Example 1600, the subject matter of any one or more of Examples 1596-1599 optionally include wherein the at least part of the vertical arm that is internal to the SMD extends through the SMD, wherein a horizontal metal trace is configured on the top of the SMD, and wherein the horizontal metal trace contacts, and is perpendicular to, the vertical arm and is a part of the vertical arm. Example 1601 is an apparatus of a mobile device, the apparatus comprising: a substrate; an integrated circuit (IC) shield that covers an IC that is configured to generate radio frequency (RF) chains, both the shield and the IC being connected to the substrate; and an antenna array comprising a plurality of L-shaped dipole antennas, each dipole antenna situated adjacent the IC shield, wherein each dipole antenna is configured to be fed by an RF chain from the IC, wherein each dipole antenna comprises a horizontal arm and a vertical arm, and wherein the dipole antennas of the plurality are arranged in adjacent pairs with the horizontal arms of each adjacent pair oriented in opposite directions. In Example 1602, the subject matter of Example 1601 optionally includes wherein when each dipole antenna is fed by an RF chain from the IC, the array provides a plurality of RF chains, each provided RF chain having both a first polarization and a second polarization that is orthogonal to the first polarization. Example 1603 is an apparatus for a mobile device, the apparatus comprising: a printed circuit board (PCB) that comprises a top layer and a bottom layer; an integrated circuit (IC) chip that comprises a top level and a bottom level, wherein the IC chip comprises a transceiver and the IC chip is connected to the top layer of the PCB; an antenna array that comprises a plurality of antenna elements configured within the bottom level of the IC chip adjacent the PCB and fed by feed transmission lines coupled to the transceiver; and an IC shield that covers the IC to shield the IC from interference, and is connected to the PCB, wherein one of the IC shield or a ground layer within the PCB comprises a ground for the antenna array. In Example 1604, the subject matter of Example 1603 optionally includes further comprising a clearance volume between the PCB and the antenna array to prevent at least one antenna element from contacting the PCB. In Example 1605, the subject matter of any one or more of Examples 1603–1604 optionally include wherein the transmission feed lines comprise metal traces. In Example 1606, the subject matter of any one or more of Examples 1603–1605 optionally include wherein the PCB comprises a mother board. Example 1607 is apparatus of a mobile device, the apparatus comprising: a transceiver configured on an integrated circuit (IC) that is connected to a printed circuit board (PCB), the transceiver configured to generate radio frequency (RF) signals in a first frequency band and in a second frequency band; a first antenna configured within the PCB, and a second antenna configured within the PCB in coaxial relationship to the first antenna; a first feed mechanism coupled to the transceiver and to the first antenna, wherein the first feed mechanism feeds the first antenna with RF signals in the first frequency band; a second feed mechanism situated orthogonal to the first feed mechanism, the second feed mechanism coupled to the transceiver and to the second antenna, wherein the second feed mechanism feeds the second antenna with RF signals in the second frequency band, wherein the processing circuitry is configured to operate each feed mechanism at different times to activate each of the first antenna and the second antenna at different times, and wherein when activated at a first time the first antenna transmits RF signals in the first frequency band in a first polarization, and when activated at a second time the second antenna transmits the RF signals in the second frequency band in a second polarization that is orthogonal to the first polarization. In Example 1608, the subject matter of Example 1607 optionally includes wherein the first antenna is a patch antenna that is configured as a driven antenna element and a parasitic antenna element, and the second antenna is a slot antenna. In Example 1609, the subject matter of Example 1608 optionally includes wherein the slot antenna is configured as a rectilinear slot antenna. In Example 1610, the subject matter of any one or more of Examples 1607–1609 optionally include wherein the first feed mechanism is configured within the PCB and comprises a first set of two orthogonal feed lines coupled to the transceiver and to the driven element of the first antenna. In Example 1611, the subject matter of any one or more of Examples 1607-1610 optionally include wherein second feed mechanism is configured within the PCB and comprises a second set of two orthogonal feed lines coupled to the transceiver and to the second antenna wherein the second antenna is fed from the two orthogonal feed lines by proximity coupling. In Example 1612, the subject matter of any one or more of Examples 1607–1611 optionally include wherein the second antenna comprises a ground for the first antenna. Example 1613 is apparatus of a mobile device, the apparatus comprising: a substrate; an integrated circuit (IC) connected to the substrate; a transceiver configured within the IC to generate radio frequency (RF) signals; a conductive shield connected to the substrate, covering the IC, and configured to protect the IC from interference; an antenna director configured on or within a chassis external to the substrate; an antenna configured on or within a surface mounted device (SMD); and dual orthogonal feed mechanisms coupled to the transceiver and to the antenna wherein the antenna is configured to transmit the RF signals in two orthogonal polarizations to interact with the antenna director, and wherein the antenna director is configured to direct the RF signals. In Example 1614, the subject matter of Example 1613 optionally includes wherein the conductive shield is configured to serve as a ground plane for the antenna. In Example 1615, the subject matter of any one or more of Examples 1613-1614 optionally include wherein the antenna comprises a dual element patch antenna wherein a first of the dual elements is a driven capacitive patch antenna element and a second of the dual elements is a parasitic patch antenna element. In Example 1616, the subject matter of Example 1615 optionally includes further comprising a ground plane for the antenna, the ground plane configured within the substrate. In Example 1617, the subject matter of any one or more of Examples 1613–1616 optionally include further comprising a cross-hatched patterned capacitive patch antenna and a cross-hatched patterned ground plane for the cross-hatched patterned capacitive patch antenna, the cross-hatched patterned capacitive patch antenna and the cross-hatched patterned ground plane being configured on or within the SMD. Example 1618 is apparatus of a mobile device, the apparatus comprising: a substrate; an integrated circuit (IC) connected to the substrate; a transceiver configured within the IC to generate radio frequency (RF) signals; a conductive shield connected to the substrate, covering the IC, and configured to protect the IC from interference; an antenna director configured on or within a chassis external to the substrate; an antenna configured on or within a surface mounted device (SMD); and a single feed mechanism coupled to the transceiver and to the antenna wherein the antenna is configured to transmit the RF signals in a single polarization to interact with the antenna director, and wherein the antenna director is configured to direct the RF signals. In Example 1619, the subject matter of Example 1618 optionally includes wherein the antenna comprises a spiral antenna configured within the SMD, the spiral antenna comprising connected traces and vias on or within the SMD, and wherein the shield is configured as a reflector and as a ground plane for the spiral antenna. In Example 1620, the subject matter of any one or more of Examples 1618-1619 optionally include wherein the antenna comprises a patch antenna configured on or within the SMD, and the shield is configured as a reflector and as a ground plane for the patch antenna. Example 1621 is apparatus of a mobile device, the apparatus comprising: a substrate; an integrated circuit (IC) connected to the substrate; a transceiver configured within the IC to generate radio frequency (RF) signals; a conductive shield connected to the substrate, covering the IC, and configured to protect the IC from interference; a plurality of antenna directors configured on or within a chassis external to the substrate; a plurality of antenna elements that comprise an antenna array configured on or within a respective surface mounted device (SMD), or configured on or within the substrate; and a feed mechanism coupled to the transceiver and to each of the plurality of antenna elements of the antenna array, wherein each of the plurality of antenna elements of the antenna array is configured to transmit the RF signals to interact with the plurality of antenna directors, and wherein the plurality of antenna directors is configured to direct the RF signals. In Example 1622, the subject matter of Example 1621 optionally includes wherein the feed mechanism comprises a plurality of feed elements configured to feed the plurality of antenna elements with the RF signals in a single polarity wherein the antenna array transmits the RF signals in the single polarity. In Example 1623, the subject matter of any one or more of Examples 1621-1622 optionally include wherein the feed mechanism comprises a plurality of dual orthogonal feed elements configured to feed the plurality of antenna elements with the RF signals in a first polarity and a second polarity that is orthogonal to the first polarity, wherein the antenna array transmits the RF signals in the first polarity and in the second polarity. Example 1624 is apparatus of a mobile device, the apparatus comprising: a substrate comprising a first layer and a second layer; a radio front end module (RFEM) attached to the first layer of the substrate and comprising an integrated circuit (IC) that is configured to generate radio frequency (RF) signals; a conductive shield that covers the IC, is attached to the first layer of the substrate, and is configured to protect the IC from interference; a surface mounted device (SMD) coupled to the substrate adjacent the conductive shield; and at least one directional monopole antenna that includes a first arm that comprises a metalized via connected to the RFEM and extending into the SMD perpendicularly to the substrate, wherein the directional monopole antenna is fed by at least one feed mechanism that is part of the substrate and is coupled to the IC, wherein the directional monopole antenna is configured to transmit the RF signals in a first polarity in a direction outward from the RFEM, and wherein the conductive shield is a reflector for the directional monopole antenna. In Example 1625, the subject matter of Example 1624 optionally includes wherein the via extends through the SMD to the top of the SMD. In Example 1626, the subject matter of Example 1625 optionally includes wherein the first arm further comprises a metal trace configured on the top layer of the SMD, perpendicular to and connected to the via that extends through the SMD to the top of the SMD. Example 1627 is apparatus of a mobile device, the apparatus comprising: a substrate comprising a first layer and a second layer; an integrated circuit (IC) attached to the first layer of the substrate and configured to generate radio frequency (RF) signals; a conductive shield that covers the IC, is attached to the first layer of the substrate, and is configured to protect the IC from interference; a plurality of antenna arrays each comprising a plurality of directional monopole antenna elements adjacent the conductive shield that is a reflector for the directional monopole antennas; and a plurality of second arrays each comprising a plurality of directional dipole antenna elements parallel to the second layer that is a ground plane for the plurality of directional dipole antennas, wherein the plurality of monopole antenna elements and the plurality of dipole antenna elements are respectively located adjacent each other, and wherein each of the plurality of monopole antennas is configured to transmit the RF signals in a first polarization and each of the plurality of dipole antennas is configured to transmit the RF signals in a second polarization that is orthogonal to the first polarization. In Example 1628, the subject matter of Example 1627 optionally includes wherein each of the plurality of monopole antenna elements includes a first arm that comprises a metalized via that extends into a respective surface mounted device (SMD) perpendicular to the substrate, wherein each of the plurality of monopole antennas is fed by a feed mechanism that is configured as part of the substrate and is coupled to the IC to feed RF signals to the plurality of monopole antennas, and wherein the directional dipole antennas are fed by a feed mechanism that is configured as part of the substrate and is coupled to the IC to feed RF signals to the plurality of dipole antennas. In Example 1629, the subject matter of Example 1628 optionally includes wherein the vertical arm of at least one of the plurality of monopole antennas extends to the top of the respective SMD of the at least one of the plurality of monopole antennas, and the vertical arm of the at least one of the plurality of monopole antennas further comprises a metal trace configured on the top of the respective SMD, perpendicular to and connected to the metalized via. Example 1630 is apparatus for a mobile device, the apparatus comprising: a substrate; an integrated circuit (IC) connected to the substrate, the IC comprising a transceiver that includes a transmitter (TX) configured to generate first radio frequency (RF) signals and a receiver (RX) configured to process received second RF signals, wherein the TX and RX operate at different times, wherein the TX comprises a power amplifier (PA) that is coupled to a first feed mechanism and the RX comprises a low noise amplifier (LNA) that is coupled to a second feed mechanism; and a dual feed antenna configured on the substrate, wherein the dual feed antenna includes a TX feedline matching point and an RX feedline matching point, wherein the first feed mechanism is directly connected to the TX feedline matching point of the dual feed antenna and the second feed mechanism is directly connected to the RX feedline matching point of the dual feed antenna, wherein the first RF signals are transmitted by the dual feed antenna and the second RF signals are received by the dual feed antenna. In Example 1631, the subject matter of Example 1630 optionally includes wherein the dual feed antenna is a patch antenna, the first feed mechanism is a first single polarization feed line configured to transmit the first RF signals in a single polarization, and the second feed mechanism is a second single polarization feed line configured to receive the second RF signals in a single polarization. In Example 1632, the subject matter of any one or more of Examples 1630-1631 optionally include wherein the dual feed antenna is a patch antenna, the first feed mechanism comprises a first dual orthogonal feed mechanism configured to transmit the first RF signals in dual orthogonal polarizations, and the second feed mechanism comprises a second dual orthogonal feed mechanism configured to receive the second RF signals in dual orthogonal polarizations. Example 1633 is apparatus of a mobile device, the apparatus comprising: a substrate; a plurality of antenna arrays configured on the substrate; an integrated circuit (IC) shield comprising a first section affixed to the substrate and a cover connected to the first section; and an IC connected to the substrate and situated within the first section, wherein an area of the cover is configured to be a reflector of the antenna array to improve the gain of the antenna, wherein a part of the first section extends through a space in the cover to extend the cover area that is configured to be a reflector of the antenna array, and wherein the extended area is configured to be a reflector for at least one of the plurality of antenna arrays. In Example 1634, the subject matter of Example 1633 optionally includes wherein the plurality of antenna arrays comprises a plurality of patch antenna elements and a plurality of dipole antenna elements. Example 1635 is apparatus of a mobile device, the apparatus comprising: a substrate; a radio front end module (RFEM) connected to the substrate and comprising an integrated circuit (IC) configured to generate radio frequency (RF) signals; an antenna array fed by a feeding mechanism coupled to the IC wherein the antenna array is configured to transmit the RF signals; a conductive IC shield that covers the IC; an obstruction adjacent the antenna array that interferes with antenna array transmission; and an interposer coupled to the substrate, wherein the antenna array and the conductive IC shield are mounted on the interposer and wherein the interposer provides height to improve antenna array transmission. In Example 1636, the subject matter of Example 1635 optionally includes wherein the conductive shield is configured as a reflector for the antenna array. In Example 1637, the subject matter of any one or more of Examples 1635-1636 optionally include wherein the antenna array comprises a plurality of patch antennas. In Example 1638, the subject matter of Example 1635 optionally includes wherein the antenna array comprises a plurality of patch antennas. Example 1639 can include, or can optionally be combined with any portion or combination of any portions of any one or more of Examples 1569 through 1639 to include, subject matter that can include means for performing any one or more of the functions of Examples 1569 through 1639, or a machine-readable medium including instructions that, when performed by a machine, cause the machine to perform any one or more of the functions of Examples 1569 through 1639. Publications, patents, and patent documents referred to in this document are incorporated by reference herein in their entirety, as though individually incorporated by reference. In the event of inconsistent usages between this document and those documents so incorporated by reference, the usage in the incorporated reference(s) are supplementary to that of this document; for irreconcilable inconsistencies, the usage in this document controls. The above description is intended to be illustrative, and not restrictive. For example, the above-described examples (or one or more aspects thereof) may be used in combination with others. Other aspects may be used, such as by one of ordinary skill in the art upon reviewing the above description. The Abstract is to allow the reader to quickly ascertain the nature of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims. Also, in the above Detailed Description, various features may be grouped together to streamline the disclosure. However, the claims may not set forth every feature disclosed herein as aspects may feature a subset of said features. Further, aspects may include fewer features than those disclosed in a particular example. Thus, the following claims are hereby incorporated into the Detailed Description, with a claim standing on its own as a separate aspect. The scope of the aspects disclosed herein is to be determined with reference to the appended claims, along with the full scope of equivalents to which such claims are entitled. , C , C , Claims:WE CLAIM: 1. A transceiver system comprising: a plurality of patch antennas, the plurality of patch antennas disposed on a first surface of a substrate; a radio frequency integrated circuit (RFIC) coupled to the plurality of patch antennas, the RFIC disposed on a second surface of the substrate and configured to process RF signals received via the plurality of patch antennas; and a shielding element, the shielding element insulating the RFIC from radio frequency interference (RFI) and electromagnetic interference (EMI). 2. The transceiver system of claim 1, further comprising: a plurality of redistribution layers within the substrate, the plurality of redistribution layers coupling the RFIC to the plurality of patch antennas. 3. The transceiver system of claim 2, further comprising: a plurality of solder balls, the plurality of solder balls disposed between the plurality of redistribution layers and the plurality of patch antennas. 4. The transceiver system of claim 1, further comprising: a plurality of surface-mount devices (SMDs), the plurality of SMDs disposed on the second surface of the substrate, wherein the RFIC is configured to process the RF signals based on one or more of the plurality of SMDs. 5. The transceiver system of claim 4, further comprising: mold compound, the mold compound disposed within a cavity formed between the shielding element and the substrate. 6. The transceiver system of claim 1, wherein each patch antenna of the plurality of patch antennas is configured as a dual-polarized antenna structure with ± 45° tilted excitation. 7. The transceiver system of claim 1, wherein each patch antenna of the plurality of patch antennas is configured as parasitically stacked dual patches. 8. The transceiver system of claim 7, wherein the parasitically stacked dual patches comprise: a driven element coupled to a feedline; and a parasitic element. 9. The transceiver system of claim 1, further comprising: a horizontal surface-mount device (SMD) element. 10. The transceiver system of claim 9, wherein the horizontal SMD element comprises at least one patch antenna of the plurality of patch antennas. 11. The transceiver system of claim 10, wherein the at least one patch antenna comprises: a parasitic patch element; and a driven capacitive patch antenna element coupled to dual feed lines.