An area aware schematic design system 200 that analyses an area of one or more components in a schematic circuit using scripting tools to generate an optimised component placement layout design for designing the schematic circuit is provided. The area aware schematic design system 200 includes one or more modules as...

A method to convert lock-free algorithm to wait-free using a hardware accelerator includes (i) executing a plurality of software threads by a plurality of processing units associated, the plurality of software threads is associated with at least one operation, (ii) generating at least one of a read request or a writ...

Disclosed herein is a method for automatic gain control based on signal spectrum sensing. Spectral sensing techniques may be employed to detect the presence or absence of interference and also determine a frequency location of the interference and power level estimates of a desired signal. The method includes runnin...

A smart antenna system for achieving circularly polarized and electrically down tilted phased array signals is provided. The baseband transmitter (302) transmits a baseband signal. The first voltage controlled oscillator (a) modulates the baseband signal to a plurality of phase shifted intermediate frequency signals...

A method of controlling and maintaining a constant slew rate at an output of a buffer 202 is provided. The method includes the following steps: (a) receiving, (i) a first input signal and (ii) at least one of a control voltage using the buffer 202; (b) generating a threshold voltage using a first reference voltage g...

A system and method of synthesizing impedance in a radio frequency (RF) circuit includes a passive mixer. The passive mixer is operable to receive a first signal at a radio frequency, perform down-conversion of the first signal into an intermediate frequency. The system includes an analogue to digital converter to c...

A system and method for performing channel estimation includes a sampling device for sampling a chip based radio signal to generate a plurality of samples. Further, the system includes a coarse path searcher for performing correlation operations of a local pattern with a time shifted first set of samples to obtain c...

METHOD AND SYSTEM FOR LINEARIZING A RADIO FREQUENCY POWER AMPLIFIER ABSTRACT A method and system for linearizing a Radio Frequency Power Amplifier (RFPA) is disclosed. The method comprises calibrating signals in the RFPA to linearize the RFPA, using at least one of a first signal, a second signal, a third signal...

A method and system for protecting low voltage devices driven by a high voltage circuit is disclosed. The method comprises monitoring an output voltage, from a high voltage block, to a low voltage block. The method further comprises comparing the output voltage with a range of voltages allowable for driving the low ...

A method for performing cyclic redundancy check of an input data stream includes a) obtaining plurality of segmentsof the input data stream, b) computing a CRC for each of the plurality of segments for obtaining a plurality of partial CRCs, c) initializing a register with a partial CRC of Nth segment of the pluralit...

Disclosed is a receiver (100) for enhancing estimation of a channel of a received signal. The receiver (100) is being configured to (i) process at least one of (a) power control commands to obtain a pattern of processed power control commands or (b) phase estimation to obtain a pattern of processed phase estimation...

METHODS AND CIRCUITS FOR MONITORING AND REGULATING VOLTAGE ACROSS A LOW VOLTAGE DEVICE DRIVEN BY A LONG LINE CARRYING RADIO FREQUENCY SIGNALS A circuit for regulating a voltage of a high radio frequency line across a low voltage device 112 is provided. The circuit includes an input port, a high radio frequency line...

A system for implementing a mixed radix fast fourier transformation is disclosed. The system includes a data source 202, a digit-reverse address generator 204, a data memory 206, a register array 208, a control unit 210, a butterfly extraction unit 212, a twiddle factor generator 214, and a computation unit 216. The...

A method of reducing an on-chip memory associated with storing frame buffer in WCDMA receiver includes obtaining, at a WCDMA front end receiver, an signal, transmitting, by an analog to digital convertor, input samples to a digital to digital sigma-delta converter, converting, by a sample rate convertor, a sampling ...

Methods and systems of symbol level interference cancellation at a receiver for multiuser detection is provided. In an embodiment, the method includes performing an interference cancellation based decoding for a plurality of users through a plurality of iterations for generating a plurality of soft bit estimates for...

A system for securing wireless communication between a transmitter 402 and a receiver 404 through a physical layer control and a data channel is disclosed. The transmitter includes a pseudo random sequence generator module 608 and an encryption module 612. The pseudo random sequence generator module 608 receives a p...

[0064] Methods and circuits for maximizing gain of a voltage follower circuit are provided. The method includes using a NMOS voltage replica generation circuit, a PMOS voltage replica generation circuit, a NPN BJT voltage replica generation circuit, a n-channel JFET voltage replica generation circuit, a P-Channel JF...

A single-hop relay cellular system 300 and a multi-hop relay cellular system 400 including frequency links (102A-F), a backhaul link 104, an access link 106, and a relay base station 108 is provided. The relay base station 108 is configured to interchange a frequency of operation between a first frequency carrier 1...

Disclosed herein is a system and a method for estimating frequency offset of LTE using DMRS and CRC. The system includes one or more modules as follows. A digital filtering and FFT unit 106 performs FFT operation on a base band signal. An individual user data extraction unit 108 extracts user data individual. A ...

A system for reducing non-linearity in mixed signal processing using complex polynomial vector processor 102 is provided. The complex polynomial vector processor 102 includes a data processing unit (104) and a co-efficient feeder unit (106). The data processing unit (104) converts a high-speed data stream into a po...

PULSED RADAR SYSTEM AND METHOD WITH DIGITAL MIXER FOR FREQUENCY HOPPING ABSTRACT A radar system (100) for generating a fast frequency hopping output for frequency agility using a transmitter block (102) and a receiver block (106).The transmitter block (102) 5 is configured to (i) modulate a digital signal using a ...

A global navigation satellite system (GNSS) receiver (200) for improving accuracy of a GNSS position estimation using a sigma-delta based fractional interpolation in a delay-locked loop is provided. The GNSS receiver includes a correlator 202, a code phase discriminator 206, a first loop filter 210A, a code numerica...

A method for reducing a memory requirement in an uplink receiver (203) using a Sounding Reference Signal (SRS) channel along with a Demodulation Reference Signal (DMRS) for channel estimation in SC-FDMA/ OFDM based radio access technologies is provided. The method includes (i) requesting the Sounding Reference Signa...

METHOD AND CIRCUIT FOR MATCHING IMPEDANCE AND REGULATING VOLTAGE ACROSS A LOW VOLTAGE DEVICE A circuit for matching impedance and regulating a voltage of a high radio frequency line (102) across a low voltage device that includes a differential input port (104), the high radio frequency lines (102), an internally ...

Acircuit for detecting, controlling, and maintaining optimal output swing for a noise performance at a given power with an improved operating range is provided. The circuit includes a Voltage Controlled Oscillator (VCO) (102), a peak detection circuit (104) and an Analog Bias Controller (108). The VCOincludes a bias...