Description:FIELD OF THE INVENTION

[0001] The present disclosure relates to a communication system, and more particularly, to a system and a method for establishing communication between a plurality of devices.
BACKGROUND

[0002] Generally, a plurality of devices, for example, laptops, vehicles, etc., tend to communicate with each other for various purposes, for example, data transfer, etc. The communication between the plurality of devices is facilitated through various communication channels in embedded systems. The embedded systems include a microcontroller or a microprocessor and are designed to perform specific tasks in the device. Such systems often communicate with other devices to exchange data or to control other devices through a wired or wireless network.
[0003] Further, the embedded systems establish communication between the plurality of devices through one or more communication protocols. Further, the communication protocols are used to define the way that the data is transmitted between the plurality of devices. There are various communication protocols used in embedded systems, each having its own set of advantages and disadvantages. Some of the commonly used communication protocols in embedded systems include Universal Asynchronous Receiver/Transmitter (UART), Serial Peripheral Interface (SPI), Inter-Integrated Circuit (I2C), Controller Area Network (CAN), and Ethernet.
[0004] However, the existing configuration has the limitation that typically, each device is compatible with different communication protocols. Thus, to establish communication between each device having different communication protocols, an additional component, for example, the microcontroller, is required. The additional component is compatible with the different communication protocols and ensures ease of communication between each device. However, this configuration increases the processing time for establishing communication between each device. Further, the existing configuration also increases the possibility of increased data loss while communicating, for example, if one or more bytes of data are corrupted/lost, therefore, a plurality of data packets are discarded during the communication (as shown in Figure 1). This configuration also impacts the efficiency of the embedded system of each device. This configuration also increases the overall cost of the devices.
[0005] Therefore, in view of the above-mentioned problems, it is desirable to provide a system and a method that can eliminate one or more of the above-mentioned problems associated with the existing configuration of the communication between the plurality of devices having different communication protocols.
SUMMARY

[0006] This summary is provided to introduce a selection of concepts, in a simplified format, that is further described in the detailed description of the invention. This summary is neither intended to identify key or essential inventive concepts of the invention and nor is it intended for determining the scope of the invention.
[0007] In an embodiment, the present disclosure discloses a system for establishing communication between a plurality of devices. The system includes a plurality of processors. The plurality of processors may be communicatively coupled to a plurality of devices. The plurality of processors is configured to be communicatively coupled with each other. At least a second processor amongst the plurality of processors is configured to receive an input signal indicative of at least one data packet, from a first processor from the plurality of processors. The at least second processor is configured to arrange the at least one data packet in a predefined sequence, on a ring buffer. The at least second processor is configured to transfer the arranged at least one data packet in the predefined sequence, to a linear buffer. The at least second processor is configured to perform one or more data parsing operations on the transferred arranged at least one data packet in the linear buffer to establish an optimal communication between the plurality of devices.
[0008] In another embodiment, a method is disclosed. The method includes receiving, by at least a second processor, an input signal indicative of at least one data packet, from a first processor from the plurality of processors. The method includes arranging, by the at least second processor, the at least one data packet in a predefined sequence, on a ring buffer. The method includes transferring, by the at least second processor, the arranged at least one data packet in the predefined sequence, to a linear buffer. The method includes performing, by the at least second processor, one or more data parsing operations on the transferred arranged at least one data packet in the linear buffer to establish an optimal communication between the plurality of devices.
[0009] The present configuration also ensures reduced load on the plurality of processors after incorporating the direct memory access, interrupts, the ring buffer, and the linear buffer, thus, ensuring the efficiency of the system. The present configuration ensures packetization and de-packetization of the at least one data packet through the system. Further, the system also uses the ring buffer which increases processing of the at least one data packet at a higher speed. Further, the system includes the pair of pointers which ensures the reading and writing of the at least one data packet on the linear buffer simultaneously which ensures saving memory of the linear buffer, thus increasing the speed and efficiency of the system.
[0010] To further clarify the advantages and features of the present invention, a more particular description of the invention will be rendered by reference to specific embodiments thereof, which are illustrated in the appended drawings. It is appreciated that these drawings depict only typical embodiments of the invention and are therefore not to be considered limiting of its scope. The invention will be described and explained with additional specificity and detail with the accompanying drawings.
BRIEF DESCRIPTION OF THE DRAWINGS

[0011] These and other features, aspects, and advantages of the present invention will become better understood when the following detailed description is read with reference to the accompanying drawings in which like characters represent like parts throughout the drawings, wherein:
[0012] Figure 1 illustrates a plurality of data packets as per existing art;
[0013] Figure 2 illustrates an environment of a system having a plurality of processors communicatively coupled to a plurality of devices, according to an embodiment of the present disclosure;
[0014] Figure 3 illustrates a block diagram of a first control unit having a first processor from the plurality of processors and a second control unit having a second processor from the plurality of processors, according to an embodiment of the present disclosure;
[0015] Figures 4A-4B illustrate a flow of at least one data packet for one or more parsing operations, according to an embodiment of the present disclosure;
[0016] Figures 5A-5B illustrate a flowchart depicting the one or more parsing operations, according to an embodiment of the present disclosure;
[0017] Figures 6 (i-ii) illustrate different types of the at least one data packet, according to an embodiment of the present disclosure;
[0018] Figure 7A illustrates a discarded data packet, according to an embodiment of the present disclosure;
[0019] Figure 7B (i) illustrates an example depicting at least one data packet, according to an embodiment of the present disclosure;
[0020] Figure 7B(ii) illustrates an example of discarding of the data packet in the existing art;
[0021] Figure 7B(iii) illustrates an example of discarding of the data packet by the system, according to an embodiment of the present disclosure;
[0022] Figure 8 illustrates at least a pair of pointers of the system, according to an embodiment of the present disclosure; and
[0023] Figure 9 illustrates a flowchart depicting a method to establish communication between the plurality of devices, according to an embodiment of the present disclosure.
[0024] Further, skilled artisans will appreciate that elements in the drawings are illustrated for simplicity and may not have necessarily been drawn to scale. For example, the flow charts illustrate the method in terms of the most prominent steps involved to help to improve understanding of aspects of the present invention. Furthermore, in terms of the construction of the device, one or more components of the device may have been represented in the drawings by conventional symbols, and the drawings may show only those specific details that are pertinent to understanding the embodiments of the present invention so as not to obscure the drawings with details that will be readily apparent to those of ordinary skill in the art having the benefit of the description herein.
DETAILED DESCRIPTION OF FIGURES

[0025] For the purpose of promoting an understanding of the principles of the present disclosure, reference will now be made to the various embodiments and specific language will be used to describe the same. It will nevertheless be understood that no limitation of the scope of the present disclosure is thereby intended, such alterations and further modifications in the illustrated system, and such further applications of the principles of the present disclosure as illustrated therein being contemplated as would normally occur to one skilled in the art to which the present disclosure relates.
[0026] It will be understood by those skilled in the art that the foregoing general description and the following detailed description are explanatory of the present disclosure and are not intended to be restrictive thereof.
[0027] Whether or not a certain feature or element was limited to being used only once, it may still be referred to as “one or more features” or “one or more elements” or “at least one feature” or “at least one element.” Furthermore, the use of the terms “one or more” or “at least one” feature or element do not preclude there being none of that feature or element, unless otherwise specified by limiting language including, but not limited to, “there needs to be one or more…” or “one or more elements is required.”
[0028] Reference is made herein to some “embodiments.” It should be understood that an embodiment is an example of a possible implementation of any features and/or elements of the present disclosure. Some embodiments have been described for the purpose of explaining one or more of the potential ways in which the specific features and/or elements of the proposed disclosure fulfil the requirements of uniqueness, utility, and non-obviousness.
[0029] Use of the phrases and/or terms including, but not limited to, “a first embodiment,” “a further embodiment,” “an alternate embodiment,” “one embodiment,” “an embodiment,” “multiple embodiments,” “some embodiments,” “other embodiments,” “further embodiment”, “furthermore embodiment”, “additional embodiment” or other variants thereof do not necessarily refer to the same embodiments. Unless otherwise specified, one or more particular features and/or elements described in connection with one or more embodiments may be found in one embodiment, or may be found in more than one embodiment, or may be found in all embodiments, or may be found in no embodiments. Although one or more features and/or elements may be described herein in the context of only a single embodiment, or in the context of more than one embodiment, or in the context of all embodiments, the features and/or elements may instead be provided separately or in any appropriate combination or not at all. Conversely, any features and/or elements described in the context of separate embodiments may alternatively be realized as existing together in the context of a single embodiment.
[0030] Any particular and all details set forth herein are used in the context of some embodiments and therefore should not necessarily be taken as limiting factors to the proposed disclosure.
[0031] The terms “comprises”, “comprising”, or any other variations thereof, are intended to cover a non-exclusive inclusion, such that a process or method that comprises a list of steps does not include only those steps but may include other steps not expressly listed or inherent to such process or method. Similarly, one or more devices or sub-systems or elements or structures or components proceeded by “comprises... a” does not, without more constraints, preclude the existence of other devices or other sub-systems or other elements or other structures or other components or additional devices or additional sub-systems or additional elements or additional structures or additional components.
[0032] Embodiments of the present disclosure will be described below in detail with reference.
[0033] Figure 2 illustrates an environment of a system 100 having a plurality of processors 210, 212 communicatively coupled to a plurality of devices 204, 206, according to an embodiment of the present disclosure.
[0034] In an embodiment, at least one of the plurality of devices 204, 206 may be a vehicle without departing from the scope of the present disclosure. In another embodiment, the at least one of the plurality of devices 204, 206 may be electronic devices, etc., without departing from the scope of the present disclosure. In an embodiment, the plurality of devices 204, 206 may include a first device 204 and a second device 206, without departing from the scope of the present disclosure.
[0035] In an embodiment, each of the first device 204 and the second device 206 may be equipped with the system 200, without departing from the scope of the present disclosure. In another embodiment, the system 200 may be implemented on a cloud-based server in communication with each of the first device 204 and the second device 206, without departing from the scope of the present disclosure. The system 200 ensures the communication between each of the first device 204 and the second device 206.
[0036] In such an embodiment, the system 200 may be configured to establish communication between the plurality of processors 210, 212 having different communication protocols. Thus, this configuration also results in establishing communication between the plurality of devices 204, 206.
[0037] In an embodiment, the system 200 may include, but is not limited to, the plurality of processors 210, 212 as will be explained in detail further below, without departing from the scope of the present disclosure.
[0038] The constructional and operational aspects of the system 200 having the plurality of processors 210, 212 may be explained with reference to Figures 3A-7B(iii) in conjunction with Figure 2.
[0039] Figure 3 illustrates a block diagram of a first control unit 302 including a first processor 210 from the plurality of processors 210, 212 and a second control unit 304 including a second processor 212 from the plurality of processors 210, 212, according to an embodiment of the present disclosure. Figures 4A-4B illustrate a flow of at least one data packet 402 for one or more parsing operations 410, according to an embodiment of the present disclosure. Figures 5A-5B illustrate a flowchart depicting the one or more parsing operations 410, according to an embodiment of the present disclosure. Figures 6(i-ii) illustrate different types of the at least one data packet 402, according to an embodiment of the present disclosure. Figure 7A illustrates a discarded data packet, according to an embodiment of the present disclosure. Figure 7B (i) illustrates an example depicting a data packet, according to an embodiment of the present disclosure. Figure 7B(ii) illustrates an example of discarding of the data packet in the existing art. Figure 7B(iii) illustrates an example of discarding of the data packet by the system 200, according to an embodiment of the present disclosure.
[0040] In an embodiment, the plurality of processors 210, 212 may be communicatively coupled to the plurality of devices 204, 206. In an embodiment, the plurality of processors 210, 212 may be configured to be communicatively coupled with each other. Further, at least the second processor 212 (referred to here as the second processor 212) may be configured to perform operations to establish communication between the plurality of processors 210, 212 having the different communication protocols and ultimately between the plurality of devices 204, 206, without departing from the scope of the present disclosure. In another embodiment, the first processor 210 may be configured to perform the operations to establish communication between the plurality of processors 210, 212 having the different communication protocols and ultimately, between the plurality of devices 204, 206, without departing from the scope of the present disclosure.
[0041] In an embodiment, the first processor 210 may be deployed in the first control unit 302, where the first control unit 302 may be communicatively coupled with the first device 204, without departing from the scope of the present disclosure. Further, the second processor 212 may be deployed in the second control unit 304, where the second control unit 304 may be communicatively coupled with the second device 206, without departing from the scope of the present disclosure. Furthermore, the first control unit 302 may be communicatively coupled with the second control unit 304, without departing from the scope of the present disclosure.
[0042] Further, the first control unit 302 may include (i) a microcontroller core (or the first processor) 210; (ii) memory 312; (iii) module(s) 314, and (iv) communication protocols including, but not limited to a CAN protocol, Serial Communication Interface (SCI) protocol and so on. The sequence of programmed instructions and data associated therewith can be stored in a non-transitory computer-readable medium such as the memory 312 or a storage device which may be any suitable memory apparatus such as, but not limited to read-only memory (ROM), programmable read-only memory (PROM), electrically erasable programmable read-only memory (EEPROM), random-access memory (RAM), flash memory, disk drive, and the like. In one or more embodiments of the disclosed subject matter, non-transitory computer-readable storage media can be embodied with a sequence of programmed instructions for monitoring and controlling the operation of different components of the devices.
[0043] The first processor 210 may include any computing system which includes, but is not limited to, a Central Processing Unit (CPU), an Application Processor (AP), a Graphics Processing Unit (GPU), a Visual Processing Unit (VPU), and/or an AI-dedicated processor such as a Neural Processing Unit (NPU). In an embodiment, the processor 226 can be a single processing unit or several units, all of which could include multiple computing units. The processor 210 may be implemented as one or more microprocessors, microcomputers, microcontrollers, digital signal processors, central processing units, state machines, logic circuitries, and/or any devices that manipulate signals based on operational instructions.
[0044] Among other capabilities, the first processor 210 is configured to fetch and execute computer-readable instructions and data stored in the memory. The instructions can be compiled from source code instructions provided in accordance with a programming language such as Java, C++, C#.net, or the like. The instructions can also comprise code and data objects provided in accordance with, for example, the Visual Basic™ language, LabVIEW, or another structured or object-oriented programming language. The one or a plurality of processors control the processing of the input data in accordance with a predefined operating rule or artificial intelligence (AI) model stored in the non-volatile memory and the volatile memory. The predefined operating rule or artificial intelligence model is provided through training or learning algorithms which include, but are not limited to, supervised learning, unsupervised learning, semi-supervised learning, or reinforcement learning.
[0045] Furthermore, the modules 314, processes, systems, and devices can be implemented as a single processor or as a distributed processor. Also, the processes, modules 314, and sub-modules described in the various figures of and for embodiments herein may be distributed across multiple computers or systems or may be co-located in a single processor or system. Further, the module 314 can be implemented in hardware, instructions executed by the first processor 210, or by a combination thereof. A processing unit can comprise a computer, the first processor 210, a state machine, a logic array, or any other suitable devices capable of processing instructions.
[0046] The first processor 210 can be a general-purpose processor which executes instructions to cause the general-purpose processor to perform the required tasks or, the processing unit can be dedicated to performing the required functions. In another embodiment of the present disclosure, the modules 314 may be machine-readable instructions (software) which, when executed by the processor/processing unit, perform any of the described functionalities. In an embodiment, the modules 314 may include a positioning module 316. The data serves, amongst other things, as a repository for storing data processed, received, and generated by the modules 314.
[0047] Further, elements of the second control unit 304 include (i) the microcontroller core (or the second processor (s)) 212; (ii) memory 318; (iii) module(s) 320, and (iv) communication protocols including, but not limited to a CAN protocol, Serial Communication Interface (SCI) protocol and so on. The configuration of the processor 212, the memory 318, and the communication protocols are same as that of the first control unit 302. Accordingly, a detailed description of the same is omitted herein for the sake of brevity of the present disclosure. Further, the modules 320 may include a receiving module 322, a sequencing module 324, a transferring module 326, a performing module 328, a determining module 330, a monitoring module 332, a comparing module 334, a padding module 336, an identifying module 338, and a discarding module 340.
[0048] In the illustrative embodiment, the first processor 210, in conjunction with the positioning module 316 along with the memory 318, the second processor 212 in conjunction with the receiving module 322, the sequencing module 324, the transferring module 326, the performing module 328, the determining module 330, the monitoring module 332, the comparing module 334, the padding module 336, the identifying module 338, and the discarding module 340 are configured to perform the specific operations to establish communication between the plurality of processors 210, 212 having the different communication protocols and ultimately between the plurality of devices 204, 206. Further, the specific operations to establish communication between the plurality of devices 204, 206 are explained in the subsequent paragraphs.
[0049] In an embodiment, the positioning module 316 may be configured to position the at least one data packet 402 (depicted in Figure 4A) in a predetermined format before sending an input signal indicative of the at least one data packet 402 to the second processor 212. In such an embodiment, the first processor 210 sends an input signal indicative of data bytes associated with the at least one data packet 402 to the second processor 212. Further, the first processor 210 may send the at least one data packet 402 through a particular communication protocol supported by the first processor 210.
[0050] In an embodiment, at step 412, the second processor 212 determines whether the input signal indicative of the at least one data packet 402 from the first processor 210 is received by the receiving module 322. In such an embodiment, the second processor 212 may have a different communication protocol than the first processor 210. In an embodiment, if the receiving module 322 does not receive the input signal indicative of the at least one data packet 402 from the first processor 210, the second processor 212 waits for the input signal indicative of the at least one data packet 402 from the first processor 210.
[0051] Further, if the receiving module 322 receives the input signal indicative of the at least one data packet 402 from the first processor 210, further operations are executed, which are explained in subsequent paragraphs.
[0052] In an embodiment, at step 414, a direct memory access (DMA) may be configured to trigger an interrupt in the at least one data packet 402, before arranging the at least one data packet 402 in a predefined sequence, on a ring buffer 404. In an embodiment, the ring buffer 406 may be stored in the memory 318, without departing from the scope of the present disclosure. In another embodiment, the ring buffer 406 may form a part of the memory 318, without departing from the scope of the present disclosure. In an embodiment, the at least one data packet 402 may be of 20 bytes, without departing from the scope of the present disclosure. This configuration ensures the efficient working of the second processor 212 as the second processor 212 does not have to perform multiple operations to receive the input signal indicative of the at least one data packet 402 from the first processor 210. Further, at that instance, the second processor 212 may be also used for executing alternate functions in the second control unit 304.
[0053] In an embodiment, at step 416, after the triggering of the interruption, the sequencing module 324, may be configured to arrange the at least one data packet 402 in the predefined sequence on the ring buffer 406. For example, there are multiple data packets that are transferred from the first processor 210. Once received, each data packet may be arranged in the predefined sequence on the ring buffer 406. Additionally, if one data packet contains 6 bytes, then, the predefined sequence associated with the one data packet may be completed only when all the 6 bytes may be received from the first processor 210. Further, once the at least one data packet 402 is arranged in the predefined sequence, further operations as mentioned in the subsequent paragraphs are performed.
[0054] In an embodiment, the transferring module 326, at step 418, may be configured to transfer the arranged at least one data packet 402 in the predefined sequence, to a linear buffer 408. In such an embodiment, the at least one data packet 402 may be positioned linearly and sequentially in the linear buffer 408, without departing from the scope of the present disclosure. Further, at step 420, the performing module 328 may be configured to perform the one or more data parsing operations 410 on the transferred arranged at least one data packet 402 in the linear buffer 408 to establish an optimal communication between the plurality of processors 210, 212 having the different communication protocols and ultimately, between the plurality of devices 204. 206. The one or more data parsing operations 410 ensures that the at least one data packet 402 may be formed into a standard packet format and thus, being compatible with the communication protocol of the second processor 212. The communication protocol of the second processor 212 may be different from the communication protocol of the first processor 210. Thus, this configuration ensures the establishment of communication between the plurality of processors 210, 212 having the different communication protocols and thus, ultimately establishing the optimal communication between the plurality of devices 204, 206.
[0055] In an embodiment, the abovementioned steps (412 to 416) of the operations are executed by the memory 318 in conjunction with the receiving module 322, the sequencing module 324 as mentioned, without departing from the scope of the present disclosure. Further, the subsequent steps (418 to 420) of the operations as explained in the subsequent paragraphs are executed by the transferring module 326, the performing module 328 in conjunction with the second processor 212. This configuration ensures an increase in the efficiency of the second processor 212, consequently increasing the efficiency of the system 200. Further, the one or more data parsing operations 410 is explained in detail in subsequent paragraphs.
[0056] In an embodiment, referring to Figure 5A, at step 502, the one or more data parsing operations 410 may be started. Further, the determining module 330 may be configured to determine a start of frame/text (STX) of the at least one data packet 402. In such an embodiment, the frame indicates frame of the at least one data packet 402. In an embodiment, at step 504, the monitoring module 332 may be configured to monitor a status of the STX. In such an embodiment, the status may be indicative if the STX may be valid or an invalid. If the status of the STX is invalid, then the monitoring module 332 may monitor and wait for the valid STX, as shown in step 506.
[0057] In an embodiment, when the STX valid is valid, then at step 508, the determining module 330 may be configured to determine at least one packet format depending on at least one parameter of the at least one data packet 402. In such an embodiment, the at least one parameter may be a length of the data packet 402. Further, the at least one packet may be a one of a fixed/standard packet format (as shown in Figure 6(i)) or a dynamic packet format (as shown in Figure 6(ii)). The fixed/standard packet format and the dynamic packet format are provided in tables 1 and 2 below:
PACKET_TYPE Value DLC
STANDARD_PACKET/FIXED_PACKET 0x01 Fixed size
DYNAMIC_PACKET 0x02 Unknown size
Table 1
Flag Value
1 More incoming data
0 No more incoming data
Table 2
[0058] In an embodiment, referring to Figure 5B, when the determined at least one packet format is the fixed packet format, then, at step 510, the determining module 330 may be configured to determine a Protocol ID, DLC, and data associated with the at least one data packet 402. In such an embodiment, the fixed packet format may include STX, PACKET_TYPE (Standard or Dynamic), the Protocol ID, Data Link Control (DLC), data, and a Cyclic Redundancy Check (CRC), without departing from the scope of the present disclosure. Particularly, the at least one data packet 402 may be parsed, and the determining module 330 may be configured to determine the Protocol ID, the DLC, and the data associated with the at least one data packet 402. Further, after determining the Protocol ID, the DLC, and the data associated with the at least one data packet 402, the second processor 212 decodes the at least one data packet 402. Further, the determining module 330 may be configured to determine an operational value of the Cyclic Redundancy Check (CRC) of the at least one data packet 402, based on the determined at least one packet format.
[0059] Similarly, when the determined at least one packet format is the dynamic packet format, then, at step 512, the determining module 330 may be configured to determine a Protocol ID of the at least one data packet 402. Particularly, the at least one data packet 402 may be parsed and the determining module 330 may be configured to determine the Protocol ID associated with the at least one data packet 402. Further, the determining module 330 may be configured to determine the Protocol ID of the at least one data packet 402, when the data from the at least one data packet 402 may be transferred to the ring buffer 408 after the end of transmission of the at least one data packet 402 may be detected from the communication protocol of the first processor 210. Further, after receiving the Protocol ID, the second processor 212 decodes the at least one data packet 402.
[0060] Particularly, in an embodiment, a length of the at least one data packet 402 in the dynamic data packet is not known. Thus, at step 514, the determining module 330 may be configured to determine the length of the at least one data packet 402 from a depacketized message. In such an embodiment, the at least one data packet 402 may include STX, PACKET_TYPE (Standard or Dynamic), the Protocol ID, data, Flag, and the CRC. Further, the receiving module 322 may receive the data associated with the at least one data packet 402 in portions of ‘n’ bytes, followed by the Flag. The Flag indicates that if the receiving module 322 may receive more data associated with the at least one data packet 402. Further, the determining module 330 may be configured to determine a Flag value associated with the at least one data packet 402 based on the portions of data being received. Further, the receiving module 322 may be configured to continue receiving the data associated with the at least one data packet 402, till the Flag value may be determined to be zero (0), as shown in step 532. Thereafter, the determining module 330 may be configured to determine the operational value of the Cyclic Redundancy Check (CRC) of the at least one data packet 402, after the Flag value becomes 0. Further, if the value of the Flag is different from zero, then the receiving module 322 may again receive the data associated with the at least one data packet 402 in the portions of ‘n’ bytes, followed by the Flag.
[0061] At step 516, the comparing module 334 may be configured to compare the determined length of the at least one data packet 402 with a predetermined length of the at least one data packet 402. Further, after comparison, if the determined length may not be same as the predetermined length, then, at step 520, the padding module 336 may be configured to pad the at least one data packet 402 with a predetermined value, where the predetermined value may be zero. Thereafter, the determining module 330 may be configured to determine the operational value of the Cyclic Redundancy Check (CRC) of the at least one data packet 402, based on the determined at least one packet format.
[0062] Further, if the determined length may be the same as the predetermined length, i.e., n bytes. Thereafter, the determining module 330 may be configured to determine the operational value of the Cyclic Redundancy Check (CRC) of the at least one data packet 402, based on the determined at least one packet format.
[0063] In an embodiment, at step 522, the comparing module 334 may be configured to compare the determined operational value of the CRC with a predetermined operational value of the CRC. In such an embodiment, the determined operational value may be a value determined in a real time by the second processor 212, without departing from the scope of the present disclosure. Further, in an embodiment, the determining module 330 may be configured to determine to monitor the at least data packet 402, further, based on the comparison. In such an embodiment, when the determined operational value of the CRC may be same as the predetermined operational value of the CRC, then, at step 524, the receiving module 322 may be configured to receive another data packet from the first processor 210.
[0064] Further, in an embodiment, when the determined operational value of the CRC may be different from the predetermined operational value of the CRC, this indicates that the data from the at least one data packet 402 may be corrupted/lost. Then, the monitoring module 412 may be configured to monitor further the at least one data packet 402 by discarding the STX. Further, at step 526, the identifying module 338 may be configured to identify subsequent STX in the at least one data packet 402 based on the monitored at least one data packet 402. At step 528, the determining module 330 may be configured to determine whether the identified subsequent STX is valid. If the subsequent STX may not be valid, then, the identifying module 338 may wait for the valid STX, without departing from the scope of the present disclosure. If the subsequent STX may be valid, then, at step 530, the at least one data packet 402 may be considered from the subsequent STX. Simultaneously, the discarding module 340 may be configured to discard the at least one data packet 402, based on the identification of the subsequent STX (as shown in Figure 7A). Particularly, a portion of the at least one data packet 402, before the identified subsequent STX, may be discarded, where the portion may include the corrupted data from the at least one data packet 402. The abovementioned operation is further explained by an example while comparing the abovementioned operation with the existing art, as provided below:
[0065] In one example, a data packet may include a STX, a PACKET_TYPE, a Protocol ID, DLC, Data, and a CRC having a specified value (as shown in Figure 7B(i)). If the determined operational value of the CRC is different from the predetermined operational value of the CRC, then, as per existing art as shown in Figure 7B(ii), the current packet and the next packet of the data may be dropped as the STX of the next data packet may not be identified correctly. This results in the loss of multiple data packets.
[0066] Thus, referring to the abovementioned operation of the present disclosure, if the determined operational value of the CRC is different from the predetermined operational value of the CRC and the subsequent STX is identified, then the portion of the at least one data packet 402 may be discarded till the CRC (as shown in Figure 7B (iii)). This results in the discarding of the portion of the at least one data packet 402 while next data packet continues to be processed unlike as the existing art. This configuration results in an increased efficiency of the system 200. Further, this configuration as disclosed also ensures that the second processor 212 establishes communication with the first processor 210 having different communication protocols, through the standard packet format and ultimately establishes communication between the plurality of devices 204, 206.
[0067] Figure 8 illustrates at least a pair of pointers 802, 804 of the system 200, according to an embodiment of the present disclosure. In an embodiment, the at least one pair of pointers 802, 804 may be a read pointer 802 and a write pointer 804. The at least one pair of pointers 802, 804 may be configured to read and write the formed predefined sequence on the linear buffer 408. The write pointer 804 may be configured to write/transfer the at least one data packet 402 in the linear buffer 408 from the ring buffer 406. Further, in an embodiment, read pointer 802 may be configured to read, i.e., process packet-by-packet, the at least one data packet 402, until both the pointers coincide. This configuration results in decreasing load on the second processor 212.
[0068] Further, in another embodiment, the plurality of processors 210, 212 having the different communication protocols may establish communication through a bridge controller. In another embodiment, the at least one data packet 402 to be transferred from the first processor 210 to the second processor 212 may be packetized into the format supported by the second processor 212 by the bridge controller. Particularly, the at least one data packet 402 may be transferred from the first processor 210 to the second controller 212 through the bridge controller, where the bridge controller executes the same operation as explained from Figures 2 to 7A.
[0069] For example, the at least data packet 402 is transferred between the second processor 212 having Universal Asynchronous Receiver/Transmitter (UART) communication protocols and the first processor 210 having Controller Area Network (CAN) through the bridge controller. In that case, the UART data may be received in a queue using interrupt mode in the bridge controller from the second processor 212. Further, the UART data is transferred using DMA mode and makes a copy of the received data into the ring buffer 406. The data that may be received in the ring buffer 406 may be further arranged into the linear buffer 408. Once, the complete packet of the at least one data packet 402 may be received and arranged in the linear buffer 408, the at least one data packet 402 may be parsed and checked for the corrupt/lost data and data packet format. Particularly, the one or more parsing operations 410 is performed in the bridge controller to parses the at least one data packet 402 to determine Protocol ID, DLC, and data of the UART data and thus convert the UART data into the standard data packet supported by the first processor 210. Further, the converted UART data is transferred over the CAN protocol to the first processor 210, from the bridge controller.
[0070] In another example, the bridge controller may receive the CAN message (CAN ID, DLC, data) from the first processor 210. Further, a CAN parser function assembles a quark short packet by appending STX, PACKET_TYPE and CRC in the CAN message. Further, the assembled packet of the at least one data packet 402 is transferred over the UART protocol to the second processor 210, from the bridge controller.
[0071] The present disclosure also relates to a method to establish communication between the plurality of devices 204, 206 as shown in Figure 9. The order in which the method steps are described below is not intended to be construed as a limitation, and any number of the described method steps may be combined in any appropriate order to execute the method or an alternative method. Additionally, individual steps may be deleted from the method without departing from the spirit and scope of the subject matter described herein.
[0072] The method 900 for establishing the communication between the plurality of devices 204, 206 may be performed by using the system 200 as shown at least in Figures 2 to 8.
[0073] The method 900 begins at step 902 and includes receiving, by at least the second processor 212, an input signal indicative of at least one data packet 402, from the first processor 210 from the plurality of processors 210, 212.
[0074] At step 904, the method 900 includes arranging, by the at least second processor 212, the at least one data packet 402 in the predefined sequence, on the ring buffer 406.
[0075] At step 906, the method 900 includes transferring, by the at least second processor 212, the arranged at least one data packet 402 in the predefined sequence, to the linear buffer 408.
[0076] At step 908, the method 900 includes performing, by the at least second processor, one or more data parsing operations on the transferred arranged at least one data packet 402, to the linear buffer, to establish the optimal communication between the plurality of devices 204, 206.
[0077] The system 200 and the method 900 of the present disclosure ensure the optimal communication between the plurality of devices 204, 206, having different communication protocols, through the standardized data packet format (fixed or dynamic) while ensuring the minimum data loss. This configuration eliminates the need of the additional component to establish the communication between the plurality of processors 210, 212 having the different communication protocols, thus, resulting in establishing the communication between the plurality of devices 210, 212. Further, the present configuration ensures checking/parsing of corrupt data from the at least one data packet 402 where a loss of a byte in the at least one data packet 402 discards the single data packet only unlike the existing art, therefore minimizing the data loss. Particularly, the data loss is improved approximately from 20 packets out of 2000 packets/sec to 10 packets/sec using a standard packetizing/de-packetizing process. Further, the throughput increases from 700 packets/sec to 800 packets/sec with the use of DMA.
[0078] Further, the present configuration also ensures reduced load on the plurality of processors 210, 212, after incorporating the direct memory access, interrupts, the ring buffer 406 and the linear buffer 408, thus, ensuring the efficiency of the system 200. The present configuration ensures packetization and de-packetization of the at least one data packet 402 through the system 200. Further, the system 200 also uses the ring buffer 406 which increases processing of the at least one data packet 402 at a higher speed. Further, the system 200 includes the pair of pointers 802, 804 which ensures the reading and writing of the at least data packet 402 on the linear buffer 408 simultaneously which ensures saving memory of the linear buffer 408, thus increasing the speed and efficiency of the system 200.
[0079] It will be appreciated that the modules, processes, systems, and devices described above can be implemented in hardware, hardware programmed by software, software instruction stored on a non-transitory computer-readable medium or a combination of the above. Embodiments of the methods, processes, modules, devices, and systems (or their sub-components or modules), may be implemented on a general-purpose computer, a special-purpose computer, a programmed microprocessor or microcontroller and peripheral integrated circuit element, an ASIC or other integrated circuit, a digital signal processor, a hardwired electronic or logic circuit such as a discrete element circuit, a programmed logic circuit such as a programmable logic device (PLD), programmable logic array (PLA), field-programmable gate array (FPGA), programmable array logic (PAL) device, or the like. In general, any process capable of implementing the functions or steps described herein may be used to implement embodiments of the methods, systems, or computer program products (software program stored on a non-transitory computer readable medium).
[0080] Furthermore, embodiments of the disclosed methods, processes, modules, devices, systems, and computer program product may be readily implemented, fully or partially, in software using, for example, object or object-oriented software development environments that provide portable source code that may be used on a variety of computer platforms. Alternatively, embodiments of the disclosed methods, processes, modules, devices, systems, and computer program product may be implemented partially or fully in hardware using, for example, standard logic circuits or a very-large-scale integration (VLSI) design. Other hardware or software may be used to implement embodiments depending on the speed and/or efficiency requirements of the systems, the particular function, and/or the particular software or hardware system, microprocessor, or microcomputer being utilized.
[0081] In this application, unless specifically stated otherwise, the use of the singular includes the plural and the use of “or” means “and/or.” Furthermore, use of the terms “including” or “having” is not limiting. Any range described herein will be understood to include the endpoints and all values between the endpoints. Features of the disclosed embodiments may be combined, rearranged, omitted, etc., within the scope of the invention to produce additional embodiments. Furthermore, certain features may sometimes be used to advantage without a corresponding use of other features.
, Claims:1. A system for establishing communication between a plurality of devices (204, 206), the system (200) comprising:
a plurality of processors (210, 212) communicatively coupled to a plurality of devices (204, 206);
wherein:
the plurality of processors (210, 212) is configured to be communicatively coupled with each other, wherein at least a second processor (212) amongst the plurality of processors (210, 212) is configured to:
receive an input signal indicative of at least one data packet (402), from a first processor (210) from the plurality of processors (210, 212);
arrange the at least one data packet (402) in a predefined sequence, on a ring buffer (406);
transfer the arranged at least one data packet (402) in the predefined sequence, to a linear buffer (408); and
perform one or more data parsing operations (410) on the transferred arranged at least one data packet (402) in the linear buffer (408) to establish an optimal communication between the plurality of devices (204, 206).

2. The system (200) as claimed in claim 1, wherein, for performing the one or more data parsing operations (410), the at least second processor (212) is configured to:
determine a start of frame (STX) of the at least one data packet (402);
monitor a status of the STX, wherein the status is indicative if the STX is valid or invalid;
determine at least one packet format depending on at least one parameter of the at least one data packet (402), wherein the at least one packet format comprises one of a fixed packet format or a dynamic packet format;
determine an operational value of a Cyclic Redundancy Check (CRC) of the at least one data packet (402), based on the determined at least one packet format;
compare the determined operational value of the CRC with a predetermined operational value of the CRC; and
determine to monitor the at least one data packet (402) further, based on the comparison.

3. The system (200) as claimed in claim 2, wherein the at least one parameter is a length of the at least one data packet (402).

4. The system (200) as claimed in claim 2, wherein when the determined at least one packet format is the fixed packet format, the at least second processor (212) is configured to:
determine a Protocol ID, DLC, and data associated with the at least one data packet (402).

5. The system (200) as claimed in claim 2, wherein when the determined at least one packet format is the dynamic packet format, the at least second processor (212) is configured to:
determine a Protocol ID associated with the at least one data packet (402);
determine a length of the at least one data packet (402);
compare the determined length of the at least one data packet (402) with a predetermined length of the at least one data packet (402); and
padding the at least one data packet (402) with a predetermined value, wherein the predetermined value be zero.

6. The system (200) as claimed in claim 5, wherein when the determined at least one packet format is the dynamic packet format, the at least second processor (212) is configured to:
receive portions of data associated with the at least one data packet (402);
determine a Flag value associated with the at least one data packet based on the portions of data being received; and
continuing to receive the data till the Flag value is determined to be zero.

7. The system (200) as claimed in claim 2, wherein when the determined operational value of the CRC is same as the predetermined operational value of the CRC, the at least second processor (212) is configured to receive another packet data.

8. The system (200) as claimed in claim 2, wherein when the determined operational value of the CRC is different from the predetermined operational value of the CRC, the at least second processor (212) is configured to:
monitor further the at least one data packet (402) by discarding the STX;
identify subsequent STX in the at least one data packet (402) based on the monitored at least one data packet (402); and
discard the at least one data packet (402), based on the identification of the subsequent STX.

9. The system (200) as claimed in claim 1, wherein the at least second processor (212) comprises a direct memory access configured to trigger an interrupt before arranging the at least one data packet (402) in the predefined sequence, on the ring buffer (404).

10. The system (200) as claimed in claim 1, comprises at least a pair of pointers (802, 804) to read and write the formed predefined sequence on the linear buffer (408).

11. The system (200) as claimed in claim 1, wherein the first processor (210) is configured to position the at least one data packet (402) in a predetermined format before sending the input signal indicative of the at least one data packet (402) to the at least second processor (212).

12. A method (900) for establishing communication between a plurality of devices (204, 206), the method (900) comprising:
receiving (902), by at least a second processor (212), an input signal indicative of at least one data packet (402), from a first processor (210) from a plurality of processors (210, 212);
arranging (904), by the at least second processor (212), the at least one data packet (402) in a predefined sequence, on a ring buffer (406);
transferring (906), by the at least second processor (212), the arranged at least one data packet (402) in the predefined sequence, to a linear buffer (408); and
performing (908), by the at least second processor (212), one or more data parsing operations (410) on the transferred arranged at least one data packet (402), inthe linear buffer (408), to establish an optimal communication between the plurality of devices (204, 206).