Manufacturing Method For A Power Semiconductor Device And Power Semiconductor Device

Abstract: The present disclosure relates to a manufacturing method for a power semiconductor device (20), comprising: forming at least one insulating layer (3) on a surface (2a) of a crystalline growth substrate (2), the at least one insulating layer (3) comprising at least one cavity (4) extending in a lateral direction (22) within the at least one insulating layer (3); selectively growing a wide bandgap, WBG, semiconductor material within the cavity (4) to form a lateral epi-layer (9), wherein a surface area of the growth substrate (2) exposed through at least one passage (5) formed between the at least one cavity (4) and the growth substrate (2) is uses as a seed area for epitaxially growing the WBG semiconductor material; and forming at least one semiconductor junction, in particular a pn junction (6), a np junction or a Schottky junction (8), within or at an end of the selectively grown WBG semiconductor material. The disclosure further relates to a power semiconductor device (20) in general, and a MISFET (25) in particular.

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