Abstract: In one embodiment the semiconductor device (1) comprises a semiconductor body (2) a gate electrode (33) and a first electrode (31) wherein the semiconductor body (2) comprises a first region (21) which is a source region or an emitter region and comprises a well region (22) located next to the first region (21) the first region (21) is of a first conductivity type and the well region (22) is of a second conductivity type the well region (22) is separated from the gate electrode (33) by a gate insulator layer (4) the first region (21) is electrically contacted by means of the first electrode (31) in the first region (21) there is at least one current limiting region (5) and the at least one current limiting region (5) is a sub region of the first region (21) with a decreased electrical conductivity.
| # | Name | Date |
|---|---|---|
| 1 | 202547021380-STATEMENT OF UNDERTAKING (FORM 3) [10-03-2025(online)].pdf | 2025-03-10 |
| 2 | 202547021380-REQUEST FOR EXAMINATION (FORM-18) [10-03-2025(online)].pdf | 2025-03-10 |
| 3 | 202547021380-PROOF OF RIGHT [10-03-2025(online)].pdf | 2025-03-10 |
| 4 | 202547021380-NOTIFICATION OF INT. APPLN. NO. & FILING DATE (PCT-RO-105-PCT Pamphlet) [10-03-2025(online)].pdf | 2025-03-10 |
| 5 | 202547021380-FORM 18 [10-03-2025(online)].pdf | 2025-03-10 |
| 6 | 202547021380-FORM 1 [10-03-2025(online)].pdf | 2025-03-10 |
| 7 | 202547021380-DRAWINGS [10-03-2025(online)].pdf | 2025-03-10 |
| 8 | 202547021380-DECLARATION OF INVENTORSHIP (FORM 5) [10-03-2025(online)].pdf | 2025-03-10 |
| 9 | 202547021380-COMPLETE SPECIFICATION [10-03-2025(online)].pdf | 2025-03-10 |
| 10 | 202547021380-FORM-26 [11-03-2025(online)].pdf | 2025-03-11 |
| 11 | 202547021380-FORM 3 [19-09-2025(online)].pdf | 2025-09-19 |