Manufacturing Method For A Power Semiconductor Device And Power Semiconductor Device

Abstract: The present disclosure relates to a manufacturing method for a power semiconductor device (1 40) comprising: forming multiple growth templates on a carrier substrate (2) comprising at least a first plurality of hollow growth templates (18) and a second plurality of hollow growth templates (28); selectively growing a first sequence of differently doped wide bandgap semiconductor materials in each one of the first hollow growth templates (18) thereby forming a corresponding plurality of first semiconductor structures (5) of a first type in particular n+/p /n /n+ structures; and selectively growing a second sequence of differently doped wide bandgap semiconductor materials in each one of the second hollow growth templates (28) thereby forming a corresponding plurality of second semiconductor structures (6) of a second type in particular n+/n /p /n+ structures. The disclosure further relates to a power semiconductor device (1 40) comprising a carrier substrate (2) at least one dielectric layer (4 27 31) a plurality of first semiconductor structures (5) of a first type and a plurality of second semiconductor structures (6) of a second type formed within the at least one dielectric layer (4 27 31).

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