Abstract: In one embodiment, the semiconductor module (10) includes a plurality of semiconductor devices (1) and at least one bus line (5), wherein - each of the semiconductor devices (1) comprises a power semiconductor chip (2), a logic unit (3) and a gate pad (4), each of the power semiconductor chips (2) has a gate electrode contact area (24), - in each one of the semiconductor devices (1), the logic unit (3) is electrically placed between the gate electrode contact area (24) and the gate pad (4), and - the semiconductor devices (1) are interconnected by means of the at least one bus line (5).
| # | Name | Date |
|---|---|---|
| 1 | 202547054008-STATEMENT OF UNDERTAKING (FORM 3) [04-06-2025(online)].pdf | 2025-06-04 |
| 2 | 202547054008-REQUEST FOR EXAMINATION (FORM-18) [04-06-2025(online)].pdf | 2025-06-04 |
| 3 | 202547054008-PROOF OF RIGHT [04-06-2025(online)].pdf | 2025-06-04 |
| 4 | 202547054008-FORM 18 [04-06-2025(online)].pdf | 2025-06-04 |
| 5 | 202547054008-FORM 1 [04-06-2025(online)].pdf | 2025-06-04 |
| 6 | 202547054008-DRAWINGS [04-06-2025(online)].pdf | 2025-06-04 |
| 7 | 202547054008-DECLARATION OF INVENTORSHIP (FORM 5) [04-06-2025(online)].pdf | 2025-06-04 |
| 8 | 202547054008-COMPLETE SPECIFICATION [04-06-2025(online)].pdf | 2025-06-04 |
| 9 | 202547054008-Proof of Right [05-06-2025(online)].pdf | 2025-06-05 |
| 10 | 202547054008-FORM-26 [05-06-2025(online)].pdf | 2025-06-05 |
| 11 | 202547054008-FORM 3 [18-11-2025(online)].pdf | 2025-11-18 |