Abstract: A power semiconductor device (20) is specified, comprising - a drift layer (1) of a first conductivity type, - at least one well region (2) of a second conductivity type being different from the first conductivity type, and - at least one first doped region (3) of the first conductivity type and at least one second doped region (4) of the second conductivity type, wherein - the at least one well region (2), the at least one first doped region (3) and the at least one second doped region (4) are provided at a first side of the power semiconductor device (20), - the at least one first doped region (3) and the at least one second doped region (4) are spaced apart from the drift layer (1) by the at least one well region (2), and - an interface between the at least one first doped region (3) and the at least one second doped region (4) is structured. Further, a method for producing such a power semiconductor device (20) is specified.
| # | Name | Date |
|---|---|---|
| 1 | 202547071952-STATEMENT OF UNDERTAKING (FORM 3) [29-07-2025(online)].pdf | 2025-07-29 |
| 2 | 202547071952-REQUEST FOR EXAMINATION (FORM-18) [29-07-2025(online)].pdf | 2025-07-29 |
| 3 | 202547071952-PROOF OF RIGHT [29-07-2025(online)].pdf | 2025-07-29 |
| 4 | 202547071952-NOTIFICATION OF INT. APPLN. NO. & FILING DATE (PCT-RO-105-PCT Pamphlet) [29-07-2025(online)].pdf | 2025-07-29 |
| 5 | 202547071952-FORM 18 [29-07-2025(online)].pdf | 2025-07-29 |
| 6 | 202547071952-FORM 1 [29-07-2025(online)].pdf | 2025-07-29 |
| 7 | 202547071952-DRAWINGS [29-07-2025(online)].pdf | 2025-07-29 |
| 8 | 202547071952-DECLARATION OF INVENTORSHIP (FORM 5) [29-07-2025(online)].pdf | 2025-07-29 |
| 9 | 202547071952-COMPLETE SPECIFICATION [29-07-2025(online)].pdf | 2025-07-29 |
| 10 | 202547071952-FORM-26 [30-07-2025(online)].pdf | 2025-07-30 |
| 11 | 202547071952-Proof of Right [31-07-2025(online)].pdf | 2025-07-31 |