Abstract: A metal substrate structure (10) for a semiconductor power module comprises a circuit metallization layer (11), a metal bottom layer (13) that coupled with the circuit metallization layer (11), and an isolating dielectric layer (12) that is coupled with and arranged between the circuit metallization layer (11) and the metal bottom layer (13) with respect to a stacking direction (A). The circuit metallization layer (11) or the dielectric layer (12) at least locally forms a top layer of the metal substrate structure (10), and the top layer and the bottom layer (13) comprise a fixation area (18) configured for receiving a fixing element (16) to fix the metal substrate structure (10) to a further component (14) of the semiconductor power module. At least the top layer comprises a stress relief recess (15).
| # | Name | Date |
|---|---|---|
| 1 | 202547091308-STATEMENT OF UNDERTAKING (FORM 3) [24-09-2025(online)].pdf | 2025-09-24 |
| 2 | 202547091308-REQUEST FOR EXAMINATION (FORM-18) [24-09-2025(online)].pdf | 2025-09-24 |
| 3 | 202547091308-PROOF OF RIGHT [24-09-2025(online)].pdf | 2025-09-24 |
| 4 | 202547091308-PRIORITY DOCUMENTS [24-09-2025(online)].pdf | 2025-09-24 |
| 5 | 202547091308-FORM 18 [24-09-2025(online)].pdf | 2025-09-24 |
| 6 | 202547091308-FORM 1 [24-09-2025(online)].pdf | 2025-09-24 |
| 7 | 202547091308-DRAWINGS [24-09-2025(online)].pdf | 2025-09-24 |
| 8 | 202547091308-DECLARATION OF INVENTORSHIP (FORM 5) [24-09-2025(online)].pdf | 2025-09-24 |
| 9 | 202547091308-COMPLETE SPECIFICATION [24-09-2025(online)].pdf | 2025-09-24 |
| 10 | 202547091308-FORM-26 [25-09-2025(online)].pdf | 2025-09-25 |
| 11 | 202547091308-Proof of Right [03-10-2025(online)].pdf | 2025-10-03 |