[0001] The present disclosure relates, generally, to a dynamic random-access memory (DRAM) and a system and device for testing of UnTesTed (uTT) DRAM chips. In particular, it relates to avoidance of occurrence of burnout issues of a DRAM test apparatus during testing of the uTT DRAM chips.

BACKGROUND OF THE INVENTION
[0002] Currently available Dynamic Random Access Memory (DRAM) is categorized in different grades. The DRAM is categorized as being an upgrade (for example, Effectively TesTed (eTT) DRAM chips) or a downgrade DRAM (for example UnTesTed (uTT) DRAM chips). Testing of the downgrade DRAM can be risky as there is a high possibility of occurrence of internal short circuits in DRAM Integrated Circuits (ICs). Due to occurrence of the internal die short circuits - DRAM module PCB, DIMM connector, motherboard DIMM connector and test sockets (herein collectively referred to as a test apparatus hence forth) may get burned, leading to financial losses. The losses may intensify when multiple (e.g., tens of thousands) ICs are tested in the DRAM test apparatus.
[0003] Further, there are additional reasons that may lead to burning of the DRAM module PCB, Dual In-Line Memory Module (DIMM) connector on motherboard, fixture and test socket during testing of the DRAM. The reasons are such as: (a) DRAM ICs internal die is covered and packed with silicon material which blocks determining and finding issues in the internal circuit or of any shorting inside, (b) during mass ICs testing, the DRAM IC may be placed with wrong polarity in a test fixture, (c) during Surface Mount Technology (SMT) production, the ICs may be placed with wrong polarity or due to excess solder paste the DRAM ICs balls or passive components may short with others, and (d) during memory module testing in the motherboard, modules such as golden finger pins may not be connected one to one properly with Motherboard DIMM connector there by leading to shorting.
[0004] There is, therefore, a need in the art for determining techniques to avoid and minimize burnout of the DRAM and the test apparatus during testing of the uTT DRAM.

OBJECTS OF THE INVENTION
[0005] A general object of the present disclosure is to provide a technique and solution for detecting whether downgrade dynamic random access memory (DRAM) is internally shorted or is placed with wrong polarity in a test fixture or is placed improperly in the test fixture or fixed with wrong polarity on a PCB or any other similar cause, leading to shorting.
[0006] Another object of the present disclosure is to prevent burning of a test apparatus used for testing of the DRAM) in case the DRAM is internally shorted or is placed with wrong polarity in a test fixture or is placed improperly in the test fixture or fixed with wrong polarity on a PCB or any other similar cause, leading to shorting.

SUMMARY
[0007] According to an aspect, the present disclosure discloses a system for avoiding burnout issues during downgrade Dynamic Random-access memory (DRAM) testing, the system comprising: a test apparatus adapted to electrically coupled to a DRAM, and configured to monitor voltage of the DRAM; and a comparator operatively coupled to the test apparatus, and configured to compare the monitored voltage of the DRAM, obtained from the test apparatus, with a dataset comprising pre-defined threshold voltages, and wherein the comparator generates a set of alarm signals when the monitored voltage of the DRAM is less than the pre-defined threshold voltages.
[0008] In an aspect, the system comprises Light Emitting Diodes (LEDs) operatively coupled to the comparator, wherein the LEDs glow on receiving the set of alarm signals.
[0009] In an aspect, the system comprises a buzzer operatively coupled to the comparator, wherein the buzzer generates an acoustic signal on receiving the set of alarm signals.
[00010] In another aspect, the system comprises a relay operatively coupled to the comparator, wherein potential free contacts of the relay get activated on receiving the set of alarm signals.
[00011] In an aspect, the DRAM comprises multiple pins and at least one die, and wherein the system is configured to monitor voltage between each of the multiple pins and the at least one die with the respective pre-defined threshold voltage, and correspondingly generate the set of alarm signals.
[00012] In an aspect, the system comprises a memory operatively coupled to the comparator, the memory stores a dataset comprising the pre-defined threshold voltages of the DRAM.
[00013] According to another aspect, the present disclosure discloses a testing apparatus for avoiding burnout issues during downgrade Dynamic Random-access memory (DRAM) testing, the testing apparatus comprising: a voltage measuring unit adapted to be electrically coupled to a DRAM, and configured to monitor voltage of the DRAM; a memory configured to store a dataset comprising the pre-defined threshold voltages of the DRAM; and a comparator operatively coupled to the voltage measuring unit and the memory, and configured to compare the monitored voltage of the DRAM, obtained from the voltage measuring unit, with the pre-defined threshold voltages, obtained from the memory, and wherein the comparator generates a set of alarm signals when the monitored voltage of the DRAM is less than the pre-defined threshold voltages.
[00014] In an aspect, the testing apparatus comprises Light Emitting Diodes (LEDs) operatively coupled to the comparator, wherein the LEDs glow on receiving the set of alarm signals.
[00015] In an aspect, the testing apparatus comprises a buzzer operatively coupled to the comparator, wherein the buzzer generates an acoustic signal on receiving the set of alarm signals.
[00016] In an aspect, the testing apparatus comprises a relay operatively coupled to the comparator, wherein potential free contacts of the relay get activated on receiving the set of alarm signals.
[00017] In an aspect, the monitoring of the DRAM facilitates in preventing effects of shorting, thereby averting burning of one or more of module PCB, module DIMM connector on motherboard, motherboard, test fixture and test socket of the testing apparatus.
[00018] The above and other mentioned objects and advantages of the present invention are described hereunder in greater details with reference to following accompanying non-limiting illustrative drawings.

BRIEF DESCRIPTION OF THE DRAWINGS
[00019] The accompanying drawings are included to provide a further understanding of the present disclosure and are incorporated in and constitute a part of this specification. The drawings illustrate exemplary embodiments of the present disclosure and, together with the description, serve to explain the principles of the present disclosure.
[00020] FIG. 1 illustrates block diagram of the system, in accordance with an embodiment of the present disclosure.
[00021] FIG. 2 illustrates a block diagram of a testing device, in accordance with an embodiment of the present disclosure.
[00022] FIGs. 3A-3C illustrate components of the system, in accordance with an embodiment of the present disclosure.

DETAILED DESCRIPTION
[00023] The following is a detailed description of embodiments of the disclosure depicted in the accompanying drawings. The embodiments are in such details as to clearly communicate the disclosure. However, the amount of detail offered is not intended to limit the anticipated variations of embodiments; on the contrary, the intention is to cover all modifications, equivalents, and alternatives falling within the spirit and scope of the present disclosure as defined by the appended claims.
[00024] Various methods described herein may be practiced by combining one or more machine-readable storage media containing the code according to the present invention with appropriate standard computer hardware to execute the code contained therein. An apparatus for practicing various embodiments of the present invention may involve one or more computers (or one or more processors within a single computer) and storage systems containing or having network access to computer program(s) coded in accordance with various methods described herein, and the method steps of the invention could be accomplished by modules, routines, subroutines, or subparts of a computer program product.
[00025] If the specification states a component or feature “may”, “can”, “could”, or “might” be included or have a characteristic, that particular component or feature is not required to be included or have the characteristic.
[00026] As used in the description herein and throughout the claims that follow, the meaning of “a,” “an,” and “the” includes plural reference unless the context clearly dictates otherwise. Also, as used in the description herein, the meaning of “in” includes “in” and “on” unless the context clearly dictates otherwise.
[00027] Exemplary embodiments will now be described more fully hereinafter with reference to the accompanying drawings, in which exemplary embodiments are shown. This invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. These embodiments are provided so that this disclosure will be thorough and complete and will fully convey the scope of the invention to those of ordinary skill in the art. Moreover, all statements herein reciting embodiments of the invention, as well as specific examples thereof, are intended to encompass both structural and functional equivalents thereof. Additionally, it is intended that such equivalents include both currently known equivalents as well as equivalents developed in the future (i.e., any elements developed that perform the same function, regardless of structure).
[00028] In an aspect, the present disclosure discloses a system for avoiding burnout issues during downgrade Dynamic Random-access memory (DRAM) testing, the system can include a test apparatus adapted to electrically coupled to a DRAM, and configured to monitor voltage of the DRAM; and a comparator operatively coupled to the test apparatus, and configured to compare the monitored voltage of the DRAM, obtained from the test apparatus, with a dataset comprising pre-defined threshold voltages, and wherein the comparator generates a set of alarm signals when the monitored voltage of the DRAM is less than the pre-defined threshold voltages.
[00029] In an embodiment, the system can include Light Emitting Diodes (LEDs) operatively coupled to the comparator, wherein the LEDs may glow on receiving the set of alarm signals.
[00030] In an embodiment, the system can include a buzzer operatively coupled to the comparator, wherein the buzzer can generate an acoustic signal on receiving the set of alarm signals.
[00031] In another embodiment, the system can include a relay operatively coupled to the comparator, wherein potential free contacts of the relay can get activated on receiving the set of alarm signals.
[00032] In an embodiment, the DRAM can include multiple pins and at least one die, and wherein the system can be configured to monitor voltage between each of the multiple pins and the at least one die with the respective pre-defined threshold voltage, and correspondingly generate the set of alarm signals.
[00033] In an embodiment, the system can include a memory operatively coupled to the comparator, the memory stores a dataset comprising the pre-defined threshold voltages of the DRAM.
[00034] In an another aspect, the present disclosure discloses a testing device for avoiding burnout issues during downgrade Dynamic Random-access memory (DRAM) testing, the testing apparatus can include a voltage measuring unit adapted to be electrically coupled to a DRAM, and configured to monitor voltage of the DRAM; a memory configured to store a dataset comprising the pre-defined threshold voltages of the DRAM; and a comparator operatively coupled to the voltage measuring unit and the memory, and configured to compare the monitored voltage of the DRAM, obtained from the voltage measuring unit, with the pre-defined threshold voltages, obtained from the memory, and wherein the comparator generates a set of alarm signals when the monitored voltage of the DRAM is less than the pre-defined threshold voltages.
[00035] In an embodiment, the testing device can include Light Emitting Diodes (LEDs) operatively coupled to the comparator, wherein the LEDs can glow on receiving the set of alarm signals.
[00036] In an embodiment, the testing device can include a buzzer operatively coupled to the comparator, wherein the buzzer can generate an acoustic signal on receiving the set of alarm signals.
[00037] In an embodiment, the testing device can include a relay operatively coupled to the comparator, wherein potential free contacts of the relay can get activated on receiving the set of alarm signals.
[00038] In an embodiment, the monitoring of the DRAM can facilitate in preventing effects of shorting, thereby averting burning of one or more of module PCB, module DIMM connector on motherboard, motherboard, test fixture and test socket of the testing device.
[00039] In an embodiment, the system is provided for avoiding burning of the test apparatus used for testing of a downgrade dynamic random-access memory (e.g., uTT DRAM). The system may facilitate using a voltage comparison circuit for preventing burning of the test apparatus while testing of the downgrade dynamic random access memory (DRAM), in case the DRAM is placed with wrong polarity in a test fixture or is placed improperly in the test fixture or fixed with wrong polarity on a PCB or any other similar cause, which could lead to shorting. Voltage between Voltage Source Source (VSS) and a Voltage Drain Drain (VDD) can be detected and compared with a threshold voltage, and upon the detected voltage value being below the threshold value an alarm is raised to prevent a burnout of the test apparatus or its constituents. In an exemplary embodiment, the voltage comparison circuit can be a controller based circuit or a logic based circuit or simply an OP-AM comparator. In another exemplary embodiment, the alarm can be at least one of an audio alarm, a visual alarm, and an audio-visual alarm. In yet another embodiment, the alarm may generate a warning input to any of other circuit or a controller. In an embodiment, the voltage comparison circuit can operates before powering ON of the motherboard for the DRAM testing device.
[00040] Various objects, features, aspects and advantages of the inventive subject matter will become more apparent from the following detailed description of preferred embodiments, along with the accompanying drawing figures in which like numerals represent like components.
[00041] FIG. 1 illustrates block diagram of the system 100, in accordance with an embodiment of the present disclosure.
[00042] In an embodiment, FIG. 1 illustrates a simplified block diagram of the system 100. The system 100 can facilitate in checking of shorting inside the downgrade DRAM (uTT DRAM). The system 100 can include a reference voltage block 102, a test apparatus voltage block 104, a comparator block 106, and an alarm output block 108. The circuit can facilitate checking occurrence of any shorting inside the test apparatus, DRAM pins/balls or inside internal die. The reference voltage block 102 can determine and store a threshold voltage. As can be appreciated by one skilled in the art the threshold voltage may be different for various DDR (Double Data Rate) DRAM types. Further, the comparator block 106 can check and compare the voltage difference between voltages looped through the test apparatus voltage block 104 with the reference determined from the reference voltage block 102. When the looped voltage is less than the threshold voltage, the comparator block 106 can generate a set of alert signals (error signals) to activate the alarm output block 108.
[00043] In an embodiment, the alarm output block 108 may generate an audio and/or a video alarm. The alarm may be raised as a form of an audio buzzer and/or as a visual indication using an LED indicator or potential free contacts may be activated through a relay.
[00044] In an embodiment, voltage testing in the voltage comparison circuit may be performed before powering of motherboard. The audio and the visual alarms that are generated may facilitate preventing burning of the test apparatus and its constituents.
[00045] FIG. 2 illustrates a block diagram of a testing device 200, in accordance with an embodiment of the present disclosure.
[00046] In an embodiment, the system 100 can be implemented in the testing device 200, where the testing device 200 can include a voltage measuring unit adapted to be electrically coupled to a DRAM 202, and configured to monitor voltage of the DRAM 202, and a memory configured to store a dataset comprising the pre-defined threshold voltages of the DRAM 202. In other embodiment, the testing device 200 can include a comparator operatively coupled to the voltage measuring unit and the memory, and configured to compare the monitored voltage of the DRAM 202, obtained from the voltage measuring unit, with the pre-defined threshold voltages, obtained from the memory, and where the comparator can generate a set of alarm signals when the monitored voltage of the DRAM 202 is less than the pre-defined threshold voltages.
[00047] In an embodiment, the testing device 200 can include Light Emitting Diodes (LEDs) 204 and a buzzer 206 operatively coupled to the comparator, wherein the LEDs 204 glow and the buzzer 206 can generate an acoustic signal on receiving the set of alarm signals. In another embodiment, the testing device 200 can include a relay 208 operatively coupled to the comparator, wherein potential free contacts of the relay 208 get activated on receiving the set of alarm signals. In yet another embodiment, the monitoring of the DRAM 202 can facilitate in preventing effects of shorting, thereby averting burning of one or more of module PCB, module DIMM connector on motherboard, motherboard, test fixture and test socket of the testing device 200.
[00048] FIGs. 3A-3C illustrate components of the system, in accordance with an embodiment of the present disclosure.
[00049] In an embodiment, as shown in FIGs. 3A-3C are the exemplary voltage comparison circuits that shows elements such as the test circuit, the motherboard, an extender, a comparator, and a buzzer. The voltage comparison circuits can be adapted to accommodate the DRAM 202 and compare its voltage with the reference voltage.
[00050] Thus, it will be appreciated by those of ordinary skill in the art that the diagrams, schematics, illustrations, and the like represent conceptual views or processes illustrating systems and methods embodying this invention. The functions of the various elements shown in the figures may be provided through the use of dedicated hardware as well as hardware capable of executing associated software. Similarly, any switches shown in the figures are conceptual only. Their function may be carried out through the operation of program logic, through dedicated logic, through the interaction of program control and dedicated logic, or even manually, the particular technique being selectable by the entity implementing this invention. Those of ordinary skill in the art further understand that the exemplary hardware, software, processes, methods, and/or operating systems described herein are for illustrative purposes and, thus, are not intended to be limited to any particular named.
[00051] While embodiments of the present invention have been illustrated and described, it will be clear that the invention is not limited to these embodiments only. Numerous modifications, changes, variations, substitutions, and equivalents will be apparent to those skilled in the art, without departing from the spirit and scope of the invention, as described in the claim.
[00052] In the foregoing description, numerous details are set forth. It will be apparent, however, to one of ordinary skill in the art having the benefit of this disclosure, that the present disclosure can be practiced without these specific details. In some instances, well-known structures and devices are shown in block diagram form, rather than in detail, to avoid obscuring the present invention.
[00053] While the foregoing describes various embodiments of the disclosure, other and further embodiments of the disclosure may be devised without departing from the basic scope thereof. The disclosure is not limited to the described embodiments, versions or examples, which are included to enable a person having ordinary skill in the art to make and use the disclosure when combined with information and knowledge available to the person having ordinary skill in the art.
ADVANTAGES OF THE INVENTION
[00054] The present disclosure provides a technique and solution for detecting whether downgrade dynamic random access memory (DRAM) is internally shorted or is placed with wrong polarity in a test fixture or is placed improperly in the test fixture or fixed with wrong polarity on a PCB or any other similar cause, leading to shorting.
[00055] The present disclosure provides a system to prevent burning of a test apparatus used for testing of the DRAM) in case the DRAM is internally shorted or is placed with wrong polarity in a test fixture or is placed improperly in the test fixture or fixed with wrong polarity on a PCB or any other similar cause, leading to shorting.

CLAIMS:

1.A system for avoiding burnout issues during downgrade Dynamic Random-access memory (DRAM) testing, the system comprising:
a test apparatus adapted to electrically coupled to a DRAM, and configured to monitor voltage of the DRAM; and
a comparator operatively coupled to the test apparatus, and configured to compare the monitored voltage of the DRAM, obtained from the test apparatus, with a dataset comprising pre-defined threshold voltages, and wherein the comparator generates a set of alarm signals when the monitored voltage of the DRAM is less than the pre-defined threshold voltages.
2. The system as claimed in claim 1, wherein the system comprises Light Emitting Diodes (LEDs) operatively coupled to the comparator, wherein the LEDs glow on receiving the set of alarm signals.
3. The system as claimed in claim 1, wherein the system comprises a buzzer operatively coupled to the comparator, wherein the buzzer generates an acoustic signal on receiving the set of alarm signals.
4. The system as claimed in claim 1, wherein the system comprises a relay operatively coupled to the comparator, wherein potential free contacts of the relay get activated on receiving the set of alarm signals.
5. The system as claimed in claim 1, wherein the DRAM comprises multiple pins and at least one die, and wherein the system is configured to monitor voltage between each of the multiple pins and the at least one die with the respective pre-defined threshold voltage, and correspondingly generate the set of alarm signals.
6. The system as claimed in claim 1, wherein the system comprises a memory operatively coupled to the comparator, the memory stores a dataset comprising the pre-defined threshold voltages of the DRAM.
7. A testing device for avoiding burnout issues during downgrade Dynamic Random-access memory (DRAM) testing, the testing device comprising:
a voltage measuring unit adapted to be electrically coupled to a DRAM, and configured to monitor voltage of the DRAM;
a memory configured to store a dataset comprising the pre-defined threshold voltages of the DRAM; and
a comparator operatively coupled to the voltage measuring unit and the memory, and configured to compare the monitored voltage of the DRAM, obtained from the voltage measuring unit, with the pre-defined threshold voltages, obtained from the memory, and wherein the comparator generates a set of alarm signals when the monitored voltage of the DRAM is less than the pre-defined threshold voltages.
8. The testing device as claimed in claim 7, wherein the testing device comprises Light Emitting Diodes (LEDs) and a buzzer operatively coupled to the comparator, wherein the LEDs glow and the buzzer generates an acoustic signal on receiving the set of alarm signals.
9. The testing device as claimed in claim 7, wherein the testing device comprises a relay operatively coupled to the comparator, wherein potential free contacts of the relay get activated on receiving the set of alarm signals.
10. The testing device as claimed in claim 7, wherein the monitoring of the DRAM facilitates in preventing effects of shorting, thereby averting burning of one or more of module PCB, module DIMM connector on motherboard, motherboard, test fixture and test socket of the testing apparatus.