The present disclosure pertains to a system and a device for avoiding burning of a downgrade dynamic random-access memory (DRAM), while testing, along with test apparatus used for testing of the DRAM. The system and device may facilitate in detecting occurrence of shorting inside the DRAM to avoid failure/burnout is...

The present disclosure relates to a memory module chip with selectable ranks, which can be used even when there is a failure of memory chip(s) in one of its ranks. The memory module includes a set of memory chips on a first side (first rank), and a second side (second rank). The memory module is adapted to be connec...

A method and system are provided for utilization of non JDECC compliant Double Data Rate 4 Synchronous Dynamic Random-Access Memory (DDR4 DRAM) by modifying standard JEDEC approved module PCB circuit and SPD. Standard JEDEC DDR4 double-sided UDIMM is modified for using DDR4 downgrade types having BG1 low or high, an...