DESC:TECHNICAL FIELD
[0001] The present disclosure relates to the field of semiconductor memories, and more particularly the present disclosure relates to a memory module with selectable ranks, and which can still be used when there is a failure of memory chip(s) in one of the ranks.

BACKGROUND OF THE INVENTION
[0002] Background description includes information that may be useful in understanding the present invention. It is not an admission that any of the information provided herein is prior art or relevant to the presently claimed invention, or that any publication specifically or implicitly referenced is prior art.
[0003] Generally, memories such as Double Data Rate 4 Synchronous Dynamic Random-Access Memory (DDR4 DRAM) are designed based on standards defined by Joint Electronic Device Engineering Council (JEDEC). The modules present in DDR4 DRAM have memory chips made up of numerous tiny integrated circuits (ICs) that are expected to perform reliably over long stretches of time under tough workloads and settings. Whether at rest or in operation, these modules face hazards throughout their usage life, and any malfunction can lead to system breakdowns that could disrupt or delay business operations.
[0004] Conventionally, a memory module Memory is manufactured with 8 chips having each chip 8-bit data wide. The memory module capacity in this case is 8 times the density of an individual chip. By using 16 chips, for the same chip density, the memory module capacity can be double of the 8 chips module for the same chip. A DDR unbuffered non-ECC Long dual inline memory module includes dual data rate chips, a printed circuit board (PCB), and one EEPROM for serial presence detect (SPD). The memory devices are arranged/placed/mounted on the printed circuit board (PCB) in a rank-wise manner.
[0005] The module is connected to the PC motherboard using a memory bus that has more than 100 electrical contact points depending upon the module/motherboard technology–DDR, DDR2, DDR3, DDR4, etc.FIG.1 illustrates a standard two rank memory module uses two chip select signal. Additionally, it requires two Clock enable signals and two on-die termination signals, which are routed through each DIMM slot. Each DIMM slot can access one memory module and has a unique DIMM slot address that connects to a memory controller, thereby a personal computer or computing device BIOS can access the memory modules individually. Each memory module contains 16pcs dynamic random access memory ICs and one EEPROM for 2 Ranks double data rate (DDR) dual inline memory module. Each rank of DRAM IC shares a chip select (CS#) signal from the memory controller through the DIMM slot.
[0006] DDR dual inline memory module also contains one EEPROM for serial presence detect (SPD), which contains memory module information, like Chip capacity/density, memory module configuration, clock timing, and a few other information. During operation the EEPROM provides the memory module SPD information to BIOS (Basic input-output system) of the personal computer through I2C communication bus using serial clock (SCL) and serial data (SDA). FIG. 2 illustrates four memory modules in four DIMM slots having different memory slot addresses. This address shares the memory module SPD information to personal computer BIOS through I2Ccommunication bus.
[0007] However, if the memory module fails then the PC can’t work till the memory module is replaced. Many times, it is not possible to change the module right away so the user may be stuck. It is practically not possible for a user to repair the memory module on his own, though most of the Laptops and Desktops allow a user to pull out the memory module without much technical expertise. In fact, most the laptops have a separate window lid (like for battery replacement) to open the chamber containing memory modules to add more memory modules.
[0008] Conventional memory modules have two ranks (also referred to as two sides), with each rank having multiple DRAM chips. Most of the times, failure in one of the two ranks of the memory module occurs due to failure or damage in only one DRAM chip (one of 16 chips) associated with that rank, leading to complete failure of the whole memory module despite other chips of the other rank remaining in a working and healthy condition. This implies that a single DRAM chip failure makes all the DRAM chips non-functional.
[0009] There is, therefore, a requirement in the art to overcome the above limitations, and shortcomings, and provide an improved dual-rank memory module chip with selectable ranks, and which can still be used when there is a failure of memory chip(s) in one of the ranks.

OBJECTS OF THE INVENTION
[0010] It is an object of the present disclosure to utilize failed two rank memory module on the fly.
[0011] It is an object of the present disclosure to provide a two rank memory module with a customized selection of the ranks.
[0012] It is an object of the present disclosure to provide a two rank memory module, which can still be used in case of failure of a DRAM chip in one of the two ranks.
[0013] It is an object of the present disclosure to modify standard JEDEC approved memory module PCB circuit, for EEPROM selection.
[0014] It is an object of the present disclosure to modify the CS, CKE, and ODT routes/tracks for utilizing the memory module
[0015] It is an object of the present disclosure to provide a two rank memory module chip with a customized selection of the ranks, maintaining that all other signals in the memory module follow JEDEC recommendation.

SUMMARY
[0016] The present disclosure relates to the field of semiconductor memories, and more particularly the present disclosure relates to a memory module with selectable ranks, and which can still be used when there is a failure of memory chip(s) in one of the ranks.
[0017] According to an aspect, the present disclosure discloses a memory module that can be connected to a Dual Inline Memory Module (DIMM) slot. The memory module includes a first set of memory chips on a front side, also referring to as first rank (or rank 1), and a second set of memory chips on a back side also referring to as second rank (or rank 2), The memory chips can be a 16 DDR4 DRAM, but not limited to the likes.
[0018] The memory module and the DIMM slot can be connected to a memory controller associated with a computing device such as a computer, laptop, and the likes. The memory controller provides a set of control signals comprising any or a combination of a chip select signal (CS), clock enable signal (CKE), and on-die termination signal (ODT) to the ranks of the memory module to disable and/or enable any of the ranks, as required or in case of failure.The memory module is connected to the memory controller through the DIMM slot, and all the control signals can be directly provided from the DIMM slot to the respective chips of the two ranks.
[0019] In an aspect, the memory module includes multiple switches being operably connected to the plurality of ranks and the memory controller. The switches are configurable by the memory controller, to disable and/or enable any of the ranks as well as their associated memory chips by modifying the control signals provided to the memory controller.
[0020] Accordingly, when one of the memory chips associated with one of the ranks fails, the switches can be configured by the memory controller or by modifying the control signals, to disable the failed rank such that the other rank remains operational and operatively connected to the DIMM slot.
[0021] In an aspect, the memory module can include resistor networks operably coupled to each of the ranks of the memory module. Upon performing the operation of providing the control signals to ranks, the resistor networks can terminate the control signals associated with the respective ranks.
[0022] In an aspect, the memory module comprises two EEPROMs for providing serial presence detect (SPD) data. The EPROMS are electrically coupled to a BIOS of the mobile computing device by at least one of the switches. Address bits of the EEPROMs are electrically coupled together using at least one of the switches such that both the EEPROM selects the same DIMM Slot address. Further, the DIMM slot address detected by at least one of the EEPROMs is provided to the BIOS of the mobile computing device as a serial control (SCL), and a serial address (SDA) by a I2C communication bus, but not limited to the likes.

BRIEF DESCRIPTION OF DRAWINGS
[0023] The accompanying drawings are included to provide a further understanding of the present disclosure and are incorporated in and constitute a part of this specification. The drawings illustrate exemplary embodiments of the present disclosure and, together with the description, serve to explain the principles of the present disclosure.
[0024] FIG. 1 illustrates a standard two rank memory module that uses two chip select signal.
[0025] FIG. 2 illustrates four memory modules in four DIMM slot having different memory slot address
[0026] FIG. 3 illustrates a conventional printed circuit board (PCB) design for a two-rank memory module.
[0027] FIG. 4 illustrates an exemplary representation of the proposed two rank memory module, in accordance with an embodiment of the present disclosure.

DETAILED DESCRIPTION
[0028] The following is a detailed description of embodiments of the disclosure depicted in the accompanying drawings. The embodiments are in such detail as to clearly communicate the disclosure. However, the amount of detail offered is not intended to limit the anticipated variations of embodiments; on the contrary, the intention is to cover all modifications, equivalents, and alternatives falling within the spirit and scope of the present disclosure as defined by the appended claims.
[0029] If the specification states a component or feature “may”, “can”, “could”, or “might” be included or have a characteristic, that particular component or feature is not required to be included or have the characteristic.
[0030] As used in the description herein and throughout the claims that follow, the meaning of “a,” “an,” and “the” includes plural reference unless the context clearly dictates otherwise. Also, as used in the description herein, the meaning of “in” includes “in” and “on” unless the context clearly dictates otherwise.
[0031] Exemplary embodiments will now be described more fully hereinafter with reference to the accompanying drawings, in which exemplary embodiments are shown. These exemplary embodiments are provided only for illustrative purposes and so that this disclosure will be thorough and complete and will fully convey the scope of the invention to those of ordinary skill in the art. The invention disclosed may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein.
[0032] The use of any and all examples, or exemplary language (e.g., “such as”) provided with respect to certain embodiments herein is intended merely to better illuminate the invention and does not pose a limitation on the scope of the invention otherwise claimed. No language in the specification should be construed as indicating any non – claimed element essential to the practice of the invention.
[0033] According to as aspect, the present disclosure elaborates upon a memory module with selectable ranks, and which can still be used with reduced capacity when there is a failure of memory chip(s) in one of the ranks. The memory module can be adapted to be configured with a Dual Inline Memory Module (DIMM) slot. The memory module can include a plurality of ranks, and each of the ranks comprising a set of memory chips, and one or more switches operably coupled with the plurality of ranks, and the DIMM slot. The one or more switches can be configurable by a memory controller associated with a mobile computing device, to disable and/or enable any of the plurality of ranks and the corresponding memory chips by modifying a plurality of signals associated with the plurality of ranks.
[0034] In an embodiment, the one or more switches can be selected from a dual in package (DIP) switch, relay, and jumper.
[0035] In an embodiment, when at least one of the memory chips associated with one of the ranks fails, the one or more switches can be configured by the memory controller to correspondingly disable the failed ranks by modifying the plurality of signals associated with the plurality of ranks such that the other ranks remain operational and operatively coupled to the DIMM slot.
[0036] In an embodiment, the plurality of signals can include any or combinations of a chip select signal, clock enable signal, and on-die termination signal.
[0037] In an embodiment, the memory module can include a first resistor network operatively coupled to one of the ranks, and a second resistor network operatively coupled to the other rank through at least one of the one or more switches. Further, upon performing the operation of providing the plurality of signals to at least one of the plurality of ranks, the first resistor network and the second resistor network can be configured to terminate the plurality of signals associated with the respective ranks.
[0038] In an embodiment, the resistance of the first resistor network, and the second resistor network are adjustable and can be in a range of 40-50 ohm. Further, each of the one or more memory chips can be a 16 DDR4 DRAM.
[0039] In an embodiment, the memory module can include two EEPROMs for providing serial presence detect (SPD) data. The two EPROMS can be electrically coupled to a BIOS of the mobile computing device by at least one of the one or more switches.
[0040] In an embodiment, address bits of the EEPROMs can be electrically coupled together using at least one of the one or more switches such that both the EEPROMs elects the same DIMM Slot address.
[0041] In an embodiment, the DIMM slot address detected by at least one of the EEPROMs is provided to the BIOS of the mobile computing device as a serial control (SCL), and a serial address (SDA) by a communication bus.
[0042] Referring to FIG. 3, a conventional printed circuit board (PCB) design for a two-rank memory module is disclosed. As illustrated, in the conventional memory module design, a different sets of signals are used for controlling and operating different memory chips on different sides of the module PCB. Memory chips (U9-U16) on the backside can be referred to as second rank or “rank 2” and signals used for the controlling of the second rank can include chip select (CS1), clock enable (CKE1), and on-die termination (ODT1). Similarly, memory chips (U1-U8) on the front side can be referred to as a first rank or “rank 1” and signals used for the controlling of the first rank can include chip select (CS0), clock enable (CKE0), and on-die termination (ODT0). Memory module chip conventionally includes an EEPROM for providing the serial presence detect (SPD) information.
[0043] The memory module is configured to be connected with a DIMM slot (300) in a computing device. The computing device can be but not limited to a laptop, and a desktop. All the signals CS0, CS1, CKE0, CKE1, ODT0, and ODT1 can be directly provided from the DIMM slot or golden finger to the respective chips of the first rank and the second rank.
[0044] The memory controller can provide signals to the first rank and the second rank directly. After operating for providing or modifying the signals, the signals CS1, CKE1, and ODT1 can be terminated through a first resistor network “RN9” and the signals CS0, CKE0, and ODT0 can be terminated through a second resistor network “RN4”.
[0045] The value of first and second resistor networks can be in a range of 40-50 ohm. The DIMM slot address can be detected by address bits (A0, A1, and A2) of an EEPROM and can be provided (as serial control SCL and serial address SDA) to BIOS of the computing device by a communication bus. The communication but can be but is not limited to an I2Ccommunication bus.
[0046] FIG. 4 illustrates the circuit design of the proposed memory module with selectable ranks, and which can still be used when there is a failure of memory chip(s) in one of the ranks, in accordance with an embodiment of the present invention.
[0047] Referring to FIG. 4, an exemplary circuit design of the proposed memory module 400 is disclosed, which is only utilizing a front side of the memory module by disabling backside of the memory module chip
[0048] In an embodiment, the memory module 400 can be adapted to be configured with a Dual Inline Memory Module (DIMM) slot 300 (also referred to as a golden finger 300 or DIMM 300, herein). The memory module 400 can include a first set of memory chips (U1-U8) at the first side (also referred to as front side) of the memory module chip and a second set of memory chips (U9-U16) at the second side (also referred as a back side, herein) of the memory module 400. The memory chips at the first side can also be referred to as a first rank 402-1, and the memory chips at the second side can also be referred to as a second rank 402-2. In an exemplary embodiment, the first set of memory chips U1-U8 and the second set of memory chips U1-U16 can be 16 DDR4 DRAM, but not limited to the like.
[0049] In an embodiment, a memory controller of the computing device can be adapted to be connected to the memory module 400 and the DIMM slot 300, and can provide respective control signals (also referred to as a plurality of signals, herein) to the respective ranks 402-1 and 402-2 via the DIMM slot 300. The control signals can include but are not limited to chip select (CS), clock enable (CKE), and on-die termination (ODT).
[0050] The proposed memory module 400 can include one or more switches (SW1, SW2, and SW3) 404-1 to 404-3 (collectively referred to as switches 404, herein), and one or more resistor networks (RN4, RN9) 406-1 and 406-2.In an exemplary embodiment, the one or more switches 404 can include any or combination of dual in package (DIP) switch, relay, and jumper, but not limited to the likes.
[0051] In an implementation, control signals (CS0, CKE0, and ODT0) for controlling the first rank 402-1 can be provided from the DIMM slot 300 directly to the memory chips (U1-U8), and after performing the operation, the signals (CS0, CKE0, and ODT0) can be terminated through the resistor network “RN4” (406-1). Further, the control signals (CS1, CKE1, and ODT1) can be used to control the second rank 402-2.
[0052] As illustrated in FIG. 4, the signal CS1 can be provided to the memory chips (U9-U16) through the switch SW3 (404-3). The CS1 can be applied to pin “3” of the switch SW3, and from pin “3” it can be transferred to pin “6” of the switch SW3. The CS1 can be applied to the chips (U9-U16) by the pin “6”. After that, the CS1 can be provided to pin “1” and “2” of the switch SW3. The CS1 signal from pin 1 and 2 can be provided to pin “8” and “7”, respectively. Pin 7 can be provided with the input supply “VDD” and pin “8” can be connected with pin “4” of the resistor network RN9 (406-2). A pin “5” can be connected to a termination voltage “Vtt” along with pins “6”, ”7”, and “8” of the resistor network RN4 (406-1).
[0053] The terminal voltage is the voltage that can be used to feed the termination logic inside the memory chips. In an exemplary implementation, by default, the termination voltage Vtt can be set at half of the memory voltage. The value of VDD can be1.2V for the DDR4 Memory module,
[0054] Further, control signals CKE1 can be provided to the chips (U9-U16) and can be connected with pins “3” and “4” of the switch SW2 (404-2),and the control signal ODT1 can be provided to the chips (U9-U16) and can be connected to pins “1” and “2” of the switch SW2. Pin “8” of the switch SW2 can be connected to a pin “2” of the resistor network RN9, and pin 5 of the switch SW2 can be connected to a pin “3” of the resistor network RN9. Pins “6” and “7” of the switch SW2 can be connected to ground (GND). Pins “5”, “6”, and “7” of the resistor network RN9 can be connected to the terminal voltage Vtt.
[0055] In an embodiment, the memory module400 can include a plurality of EEPROMs 408-1 and 408-2 for providing serial presence detect (SPD) data. The EPROMS 408-1 and 408-2can be electrically coupled to a BIOS of the mobile computing device by at least one of the switches 404. Address bits of the EEPROMs 408-1 and 408-2can be electrically coupled together using at least one of the switches 404-1 (SW1, herein) such that both the EEPROMs 408-1 and 408-2 select the same DIMM Slot address. Further, the DIMM slot address detected by at least one of the EEPROMs 408-1 and 408-2 can be provided to the BIOS of the mobile computing device as a serial control (SCL), and a serial address (SDA) by an I2C communication bus, but not limited to the likes.
[0056] As illustrated in FIG. 4, in an exemplary embodiment, the proposed memory module 400 can include two EEPROMs (also referred to as U17 and U18, herein). Address inputs (A0, A1, and A2) of the EEPROM1 408-1 (also referred to as U17, herein) can be connected to address inputs (A0, A1, and A2) of the EEPROM2 408-2 (also referred to as U18, herein). Serial control (SCL) of the EEPROM1 can be connected to a pin “1” of the switch SW1, and serial data (SDA) of the EEPROM1 408-1 can be connected to a pin “2” of the switch SW1 (404-1). Serial control (SCL) of the EEPROM2 can be connected to a pin “3” of the switch SW1, and serial data (SDA) of the EEPROM2 can be connected to a pin “4” of the switch SW1.The serial controls (SCL0 and SCL1) of both the EEPROMS 408-1 and 408-2(U17 and U18) are connected by connecting pins “8” and “6” of the switch SW1. The serial data (SDA0 and SDA1) of both the EEPROMS 408-1 and 408-2(U17 and U18) are connected by connecting pins “7” and “5” of the switch SW1 (404-1). Pins 2 and 6 of the EEPROM2 408-2 can be connected to pins “3” and “4” of the switch SW1. The combined serial data (SDA) and serial control (SCL) can be provided to the BIOS setting of the computing device throughI2Ccommunication interface bus.
[0057] In an embodiment, Table 1 shows the status of one or more switches (SW1, SW2, and SW3) when both the first and second ranks are utilized. Different sub-switches of the switches SW1, SW2, and SW3 can be operated in different combinations to make the proposed memory module work as a two rank memory module.
TABLE:1
Dip Switch 1-8 2-7 3-6 4-5 Remark
SW1 ON ON OFF OFF Normal 2Rank Memory Module
SW2 ON OFF OFF ON
SW3 ON OFF ON NC

[0058] In another embodiment, Table 2 shows the status of the one or more switches when back side of the memory module chip is disabled and only the front side is utilized. When both ranks are used pins “1” and “8”, and “2” and “7”of the switch SW1 can be connected. Pins “1” and “8”, and “4” and “5” of the switch SW2 can be connected. Pins 3 and 6, and 1 and 8 of the switch SW3 can be connected. By the mentioned switch combination, the CS1 can be provided to the second set of memory chips (U9-U16), and CKE1 and ODT1 can be terminated with the termination voltage Vtt through the resistor network RN9.
TABLE: 2
Dip Switch 1-8 2-7 3-6 4-5 Remark
SW1 OFF OFF ON ON Single Rank (Front side)
SW2 OFF ON ON OFF
SW3 OFF ON OFF NC

The second set of memory chips (U9-U16) can be disabled by connecting pins “3” and “6”, and pins “4” and “5” of the switch SW1.The chip select CS1 can be blocked by isolating the pins “3” and “6” of the switch SW3 and the input supply voltage can be provided to the second set of memory chips by pins “2” and “7” of the switch SW3. In this way, the second set of memory chips cannot receive any signal from the memory controller through the DIMM slot. Also, the CKE1 and ODT1 terminals can be grounded to prevent any floating voltage on CKE1 and ODT1, by connecting pins “2” and “7”, and pins “3” and “6” of the switch SW2.
[0059] It is to be appreciated by a person skilled in the art that while FIG. 4, as well as the corresponding description, illustrated the circuit design of the proposed memory module 400 only for utilizing a front side (rank 1) of the memory module 400 by disabling the back side (rank 2) of the memory module 400. Similarly, circuit design for utilizing the backside can also be designed and is achievable using the proposed memory module, and all such embodiments are well within the scope of the present disclosure.
[0060] Accordingly, when one of the memory chips associated with one of the ranks fails, the switches can be configured by the memory controller using or by modifying the control signals, to disable the failed rank such that the other rank remains operational and operatively connected to the DIMM slot, thereby utilizing failed memory modules in a fly, and providing an improved and efficient memory module with selectable ranks, which can be used with reduced capacity even if one of the ranks fails.
[0061] While the foregoing describes various embodiments of the invention, other and further embodiments of the invention may be devised without departing from the basic scope thereof. The scope of the invention is determined by the claims that follow. The invention is not limited to the described embodiments, versions or examples, which are included to enable a person having ordinary skill in the art to make and use the invention when combined with information and knowledge available to the person having ordinary skill in the art.

ADVANTAGES OF THE INVENTION
[0062] The proposed invention enables the utilization of failed two rank memory modules on the fly.
[0063] The proposed invention provides a two rank memory module with a customized selection of the ranks.
[0064] The proposed invention provides a two rank memory module, which can still be used in case of failure of a DRAM chip in one of the two ranks.
[0065] The proposed invention modifies the standard JEDEC approved memory module PCB circuit, for EEPROM selection.
[0066] The proposed invention modifies the CS, CKE, and ODT routes/tracks for utilizing the memory module.
[0067] The proposed invention provides a two rank memory module chip with a customized selection of the ranks, maintaining that all other signals in the memory module follow JEDEC recommendation.

CLAIMS:1. A memory module adapted to be configured with Dual Inline Memory Module (DIMM) slot, the memory module comprising:
a plurality of ranks, and each of the ranks comprising a set of memory chips; and
one or more switches operably coupled with the plurality of ranks, and the DIMM slot, wherein the one or more switches are configurable by a memory controller associated with a mobile computing device, to disable and/or enable any of the plurality of ranks and the corresponding memory chips by modifying a plurality of signals associated with the plurality of ranks.
2. The memory module as claimed in claim 1, wherein the one or more switches is selected from a dual in package (DIP) switch, relay, and jumper.
3. The memory module as claimed in claim 1, wherein when at least one of the memory chips associated with one of the ranks fails, the one or more switches are configured by the memory controller to correspondingly disable the failed ranks by modifying the plurality of signals associated with the plurality of ranks such that the other ranks remain operational and operatively coupled to the DIMM slot.
4. The memory module as claimed in claim 1, wherein the plurality of signals comprises any or combination of a chip select signal, clock enable signal, and on-die termination signal.
5. The memory module as claimed in claim 1, wherein the DIMM slot and the memory module are operatively coupled to the memory controller, and the plurality of signals is provided to the plurality of ranks of the memory module by the memory controller.
6. The memory module as claimed in claim 1, wherein the memory module comprises a first resistor network operatively coupled to one of the ranks, and a second resistor network operatively coupled to the other rank through at least one of the one or more switches, and
wherein upon operating for providing the plurality of signals to at least one of the plurality of ranks, the first resistor network and the second resistor network are configured to terminate the plurality of signals associated with the respective ranks.
7. The memory module as claimed in claim 6, wherein a resistance of the first resistor network, and the second resistor network are adjustable and selected in a range of 40-50 ohm, and wherein each of the one or more memory chips is a 16 DDR4 DRAM.
8. The memory module as claimed in claim 1, wherein the memory module comprises two EEPROMs for providing serial presence detect (SPD) data, wherein the two EPROMS are electrically coupled to a BIOS of the mobile computing device by at least one of the one or more switches.
9. The memory module as claimed in claim 8, wherein address bits of the EEPROMs are electrically coupled together using at least one of the one or more switches such that both the EEPROM selects same DIMM Slot address.
10. The memory module as claimed in claim 9, wherein the DIMM slot address detected by at least one of the EEPROMs is provided to the BIOS of the mobile computing device as a serial control (SCL), and a serial address (SDA) by a communication bus.