[0001] The present disclosure generally relates to a dynamic random-access memory (DRAM), and in particular relates to testing and using of non JEDEC complaint DRAM ICs.

BACKGROUND OF THE INVENTION
[0002] Generally, memories such as Double Data Rate 4 Synchronous Dynamic Random-Access Memory (DDR4 DRAM) are designed based on standards defined by Joint Electronic Device Engineering Council (JEDEC). The modules present in DDR4 DRAM have memory chips made up of numerous tiny integrated circuits (ICs) that are expected to perform reliably over long stretches of time under tough workloads and settings. Whether at rest or in operation, these modules face hazards throughout their usage life, and any malfunction can lead to system breakdowns that could disrupt or delay business operations. As such, these components should be manufactured and tested according to very high standards. While JEDEC complaint DRAM ICs may mostly pass the testing phase, non-JEDEC compliant ICs may fail at these tests, leading to losses pertaining to failure of the modules resulting in unstable system operation.
[0003] There is, therefore, a need in the art for determining techniques to avoid and minimize lossesby utilizing non JEDEC complaint DRAM Ics found during testing of JEDEC complaint DRAM ICs.

OBJECTS OF THE INVENTION
[0004] A general object of this disclosure is to facilitateutilizing non JEDEC standard compliant DDR4 DRAM chips by modifying standard JEDEC approved module Printed Circuit Board (PCB) circuit design schematic and Serial Presence Detect (SPD).
[0005] An object of the present disclosure is to modify the standard JEDEC DDR4 double-sided unregistered memory (UDIMM) for using DDR4 downgrade types having bank group address BG1 Low or High and when BG1 is equal to BG0.
[0006] An object of the present disclosure is to modify the BG0 and BG1 routes/tracks for utilizing the downgrade ICs.
[0007] An object of the present disclosure is to maintain that all other signals in the PCB follow JEDEC recommendation.

SUMMARY
[0008] The present disclosure relates to a Dynamic Random Access Memory (DRAM) comprising a plurality of back-side and corresponding front-side integrated circuits (ICs) are all Downgrade IC of same downgrade type and density, wherein said plurality of ICs are configured such that Dual-In Line Memory Module (DIMM) Bank Group address (BG0) signal connects to all BG0s of front-side and back-side ICs, and wherein all BG1s of said front-side and back-side ICs are controlled by a plurality of resisters.
[0009] In an aspect, the said DRAM can be non-JEDEC compliant. In another aspect, said DRAM can be a Double Data Rate (DDR) 4 Synchronous DRAM. In yet another aspect, said plurality of resisters can include four resisters (R1 to R4), wherein resister R3 is provided near to gold finger source connector, and wherein resister R4 is provided near to termination. In another aspect, when BG1 of the ICs is low, resister R1 is used, and when BG1 of the ICs is high, resister R2 is used. In another aspect, when BG1 = BG0, R3 and R4 are used.
[00010] In an aspect, circuit of the DRAM can be tested for BG1 when it is low or high. In another aspect, DRAM can include 8 back-side ICs and corresponding 8 front-side ICs.

BRIEF DESCRIPTION OF THE DRAWINGS
[00011] The accompanying drawings are included to provide a further understanding of the present disclosure and are incorporated in and constitute a part of this specification. The drawings illustrate exemplary embodiments of the present disclosure and, together with the description, serve to explain the principles of the present disclosure.
[00012] FIG. 1A (Prior Art) illustrates an exemplary circuit with standard JEDEC BG0 and BG1 connections.
[00013] FIG. 1B illustrates downgrade BG0 and BG1 connection in accordance with an embodiment of the present disclosure.
[00014] FIG. 2 illustrates an exemplary printed circuit board in accordance with an embodiment of the present disclosure.

DETAILED DESCRIPTION
[00015] The following is a detailed description of embodiments of the disclosure depicted in the accompanying drawings. The embodiments are in such details as to clearly communicate the disclosure. However, the amount of detail offered is not intended to limit the anticipated variations of embodiments; on the contrary, the intention is to cover all modifications, equivalents, and alternatives falling within the spirit and scope of the present disclosure as defined by the appended claims.
[00016] Various methods described herein may be practiced by combining one or more machine-readable storage media containing the code according to the present invention with appropriate standard computer hardware to execute the code contained therein. An apparatus for practicing various embodiments of the present invention may involve one or more computers (or one or more processors within a single computer) and storage systems containing or having network access to computer program(s) coded in accordance with various methods described herein, and the method steps of the invention could be accomplished by modules, routines, subroutines, or subparts of a computer program product.
[00017] If the specification states a component or feature “may”, “can”, “could”, or “might” be included or have a characteristic, that particular component or feature is not required to be included or have the characteristic.
[00018] As used in the description herein and throughout the claims that follow, the meaning of “a,” “an,” and “the” includes plural reference unless the context clearly dictates otherwise. Also, as used in the description herein, the meaning of “in” includes “in” and “on” unless the context clearly dictates otherwise.
[00019] Exemplary embodiments will now be described more fully hereinafter with reference to the accompanying drawings, in which exemplary embodiments are shown. This invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. These embodiments are provided so that this disclosure will be thorough and complete and will fully convey the scope of the invention to those of ordinary skill in the art. Moreover, all statements herein reciting embodiments of the invention, as well as specific examples thereof, are intended to encompass both structural and functional equivalents thereof. Additionally, it is intended that such equivalents include both currently known equivalents as well as equivalents developed in the future (i.e., any elements developed that perform the same function, regardless of structure).
[00020] In an embodiment, a method is provided for utilization of non JDECC compliant Double Data Rate 4 Synchronous Dynamic Random-Access Memory (DDR4 DRAM) by : modifying standard JEDEC approved module PCB circuit design schematic and SPD; modifying standard JEDEC DDR4 double-sided UDIMM for using DDR4 downgrade types having BG1 low or high, when BG1 is equal to BG0; modifying BG0 and BG1 routes for utilizing the downgrade ICs; and in response to modifying the BG0 and BG1 routes, all other remaining signals not mentioned should follow JEDEC recommendation.
[00021] In an embodiment, the non JEDEC complaint DRAM ICs have DIMM BG0 signal connect to all IC BG0 on both front and back sides same for BG1 signal.
[00022] In an embodiment, a circuit for testing of the non JEDEC complaint DRAM Ics is designed for x8-bit ICs.
[00023] In an embodiment, the circuit has four resistors R1 to R4 for controlling all IC BG1 on the both front and back side.
[00024] In an embodiment, the circuit has a resistor R3 near to gold finger source connector and resistor R4 being near to termination.
[00025] In an embodiment, the circuit has trace width, gap, route and impedance in accordance with available JEDEC recommendation.
[00026] Various objects, features, aspects and advantages of the inventive subject matter will become more apparent from the following detailed description of preferred embodiments, along with the accompanying drawing figures in which like numerals represent like components.
[00027] FIG. 1A (Prior Art) illustrates an exemplary circuit with standard JEDEC BG0 and BG1 connections, where Dual-In Line Memory Module (DIMM) Bank Group address (BG0) signal (DIMM_BG0) 102 and DIMM_BG1 signal 104 commonly connect a plurality of ICs106-1 to 106-16 of a DRAM 100 on both the front as well as back sides (i.e. 106-1 to 106-8 on the back side, and 106-9 to 106-16 on the back side). Each IC 106 has a BG0 and BG1 which can be connected with the DIMM signal lines as presented in the figure.
[00028] FIG. 1B illustrates downgrade BG0 and BG1 connection in accordance with an embodiment of the present disclosure. FIG. 1B illustrates a Dynamic Random Access Memory (DRAM) 150 comprising a plurality of back-side and corresponding front-side integrated circuits (ICs) 156 (156-1 to 156-16) of which at least one IC is a downgrade IC, wherein said plurality of ICs 156 can be configured such that Dual-In Line Memory Module (DIMM) Bank Group 0 (BG0) signal 152 connects to all BG0s of front-side and back-side ICs 156, and wherein all BG1s of said front-side and back-side ICs 156 are controlled by a plurality of resisters.
[00029] In an aspect, the DRAM can be non-JEDEC compliant. DRAM can, in an exemplary aspect, be a Double Data Rate (DDR) 4 Synchronous DRAM.
[00030] In an aspect, the plurality of resisters can include four resisters (R1 to R4), wherein resister R3 can be provided near to gold finger source connector, and wherein resister R4 can be provided near to termination. In an aspect, when BG1 of the ICs 156 is low, resister R1 can be used, and when BG1 of the ICs 156 is high, resister R2 can be used. Furthermore, when BG1 = BG0, resisters R3 and R4 can beused.
[00031] In an aspect, circuit of the DRAM can be tested for BG1 when it is low or high.
[00032] In another aspect, the DRAM can include 8 back-side ICs and corresponding 8 front-side ICs.
[00033] In an embodiment, the exemplary circuit which is a downgrade PCB as shown has been designed for x8-it ICs.
[00034] In an embodiment of the present invention, a standard (prior art) JEDEC DDR4 double-sided UDIMM can be modified for using DDR4 downgrade types having BG1 low or high, when BG1 is equal to BG0. As part of the modified PCB construction of the proposed DRAM, BG0 and BG1 routes have been modified for utilizing downgrade ICs. Upon modifying the BG0 and BG1 routes remaining signals on the circuit can be required to follow JEDEC recommendation.
[00035] In an embodiment, for the presented downgrade PCB design, as explained above with reference to FIG. 1B, Dual In Line Memory Module (DIMM) BG0 signal can connect to all ICs BG0 on front and back sides. Similarly, for the downgrade PCB design, four resistors can be provided, wherein resistors R1 to R4 can be added to control all ICs BG1 on both the front and the back sides.In an aspect, resistor R3 can be provided near to gold finger source connector, and resistor R4 can be provided near to termination.
[00036] In an embodiment, all elements such as trace width, route and impedance can be maintained as per JEDEC recommendations.
[00037] In an exemplary embodiment, register options for the four registers of the proposed circuit are presented as in Table 1:

R1 R2 R3 R4
BG1=Low Use
BG1=High Use
BG1=BG0 Use Use

Table 1: Register Options
[00038] In an embodiment, the proposed circuit can be tested for BG1 when it is Low or High. In an embodiment, to facilitate the DRAM modules to be workable, the proposed disclosure facilitates customizing (x16) Serial Presence Detect (SPD) as provided for 512x8 chips. For example :
Byte 4: 0x84 => 0x44
Byte 12 (0x0C): 0x01 => 0x02 (Single sided)
Byte 12 (0x0C): 0x09 => 0x0A (Double sided)
[00039] FIG. 2 illustrates an exemplary printed circuit board in accordance with an embodiment of the present disclosure.
[00040] In an embodiment, the exemplary printed circuit board has DRAM ICs that are non-complaint to JEDEC standards and are used for testing of the circuit while avoiding any issues and loss to the circuit.
[00041] Thus, it will be appreciated by those of ordinary skill in the art that the diagrams, schematics, illustrations, and the like represent conceptual views or processes illustrating systems and methods embodying this invention. The functions of the various elements shown in the figures may be provided through the use of dedicated hardware as well as hardware capable of executing associated software. Similarly, any switches shown in the figures are conceptual only. Their function may be carried out through the operation of program logic, through dedicated logic, through the interaction of program control and dedicated logic, or even manually, the particular technique being selectable by the entity implementing this invention. Those of ordinary skill in the art further understand that the exemplary hardware, software, processes, methods, and/or operating systems described herein are for illustrative purposes and, thus, are not intended to be limited to any particular named.
[00042] While embodiments of the present invention have been illustrated and described, it will be clear that the invention is not limited to these embodiments only. Numerous modifications, changes, variations, substitutions, and equivalents will be apparent to those skilled in the art, without departing from the spirit and scope of the invention, as described in the claim.
[00043] In the foregoing description, numerous details are set forth. It will be apparent, however, to one of ordinary skill in the art having the benefit of this disclosure, that the present disclosure can be practiced without these specific details. In some instances, well-known structures and devices are shown in block diagram form, rather than in detail, to avoid obscuring the present invention.
[00044] While the foregoing describes various embodiments of the disclosure, other and further embodiments of the disclosure may be devised without departing from the basic scope thereof. The disclosure is not limited to the described embodiments, versions or examples, which are included to enable a person having ordinary skill in the art to make and use the disclosure when combined with information and knowledge available to the person having ordinary skill in the art.

CLAIMS:1. A Dynamic Random Access Memory (DRAM) comprising a plurality of back-side and corresponding front-side integrated circuits (ICs) of which are all Downgrade IC of same downgrade type and density , wherein said plurality of ICs are configured such that Dual-In Line Memory Module (DIMM) Bank Group address (BG0) signal connects to all BG0s of front-side and back-side ICs, and wherein all BG1s of said front-side and back-side ICs are controlled by a plurality of resisters.
2. The DRAM as claimed in claim 1, wherein said DRAM is non-JEDEC compliant.
3. The DRAM as claimed in claim 1, wherein said DRAM is a Double Data Rate (DDR) 4 Synchronous DRAM.
4. The DRAM as claimed in claim 1, wherein said plurality of resisters comprise four resisters (R1 to R4), wherein resister R3 is provided near to gold finger source connector, and wherein resister R4 is provided near to termination.
5. The DRAM as claimed in claim 4, wherein when BG1 of the ICs is low, resister R1 is used, and when BG1 of the ICs is high, resister R2 is used.
6. The DRAM as claimed in claim 4, wherein when BG1 = BG0, R3 and R4 are used.
7. The DRAM as claimed in claim 1, wherein circuit of said DRAM is tested for BG1 when it is low or high.
8. The DRAM as claimed in claim 1, wherein said DRAM comprises 8 back-side ICs and corresponding 8 front-side ICs.