Claims:We claim:
1. A computing device (1000) having fourteen-transistor static random-access memory (14T SRAM) cells (210), wherein each 14T SRAM cell (210) comprises:
a first inverter (1) comprising a first pull-up transistor (P3), a first pull-down transistor (N3), and a first middle transistor (P9) coupled therebetween;
a second inverter (2) comprising a second pull-up transistor (P5), a second pull-down transistor (N1), and a second middle transistor (P7) coupled therebetween;
a third inverter (3) comprising a third pull-up transistor (P6), a third pull-down transistor (N2), and a third middle transistor (P8) coupled therebetween;
a fourth inverter (4) comprising a fourth pull-up transistor (P4), a fourth pull-down transistor (N4), and a fourth middle transistor (P10) coupled therebetween;
a first access transistor (P1) at its drain coupled to a first storage node (A) provided between the first pull-up transistor (P3) and the first middle transistor (P9); and
a second access transistor (P2) at its drain coupled to a fourth storage node (B) provided between the fourth pull-up transistor (P4) and the fourth middle transistor (P10);
wherein the fourth middle transistor (P10) at its gate is coupled to a second storage node (C) provided between the second pull-up transistor (P5) and the second middle transistor (P7),
wherein the first middle transistor (P9) at its gate is coupled to a third storage node (D) provided between the third pull-up transistor (P6) and the third middle transistor (P8),
wherein sources of the second pull-up transistor (P5) and the third pull-up transistor (P6) are coupled to gates of the first pull-up transistor (P3) and the fourth pull-up transistor (P4), respectively.

2. The device as claimed in claim 1, wherein each of the middle transistors (P9, P7, P8, P10) is made up of P-channel metal-oxide semiconductor (PMOS) having a threshold voltage lesser than its corresponding pull-up and pull-down transistor.

3. The device as claimed in claim 1, wherein gates of the access transistors (P1, P2) are coupled to a word line (WL).

4. The device as claimed in claim 1, wherein sources of the first (P1) and the second (P2) access transistors are coupled to a biline (BL) and a bitline bar (BLB), respectively.

5. The device as claimed in claim 1, wherein sources of the first pull-up transistor (P3) and the fourth pull-up transistor (P4) are coupled to a VDD (voltage drain drain) pin.

6. The device as claimed in claim 1, wherein sources of the first pull-down (N3), the second pull-down (N1), the third pull-down (N2) and the fourth pull-down (N4) transistors are coupled to a ground (GND/VSS) pin.

7. The device as claimed in claim 1, wherein the access transistors (P1, P2) are configured to be activated during write and read operations, and the access transistors (P1, P2) are configured to be deactivated during hold operation.

8. The device as claimed in claim 7, wherein the first pull-up (P3), the second middle (P7), the second pull-down (N1), the third pull-up (P6), the fourth middle (P10), and the fourth pull-down (N4) transistors are configured to be deactivated while the remaining transistors of the inverters (1, 2, 3, 4) are configured to be activated, and vice versa to perform the write operation.

9. The device as claimed in claim 7, wherein the first middle (P9), the first pull-down (N3), the second pull-up (P5), the third middle (P8), the third pull-down (N2) and the fourth pull-up (P4) transistors are configured to be deactivated while the remaining transistors of the inverters (1, 2, 3, 4) are configured to be activated, and vice versa to perform the read operation.

10. The device as claimed in claim 7, wherein the first pull-up (P3), the second middle (P7), the second pull-down (N1), the third pull-up (P6), the fourth middle (P10), and the fourth pull-down (N4) transistors are configured to be deactivated while the remaining transistors of the inverters (1, 2, 3, 4) are configured to be activated, and vice versa to perform the hold operation.
, Description:FIELD OF THE INVENTION
The present invention relates to static random-access memory used in computing/processing devices for aerospace/terrestrial applications. More particularly, the present invention relates to computing devices having fourteen transistor static random-access memory (14T SRAM) cells which can resilience to any single event upset and single event double node upset at their storage nodes. As compared with the existing SRAM devices, the 14T SRAM cell is advantageous in term of minimal power consumption, and read/write/hold stability in radiation environment.

BACKGROUND OF THE INVENTION
SRAM based memories are extensively used to store the data in aerospace and terrestrial applications. However, the SRAM devices are likely to suffer from radiation effects which may cause single event upset (SEU) or single event double node upset (SEDNU). A single-event upset (SEU), also known as a single-event error (SEE), is a change of state caused by one single ionizing particle (ions, electrons, photons...) striking a sensitive node in a micro-electronic device, such as in a microprocessor, semiconductor memory, or power transistors. The state change is a result of the free charge created by ionization in or close to an important node of a logic element (e.g., memory "bit"). The error in device output or operation caused as a result of the strike is called an SEU or a soft error.

Cosmic rays come from all directions and consist of approximately 85% protons, 14% alpha particles, and 1% heavy ions, together with X-ray and gamma-ray radiation. Most effects are caused by particles with energies between 0.1 and 20 GeV. The atmosphere filters most of these, so they are primarily a concern for spacecraft and high-altitude aircraft, but can also affect ordinary computers on the surface. Solar particle events come from the direction of the sun and consist of a large flux of high-energy (several GeV) protons and heavy ions, again accompanied by X-ray radiation. Nuclear reactors produce gamma radiation and neutron radiation which can affect sensor and control circuits in nuclear power plants. Therefore, a need arises to protect the computing/processing devices/circuitry from these radiations.

One of the best solutions to provide soft error tolerant SRAMs is to use radiation hardening techniques. Radiation hardening is a process of making electronic components and circuits resistant to damage or malfunction caused by high levels of ionizing radiation (particle radiation and high-energy electromagnetic radiation), especially for environments in outer space (especially beyond the low Earth orbit), around nuclear reactors and particle accelerators, or during nuclear accidents or nuclear warfare. Typical physical radiation-hardening techniques are using insulating substrates, utilizing bipolar integrated circuits, adopting radiation-tolerant SRAM. Typical logical radiation-hardening techniques are using error correcting memory, utilizing redundant elements, adopting a watchdog timer.

These radiation hardening techniques or approaches may be divided into the three sub-approaches. The first approach is based on the layout-level. This approach is not convenient for subnanometer technologies because of its intricate design rules. The second approach is based on the system-level, as they apply error correction and detection codes (ECC) at the system level to protect from radiation effect. However, the second approach has a disadvantage of its high delay due to the more complex circuit of the decoder and encoder. The third approach is based on circuit-level that involves circuit changes. The circuit-level as referred radiation-hardened based design (RHBD) can provide less delay with more resilience from soft errors.

The circuit-level approach is preferable over the layout and system-level because of its high resilience from radiation and high-speed. The triple modular redundancy (TMR) is a commonly used circuit-level approach to protect the memory from radiation effects like a soft error. The main drawbacks of TMR are high power dissipation and large area. The most popular circuit-level hardening techniques approach with adding additional transistors on a standard 6T cell or proposing new hardened SRAM cells. In recent years, the researchers have reported many RHBD cells like DICE-12T, QUATRO-10T, QUATRO-12T, RHBD-12T, QUCCE-12T to provide soft errors resilience, especially for SEU. Very few researchers have reported the RHBD SRAM cells for SEDNU tolerance like RHBD-13T, RHBD-14T, RSP-14T, SRRD12T, and DNUSRM with compromising the power, stability, and speed. While designing a radiation-hardened circuit, there is a trade-off between soft error tolerance, power, and speed.

Therefore, in view of the above limitations of the conventional/existing approaches, techniques, computing/memory devices, there exists a need to develop an improved approach, computing/memory device and method which would in turn address a variety of issues including, but not limited to, quick recovery from radiation damage, correcting soft error (SEU, SEDNU), low power consumption, read/write/hold stability suitable for aerospace/terrestrial applications. Moreover, it is desired to develop a technically advanced computing/memory device for aerospace/terrestrial applications, which includes all the advantages of the conventional/existing techniques/methodologies and overcomes the deficiencies of such techniques/methodologies.

OBJECT OF THE INVENTION
It is an object of the present invention to protect the computing devices from soft error (SEU, SEDNU) and radiation damage.

It is another object of the present invention to improve read/write/hold stability in the computing/memory device used in aerospace/terrestrial applications.

It is one more object of the present invention to minimize power consumption in the computing/memory device.

It is a further object of the present invention to provide a computing device integrated with fourteen-transistor static random-access memory (14T SRAM) cells.

SUMMARY OF THE INVENTION
The following presents a simplified summary of one or more aspects in order to provide a basic understanding of such aspects. This summary is not an extensive overview of all contemplated aspects, and is intended to neither identify key or critical elements of all aspects nor delineate the scope of any or all aspects. The summary’s sole purpose is to present some concepts of one or more aspects in a simplified form as prelude to the more detailed description that is presented later.

In one aspect, the present invention provides a computing device comprising a processor coupled with a static random-access memory (SRAM) device. The SRAM device comprises fourteen-transistor based memory/bit cells (i.e., 14T SRAM memory/bit cells). Each 14T SRAM memory/bit cells comprises four (first, second, third and fourth) inverters cross coupled between two (first and second) access transistors. The second and the third inverters are positioned between the first and the fourth transistors. Each inverter comprises a pull-up transistor, a pull-down transistor, and a middle low threshold transistor coupled therebetween. Each inverter comprises a storage node between the pull-up transistor and the middle transistor. Drains of the two access transistors are coupled to the storage nodes of the first and the fourth inverters. Gates of the middle transistors of the fourth and the first inverters are coupled to the storage nodes of the second and the third inverters, respectively. Sources of the pull-up transistors of the second and the third inverters are coupled to gates of the pull-up transistors of the first and the fourth inverters, respectively.

Other aspects, advantages, and salient features of the present invention will become apparent to those skilled in the art from the following detailed description, which delineate the present invention in different embodiments.

BRIEF DESCRIPTION OF DRAWINGS
These and other features, aspects, and advantages of the present invention will become better understood when the following detailed description is read with reference to the accompanying figures.

Fig. 1 shows a conceptual block diagram of the computing device, in accordance with an embodiment of the present invention.

Fig. 2 shows a block diagram illustrating various circuitry/components used in the SRAM device, in accordance with an embodiment of the present invention.

Fig. 3 shows schematic diagram illustrating various components of the 14T SRAM cells, in accordance with an embodiment of the present invention.

Fig. 4 illustrates write operations performed in the 14T SRAM cells, in accordance with an embodiment of the present invention.

Fig. 5 illustrates read operations performed in the 14T SRAM cells, in accordance with an embodiment of the present invention.

Fig. 6 illustrates hold operations performed in the 14T SRAM cells, in accordance with an embodiment of the present invention.

Fig. 7 illustrates fault injection circuits for (a) 1?0 SEU, (b) 0?1 SEU used in single event upset (SEU) recovery.

Fig. 8 illustrates circuit analysis for SEU recovery of the 14T SRAM cells at (a) node “A”, (b) node “D”, transient responses for SEU recovery of the 14T SRAM cells at (c) node “A”, and (d) node “D”, in accordance with an embodiment of the present invention.

List of reference numerals
1000 computing device
100 processor
102 address bus
104 write data bus
106 read data bus
108 control bus
200 memory device (SRAM)
202 row/column decoders
204 address latch
206 write driver
208 pre-charge circuit
212 sense amplifier
214 memory array
210 14T SRAM memory/bit cells
1, 2, 3, 4 inverters
P1, P2 access transistors
P3, P5, P6, P4 pull-up transistors
N3, N1, N2, N4 pull-down transistors
P9, P7, P8, P10 middle (low threshold) transistors
A, C, D, B storage nodes
BL bitline
BLB bitline bar
DETAILED DESCRIPTION OF THE INVENTION
Various embodiments described herein are intended only for illustrative purposes and subject to many variations. It is understood that various omissions and substitutions of equivalents are contemplated as circumstances may suggest or render expedient, but are intended to cover the application or implementation without departing from the scope of the present invention. Also, it is to be understood that the phraseology and terminology used herein is for the purpose of description and should not be regarded as limiting.

The use of terms “including,” “comprising,” or “having” and variations thereof herein are meant to encompass the items listed thereafter and equivalents thereof as well as additional items. Further, the terms “an” and “a” herein do not denote a limitation of quantity, but rather denote the presence of at least one of the referenced items. Furthermore, the terms “at least one” and “one or more” herein are used to indicate one minimum number of components/features to be essentially present in the invention.

The term ‘coupled’ means any connection either direct or indirect between two or more elements and may encompass the presence of one or more intermediate elements between two elements that are connected together. The connection between the elements may be physical, logical, or a combination thereof. Further, the elements may be considered to be connected together using one or more wires/cables and/or printed electrical connections, electromagnetic energy having wavelengths in radio frequency/microwave/optical regions, as several non-limiting and non-exhaustive examples.

The term ‘computing device’ used herein to mean all type of computers, laptops, tabloids, smartphones, communication devices, artificial intelligence devices, robotic devices, and like computing (data analysis/processing/interpretation) devices.

In accordance with an embodiment of the present invention as shown in Fig. 1, the computing device (1000) comprises a processor (100) coupled with a static random-access memory (SRAM) (200) through a plurality of connections including but not limited to an address bus (102), a write data bus (104), a read data bus (106), and a control bus (108). The computing device (1000) may include all type devices associated with data processing/analysis/interpretation/communication/management which are very often suffer from (radiation damages) soft error, particularly in the field of aerospace, terrestrial and satellite-based application. The processor (100) may be microprocessor, microcontroller, digital signal processor, field programmable processor, server, or like data processing circuitry/devices. The SRAM (200) may include row/column decoders (202), address latch (204), write driver (206), pre-charge circuit (208), sense amplifier (212), and plurality of memory cells (210). The write data bus (104) is used to write data from the processor (100) to the SRAM (200). The read data bus (106) is used to read data from the SRAM (200) to the processor (100).

The computing devices (1000) may randomly access data stored in one or more memory cells (210) using the address bus (102) provided through a control unit (controller) coupled to the row/column decoders (202). The controller is further connected to the control bus (108) which may be responsible for memory read and write operation, for example providing signal/timing for read and write operations in memory cycles, other optional signals such as transfer of acknowledgement, bus request, bus grant, interrupt request, clock signal, reset signal etc.

In accordance with an embodiment of the present invention as shown in Fig. 2, the computing device (1000) may be integrated with a memory device. The memory device may be a static random-access memory (SRAM) (200). The SRAM uses bistable latching circuitry, known as a flip-flop, to store each bit of data. Once a flip-flop stores a bit, it keeps that value until the opposite value is stored in it. The SRAM may include a memory array (214) with the supporting circuitry (i.e., multiplexer, row/column decoders, pre-charge circuit, and sense amplifier) to decode addresses and perform read and write operations. The memory array (214) may include memory cells (210) for storing data. One memory cell may store a first bit of data. Similarly, another memory cell may store a second bit of data, and so on; thus, each memory cell is called as ‘bit cell’. The bit cells (210) may be fourteen-transistor based (SRAM) bit cells. In the memory array (214), the memory cells (bit cells) (210) may be arranged in horizontal rows and vertical columns. Each horizontal row of memory cells may share a wordline (WL) (for example, four wordlines WL1, WL2, WL3, WL4 for four rows of bit cells), where each vertical column of memory cells may share a pair of bitlines (BL, BLB) (for example, four bitlines BL1, BL2, BL3, BL4, and four bitline bars BLB1, BLB2, BLB3, BLB4 for four vertical rows). The size of memory array (i.e., number of memory/bit cells and rows/columns) may vary according to the application requirements.

In accordance with an embodiment of the present invention as shown in Fig. 3, the memory device comprises fourteen transistor static random access memory cells (14T SRAM cells), i.e., each bit cell has total number of 14 transistors. Each 14T SRAM cell (210) comprises four (first, second, third, fourth) inverters (1, 2, 3, 4) cross coupled between two (first, second) access transistors (P1, P2), and four (first, second, third, fourth) storage/output nodes (A, C, D, B). The second (2) and the third (3) inverters are positioned between the first (1) and the fourth (4) inventers. The first access transistor (P1) at its source side is coupled with a bitline (BL), where the second access transistor (P2) at its source side is coupled with a bitline bar (BLB). A wordline (WL) is coupled to gates of both access transistors (P1, P2). Each inverter comprises a pull-up transistor (P-channel metal-oxide semiconductor (PMOS) normal threshold transistor), a pull-down transistor (N-channel metal-oxide semiconductor (NMOS) high threshold transistor), and a middle transistor (P-channel metal-oxide semiconductor (PMOS) low threshold transistor). Each inverter comprises a storage/output node between the pull-up transistor and the middle (low threshold) transistor.

The negative (‘1’ to ‘0’) and positive (‘0’ to ‘1’) transitory pulses can be generated whenever a radiation particle strikes the reverse-biased NMOS and PMOS transistors, respectively. Hence, the PMOS are used as the access transistors (P1, P2) to avoid negative pulse changes from ‘1’ to ‘0’ at “A” and “B” due to a radiation particle. In all four inverters, the low threshold PMOS is added between NMOS and PMOS to minimize the charge sharing effect (to increase the robustness in terms of SEDNU) and to improve the voltage swing. The inputs of inverters are ‘1’?‘0’ flip immune due to the output/storage nodes (A, C, D, B) are surrounded by PMOSs. As a result, the flipping of outputs gets reduced.

In a preferred embodiment, the first inverter (1) comprises a first pull-up transistor (P3), a first pull-down transistor (N3), and a first low threshold transistor (P9) coupled therebetween. The second inverter (2) comprises a second pull-up transistor (P5), a second pull-down transistor (N1), and a second low threshold transistor (P7) coupled therebetween. The third inverter (3) comprises a third pull up transistor (P6), a third pull down transistor (N2), and a third low threshold transistor (P8) coupled therebetween. The fourth inverter (4) comprises a fourth pull up transistor (P4), a fourth pull down transistor (N4), and a fourth low threshold transistor (P10) coupled therebetween.

In a preferred embodiment, the first storage node (A) provided between the first pull-up transistor (P3) and the first low threshold transistor (P9) is coupled to drain of the first access transistor (P1). The fourth storage node (B) provided between the fourth pull up transistor (P4) and the fourth low threshold transistor (P10) is coupled to drain of the second access transistor (P2). The second storage node (C) provided between the second pull-up transistor (P5) and the second low threshold transistor (P7) is coupled to gate of the fourth low threshold transistor (P10). The third storage node (D) provided between the third pull-up transistor (P6) and the third low threshold transistor (P8) is coupled to gate of the first low threshold transistor (P9).

In a preferred embodiment, a supply voltage pin (VDD) is connected to sources of the first (P3) and the fourth (P4) pull-up transistors. All four pull-down transistors (N3, N1, N2, N4) at source sides are connected to ground pin (GND). The access transistors (P1, P2) give strong/high (VDD) and weak/low (threshold-voltage) at the output nodes (A, C, D, B). Hence, the inverters (1, 2, 3, 4) of the cell provides a voltage swing between the VDD and threshold-voltage (Vth). Therefore, the low threshold transistors (P9, P7, P8, P10) improve the voltage swing. The pull-down transistors (N3, N1, N2, N4) reduce the leakage current and enhance the stability.

In a preferred embodiment, sources of the second pull up transistor (P5) and the third pull up transistor (P6) are coupled to gates of the first pull up transistor (P3) and the fourth pull up transistor (P4), respectively. Since the second (P5) and the third (P6) pull up transistors are not connected to supply voltage (VDD), it becomes advantageous than the existing technology in terms of minimizing power consumption.

Each memory/bit cell (210) stores a bit of data. Each data bit may represent a logical zero (‘0’) value or a logical one (‘1’) value. During read/write operation of the selected memory/bit cell, a low voltage state represents a logical ‘0’ value and a relatively higher voltage state represents a logical ‘1’ value. As per general rule, if the logical ‘0’ appears at one storage node, then the logical ‘1’ will appear at its opposite node and vice versa. Therefore, if the logical ‘0’ appears at the storage node (A), then the logical ‘1’ will appear at its opposite node (B) and vice versa. Similarly, if the logical ‘0’ appears at the storage node (C), then the logical ‘1’ will appear at its opposite node (D) and vice versa. During read and write operations/modes, the access transistors (P1, P2) are remain turned ON. During hold operation/mode, the access transistors (P1, P2) are remain turned OFF.

In a write operation of a logical ‘1’ (strong voltage level) in the bit cell (210) as shown in Fig. 4a, the bitline (BL) is driven to a high voltage state (logical ‘1’) and the bitline bar (BLB) is driven to a low-voltage state (logical ‘0’), where the word line (WL) is set to a low voltage state (logical ‘0’). The access transistors (P1, P2), the first middle transistor (P9), the first pull-down transistor (N3), the second pull-up transistor (P5), the third middle transistor (P8), the third pull-down transistor (N2), and the fourth pull-up transistor (P4) are configured to be activated (turned/switched ON). At same time, the first pull-up transistor (P3), the second middle transistor (P7), the second pull-down transistor (N1), the third pull-up transistor (P6), the fourth middle transistor (P10), and the fourth pull-down transistor (N4) are configured to be deactivated (turned/switched OFF). In this circumstance, the voltage in the bitline (BL) is discharged towards the first pull-down transistor (N3) via the first node (A) of the first inverter (1), which causes a logical ‘1’ value to be written at the first storage node (A) (i.e., A gets charged). Parallelly, the bitline bar (BLB) is charged by the voltage received from the fourth pull-up transistor (P4) via the fourth node (B) of the fourth inverter (4), which causes a logical ‘0’ value to be written at the fourth storage node (B) (i.e., B gets discharged).

In a write operation of a logical ‘0’ (weak voltage level) in the bit cell (210) as shown in Fig. 4b, the bitline (BL) is driven to a low voltage state (logical ‘0’) and the bitline bar (BLB) is driven to a high-voltage state (logical ‘1’), where the word line (WL) is set to a low voltage state (logical ‘0’). The access transistors (P1, P2), the first pull-up transistor (P3), the second middle transistor (P7), the second pull-down transistor (N1), the third pull-up transistor (P6), the fourth middle transistor (P10), and the fourth pull-down transistor (N4) are configured to be activated (turned/switched ON). At same time, the first middle transistor (P9), the first pull-down transistor (N3), the second pull-up transistor (P5), the third middle transistor (P8), the third pull-down transistor (N2), and the fourth pull-up transistor (P4) are configured to be deactivated (turned/switched OFF). In this circumstance, the bitline (BL) is charged by the voltage received from the first pull-up transistor (P3) via the first node (A) of the first inverter (1), which causes a logical ‘0’ value to be written at the first storage node (A) (i.e., A gets discharged). Parallelly, the voltage in the bitline bar (BLB) is discharged towards the fourth pull-down transistor (N4) via the fourth node (B) of the fourth inverter (4), which causes a logical ‘1’ value to be written at the fourth storage node (B) (i.e., B gets charged).

In a read operation of a logical ‘1’ (strong voltage level) in the bit cell (210) as shown in Fig. 5a, the bitline (BL) and the bitline bar (BLB) are both pre-charged to a high voltage state (logical ‘1’), where the word line (WL) is set to a low voltage state (logical ‘0’). The access transistors (P1, P2), the first pull-up transistor (P3), the second middle transistor (P7), the second pull-down transistor (N1), the third pull-up transistor (P6), the fourth middle transistor (P10), and the fourth pull-down transistor (N4) are configured to be activated (turned/switched ON). At same time, the first middle transistor (P9), the first pull-down transistor (N3), the second pull-up transistor (P5), the third middle transistor (P8), the third pull-down transistor (N2), and the fourth pull-up transistor (P4) are configured to be deactivated (turned/switched OFF). In this circumstance, no current flows through the first access transistor (P1) because the first storage node (A) and the bitline (BL) have same voltage potential i.e., logical ‘1’ value. Parallelly, the fourth storage node “B” and the bitline bar (BLB) have different logical values i.e., ‘0’ and ‘1’ respectively, so the bitline bar (BLB) gets discharged towards the fourth pull-down transistor (N4). The difference voltage between the bitline (BL) and the (BLB) is detected by the sense ampli?er (212) and the logical ‘1’ value is read from the bit cell.

In a read operation of a logical ‘0’ (weak voltage level) in the bit cell (210) as shown in Fig. 5b, the bitline (BL) and the bitline bar (BLB) are both pre-charged to a high voltage state (logical ‘1’ value), where the word line (WL) is set to a low voltage state (logical ‘0’ value). The access transistors (P1, P2), the first middle transistor (P9), the first pull-down transistor (N3), the second pull-up transistor (P5), the third middle transistor (P8), the third pull-down transistor (N2), and the fourth pull-up transistor (P4) are configured to be activated (turned/switched ON). At same time, the first pull-up transistor (P3), the second middle transistor (P7), the second pull-down transistor (N1), the third pull-up transistor (P6), the fourth middle transistor (P10), and the fourth pull-down transistor (N4) are configured to be deactivated (turned/switched OFF). In this circumstance, no current flows through the second access transistor (P2) because the fourth storage node (B) and the bitline bar (BLB) have same voltage potential i.e., logical ‘1’ value. At the same time, the first storage node “A” and the bitline (BL) have different logical values i.e., ‘0’ and ‘1’ respectively, so the bitline (BL) gets discharged towards the first pull-down transistor (N3). This voltage difference between the bitline (BL) and the (BLB) is detected by the sense ampli?er (212) and the logical ‘0’ value is read from the bit cell.

In a hold operation of a logical ‘1’ (strong voltage level) in the bit cell (210) as shown in Fig. 6a, the bitline (BL), the bitline bar (BLB) and the word line (WL) are set to a high voltage state (logical ‘1’ value). The first pull-up transistor (P3), the second middle transistor (P7), the second pull-down transistor (N1), the third pull-up transistor (P6), the fourth middle transistor (P10), and the fourth pull-down transistor (N4) are configured to be activated (turned/switched ON). At same time, the access transistors (P1, P2), the first middle transistor (P9), the first pull-down transistor (N3), the second pull-up transistor (P5), the third middle transistor (P8), the third pull-down transistor (N2), and the fourth pull-up transistor (P4) are configured to be deactivated (turned/switched OFF). In this circumstance, the first node “A” and the fourth node “B” both are charged, and the bit cell holds logical ‘1’ value stored therein.

In a hold operation of a logical ‘0’ (low voltage level) in the bit cell (210) as shown in Fig. 6b, the bitline (BL), the bitline bar (BLB) and the word line (WL) are set to a high voltage state (logical ‘1’ value). The first middle transistor (P9), the first pull-down transistor (N3), the second pull-up transistor (P5), the third middle transistor (P8), the third pull-down transistor (N2), and the fourth pull-up transistor (P4) are configured to be activated (turned/switched ON). At same time, the access transistors (P1, P2), the first pull-up transistor (P3), the second middle transistor (P7), the second pull-down transistor (N1), the third pull-up transistor (P6), and the fourth middle transistor (P10), and the fourth pull-down transistor (N4) are configured to be deactivated (turned/switched OFF). In this circumstance, the first node “A” and the fourth node “B” both are charged, and the bit cell holds logical ‘0’ value stored therein.

Experiments

Soft Error Recovery Analysis
1) SEU Modeling: When a high-energy particle touches any reverse-biased drain junction of the MOS transistor, it produces a current spike due to charge movement towards the junction. Hence, the radiation instigated soft error can be occurred. A simple mark for soft error is the Qc. The Qc is the minimum charge required to accumulate at the node to change its stored value. One of the popular model to calculate Qc is a double exponential current pulse. The double exponential current pulse model is employed to emulate the effect of radiation in the SRAM. The model is expressed by
I(t) = Is × (e -t/t1 - e -t/t2 ) …………………..equation (1)
where Is is the peak current of the current pulse, t1 is the collection time constant of the junction (200 ps), t2 is the ion track establishing time constant (50 ps).
In this model, the double exponential current source has to be added at any or multi-node of the SRAM cell to check the soft error resilience.

The fault injection circuit of a negative pulse, i.e., a double exponential current source, is connected at the drain of NMOS to mimic a ‘1’?‘0’ transient as shown in Fig. 7a. Similarly, the fault injection circuit of a positive pulse, i.e., double exponential current source, is connected at the drain of PMOS to mimic a ‘0’?‘1’ transient as shown in Fig. 7b. For multi-node fault injection simulation, the double exponential current source has been added at multiple nodes of the circuit to mimic the transient or charge sharing effect.

2) Single Event Upset (SEU) Tolerance Analysis:
A device’s vulnerable area is substantially reverse-biased. As a result, the generated transient current passes from N to P diffusion. So, whenever an energy particle impacts an NMOS (PMOS), only a negative (positive) pulse can create, i.e., ‘0’ to ‘0’ or ‘1’ to ‘0’ (‘0’ to ‘1’ or ‘1’ to ‘1’) depending on the stored value. Let us consider the logic ‘0’ (i.e., “A”, “B”, “C”, “D” are ‘0’, ‘1’, ‘1’, ‘0’, respectively) is stored for the proposed 14t SRAM cell. Since the nodes “B” and “C” (‘1’) are surrounded by PMOSs, so only a positive transient is possible (‘1’ to ‘1’). Therefore, only “A” and “D” are the sensitive nodes for the proposed cell. The single event upset (SEU) recovery of the proposed cell is illustrated in the following cases.
Case 1 (SEU at node “A”): If an SEU impacts “A”, as shown in Fig. 8a, it changes from ‘0’ to ‘1’. This switches OFF (ON) P4, P5 (N1, N4). The unharmed nodes “B” and “C” maintain the P9, N3 (P3) turned ON (OFF). As a result, node “A” is rolled back to its original value (‘0’). The simulated responses of upset recovery at node “A” are delineated in Fig. 8c.
Case 2 (SEU at node “B”): In the proposed cell, the node “B” (‘1’ stored) is surrounded by PMOSs, so only a positive transient is possible (‘1’ to ‘1’). Hence the node “B” is an insensitive node.
Case 3 (SEU at node “D”): If an SEU impacts node “D”, as shown in Fig. 8b, it changes from ‘0’ to ‘1’. This switches OFF P9. However, the unharmed node “B” maintains the P3, P6 (N2) turned OFF (ON). As a result, node “A” enters into a high impedance condition and holds its value (‘0’). This turned ON the P8. As a result, the node “D” is rolled over to its original value (‘0’). The simulated response of upset recovery at node “A” is delineated in Fig. 8d.
Case 4 (SEU at node “C”): In the proposed cell, node “C” (‘1’ stored) is surrounded by PMOSs, so only a positive transient is possible (‘1’ to ‘1’). Hence the node “C” is an insensitive node.

3) Single Event Double Node Upset (SEDNU) Tolerance Analysis: As the proposed cell’s node “B” and “C” (‘1’) is surrounded by PMOSs, so only a positive transient is possible (‘1’ to ‘1’). Therefore, only “A” = ‘0’, and “D” = ‘1’ are the only sensitive nodes. The proposed cell is SEU immune and SEDNU tolerant. It may be SEDNU immune if its layout maintains a minimum distance between sensitive node pairs. To evaluate the single event double node upset (SEDNU) tolerance capacity of the proposed cell, which has four nodes (A, B, C, D), six possible node pairs (A-B, A-C, A-D, B-C, B-D, C-D) are realized. The SEDNU recovery of the proposed cell is illustrated in the following cases:
Case 1 (SEDNU at node pair “A-B”): If the node pair “A-B” is upset due to radiation strikes and charge sharing, they will be recovered. However, node “B” is insensitive to the radiation effect. This case looks like SEU on node “A” is recovered.
Case 2 (SEDNU at node pair “A-C”): If the node pair “A-C” is upset due to radiation strikes and charge sharing, they will be recovered. However, node “C” is insensitive to the radiation effect. This case looks like SEU on node “A” is recovered.
Case 3 (SEDNU at node pair “B-C”): If the node pair “B-C” is upset due to radiation strikes and charge sharing effect, then they will be recovered. However, the node “B” and “C” are insensitive to the radiation effect. This case looks like SEU on nodes “B,” and “C” are recovered.
Case 4 (SEDNU at node pair “B-D”): If the node pair “BD” is upset due to radiation strikes and charge sharing effect, they will be recovered. However, node “B” is insensitive to the radiation effect. This case looks like SEU on node “D” is recovered.
Case 5 (SEDNU at node pair “C-D”): If the node pair “CD” is upset due to radiation strikes and charge sharing effect, they will be recovered. However, node “C” is insensitive to the radiation effect. This case looks like SEU on node “D” is recovered.
Case 6 (SEDNU at node pair “A-D”): If more charge is placed at node-pair “A-D,” the cell’s stored value may vary. The charge sharing among MOSs is minimal if their separation is greater than the effective range of charge sharing.

Comparison and Evaluation of Results
Table 1 shows the overhead comparison of RHBD SRAM cells in terms of static power, total power, area, read access time (RAT), write access time (WAT), and sensitive area. The ?SP, ?TP, ?A, ?R, and ?W represent relative static power, total power, area overhead, RAT, and WAT comparisons among the proposed cell and other considered cell respectively. Here ? is the reduced cost between the proposed and the existing compared cell.
Table 1

Similarly, Table 2 shows the reliability and stability comparison of RHBD SRAM cells in terms of SEU recover-ability (SEUR), SEDNU recover-ability (SDUR), SEU critical charge, hold static noise margin (HSNM), read static noise margin (RSNM), write static noise margin (WSNM), disturb margin (DM), write margin (WM), probability of SEU occurrence (PS), and probability of logical flipping (PLF).

Table 2

A. Soft Error Tolerance Comparison:
Qc = Cnode × V DD + IP.ON × Wpulse equation (2)
The Qc as expressed in equation 2 is the product of ON-current of the stabilizing PMOS (IP.ON) times the pulse width (Wpulse) plus node capacitance Cnode times supply voltage (V DD). As V DD and Wpulse are fixed, so Qc is mainly affected by the Cnode and IP.ON. The parasitic capacitance Cnode and IP.ON are high due to strong PMOSs P7-P10 (1.8×) and more number of PMOSs in the proposed cell. It is the reason while applying a very high charge at nodes also gives perfect upset recovery not only for ‘0’ to ‘1’ but also for ‘1’ to ‘0’ upset. Further, the proposed SRAM cell has a better SER than other SRAM cells due to stronger PMOSs and higher critical charge.

B. Comparisons of Power, Speed, and Area Cost:
The leakage current of the SRAM cell is the primary source of total power consumption, especially in the hold mode. The static and total power cost of the proposed cell is less compared to other considered RHBD cells, as reported in Table 1. As in the proposed cell’s internal structure, the source of P5 and P6 are connected to the gate of P3 and P4 or drain of P4 and P3 respectively instead of direct V DD. It gives less current, which is responsible for achieving less total power cost. Additionally, the leakage current is decreased significantly. Since the potential at the source of P6 and P5 are ‘0’ and weak ‘1’ rather than the strong ‘1’ (VDD) respectively during hold mode. Thus, it makes the NMOSs drain to collect charge hardly and gives less leakage current. Also, the proposed cell is used high Vth transistors (N3, N1, N2, and N4) to minimize the leakage current. Therefore, the static, dynamic, and total power of the proposed cell are reduced compared to all existing SRAM cells.

The WAT (write access time) and RAT (read access time) comparison of the proposed cell with other considered cells is reported in Table 1. The reduced driving capabilities of nodes “A” and “B” (due to low Vth of MOSs) can decrease the degree of difficulty of writing data so that the WAT should be reduced. However, its write access time increases, because of the increased feedback path length and node capacitance. The proposed cell uses two ended circuit for write operation at node “A” and “B”. While writing ‘1’ on the cell means to write ‘1’ at node “A”, the PMOS access transistors P1 and P2 will be switched ON by giving logic ‘0’ to WL. In the proposed 14T cell, during write mode, “A” holds weak ‘0’, as it is pulled down by PMOS. Hence, “A” is charged faster, and the writing process is faster. Additionally, since “B” is first pulled up via a PMOS, charging “B” is more straightforward. Furthermore, because “A” and “B” are also the terminals of a cross-coupled latch, a shift in one node causes another to alter its value at the same time. RAT mainly depends on the length of the read path and read current. In the proposed cell, the PMOSs are used as an access transistor to avoid the negative transient induced by radiation particles at nodes “A” and “B”. The proposed cell gives loss of threshold voltage (less driving voltage) at the nodes “A” and “B” due to PMOS transistors P9 and P10. Hence, the proposed cell’s read access time is a little high compared to few considered cells. The uses of low threshold PMOSs (P7- P10) give minimal effect on read operation and read access time. Therefore, the RAT of the SEDNU tolerant proposed cell is moderate between considered SEDNU tolerant cells.

The area overhead of SEDNU tolerant 14T proposed cell is less than SEDNU tolerant SRAM cells like RSP-14T, RHBD-13T, DNUSRM and RHBD-14T due to number and size of transistor.

C. Stability Comparison
The stability of the SRAMs is defined by the static noise margins (SNMs), and it is characterized by HSNM, WSNM, and RSNM in the hold, write and read mode, respectively. The comparison of HSNM, RSNM, WSNM, DM, and RM of the cells is reported in Table 2. The proposed cell has a better HSNM than most of the cells due to the larger feedback path during hold mode and high Vth transistors, which will not be affected by smaller noise. In the write mode of the proposed cell, high Vth pull-down transistors, less driving voltage of nodes “A” and “B” due to higher length of write path, and double-ended write operation improve the WSNM. The proposed cell has the better RSNM due to the increased length of the read path, stronger pull-down transistors, and reduced driving voltages at nodes “A” and “B”.

Particularly, the present invention provides following advantages including but not limited to:
• Optimize static power and total power consumption.
• Improve read/write/hold stability.
• Tolerate not only SEUs but also provide adequate SEDNUs protection.
• The write speed is increased compared to other SEDNU protected cells.
• The proposed cell is a better choice for critical aerospace and terrestrial applications where the SEDNUs is a severe issue.

The foregoing descriptions of exemplary embodiments of the present invention have been presented for purposes of illustration and description. They are not intended to be exhaustive or to limit the invention to the precise forms disclosed, and obviously many modifications and variations are possible in light of the above teaching. The exemplary embodiment was chosen and described in order to best explain the principles of the invention and its practical application, to thereby enable the persons skilled in the art to best utilize the invention and various embodiments with various modifications as are suited to the particular use contemplated. It is understood that various omissions, substitutions of equivalents are contemplated as circumstance may suggest or render expedient, but is intended to cover the application or implementation without departing from the scope of the claims of the present invention.