Abstract: In an embodiment, the power semiconductor device (1) comprises: - a semiconductor body (2) having a source region (21) of a first conductivity type and a well region (22) of a second conductivity type different from the first conductivity type, and the well region (22) comprises a channel region (220) directly at the source region (21), - a gate electrode (31) arranged at the semiconductor body (2) and assigned to the channel region (220), and - a gate insulator (4) directly between the semiconductor body (2) and the gate electrode (31), wherein the gate insulator (4) has a non-uniform thickness Tox along the channel region (220) so that, along the channel region (220), the gate insulator (4) is thickest in a first part (44) remote from the source region (21).
| # | Name | Date |
|---|---|---|
| 1 | 202447002065-STATEMENT OF UNDERTAKING (FORM 3) [11-01-2024(online)].pdf | 2024-01-11 |
| 2 | 202447002065-PROOF OF RIGHT [11-01-2024(online)].pdf | 2024-01-11 |
| 3 | 202447002065-PRIORITY DOCUMENTS [11-01-2024(online)].pdf | 2024-01-11 |
| 4 | 202447002065-FORM 18 [11-01-2024(online)].pdf | 2024-01-11 |
| 5 | 202447002065-FORM 1 [11-01-2024(online)].pdf | 2024-01-11 |
| 6 | 202447002065-DRAWINGS [11-01-2024(online)].pdf | 2024-01-11 |
| 7 | 202447002065-DECLARATION OF INVENTORSHIP (FORM 5) [11-01-2024(online)].pdf | 2024-01-11 |
| 8 | 202447002065-COMPLETE SPECIFICATION [11-01-2024(online)].pdf | 2024-01-11 |
| 9 | 202447002065-FORM-26 [31-03-2024(online)].pdf | 2024-03-31 |
| 10 | 202447002065-FORM 3 [21-06-2024(online)].pdf | 2024-06-21 |