Abstract: In at least one embodiment, the power semiconductor device (1) comprises: - a semiconductor body (2) having a source region (21) of a first conductivity type and a well region (22) of a second conductivity type different from the first conductivity type, and the well region (22) comprises a channel region (220) starting directly at the source region (21), and - a gate insulator (4) directly between the semiconductor body (2) and a gate electrode (31), wherein the gate electrode (4) has a non-uniform work function profile (6) along the channel region (220), such that a threshold voltage (Vth) is highest in a first section (61) remote from the source region (21).
| # | Name | Date |
|---|---|---|
| 1 | 202447002078-STATEMENT OF UNDERTAKING (FORM 3) [11-01-2024(online)].pdf | 2024-01-11 |
| 2 | 202447002078-PROOF OF RIGHT [11-01-2024(online)].pdf | 2024-01-11 |
| 3 | 202447002078-PRIORITY DOCUMENTS [11-01-2024(online)].pdf | 2024-01-11 |
| 4 | 202447002078-FORM 18 [11-01-2024(online)].pdf | 2024-01-11 |
| 5 | 202447002078-FORM 1 [11-01-2024(online)].pdf | 2024-01-11 |
| 6 | 202447002078-DRAWINGS [11-01-2024(online)].pdf | 2024-01-11 |
| 7 | 202447002078-DECLARATION OF INVENTORSHIP (FORM 5) [11-01-2024(online)].pdf | 2024-01-11 |
| 8 | 202447002078-COMPLETE SPECIFICATION [11-01-2024(online)].pdf | 2024-01-11 |
| 9 | 202447002078-FORM-26 [16-02-2024(online)].pdf | 2024-02-16 |
| 10 | 202447002078-FORM 3 [21-06-2024(online)].pdf | 2024-06-21 |
| 11 | 202447002078-FER.pdf | 2025-10-22 |
| 12 | 202447002078-FORM 3 [19-11-2025(online)].pdf | 2025-11-19 |
| 13 | 202447002078-FORM 3 [19-11-2025(online)]-1.pdf | 2025-11-19 |
| 1 | 202447002078_SearchStrategyNew_E_POWERSEMICONDUCTORDEVICEANDPRODUCTIONMETHODE_09-10-2025.pdf |