We Claim:
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A silicon carbide power device (100; 200; 300; 400; 500; 600; 700; 800),
comprising:
a first conductivity-type substrate (20; 25) having a first main side (21) and a second main side (22) opposite to the first main side (21); a plurality of silicon carbide layer stacks (30; 230; 330; 430; 530; 630; 730; 830) arranged on the first main side (21) of the substrate (20; 25), wherein each silicon carbide layer stack (30; 230; 330; 430; 530; 630; 730; 830) comprises the following layers stacked on the first main side (21) in a direction away from the first main side (21): a first conductivity-type drain layer (35; 235; 335; 435; 735) on the substrate (20; 25), a second conductivity-type channel layer (37; 237; 337; 437; 537; 637) on the drain layer (35; 235; 335; 435; 735) and a first conductivity­type source layer (36; 236; 336; 436; 836) on the channel layer (37; 237; 337; 437; 537; 637), the second conductivity-type being different from the first
conductivity-type;
a continuous first insulating layer (40; 240; 340; 440; 540; 640), which comprises a plurality of first insulating layer portions (42; 242; 342; 442; 542; 642) respectively extending directly on a lateral surface of a corresponding one of the plurality of silicon carbide layer stacks (30; 230; 330; 430; 530; 630; 730; 830) so that the plurality of first insulating layer portions (42; 242; 342; 442; 542; 642) laterally covers and laterally surrounds at least the drain layer (35; 235; 335; 435; 735) and the channel layer (37; 237; 337; 437; 537; 637; 737) of each silicon carbide layer stack (30; 230; 330; 430; 530; 630; 730; 830), and a second insulating layer portion (43; 243; 343; 443) extending on the first main side (21) between the plurality of first insulating layer portions (42; 242; 342; 442; 542;
642); and
a gate electrode layer (45) extending directly on the first insulating layer (40; 240; 340; 440; 540; 640) such that the gate electrode layer (45) is electrically separated from each one of the plurality of silicon carbide layer stacks (30; 230; 330; 430 530; 630; 730; 830) by the first insulating layer portions (42; 242; 342; 442; 542;
642),
wherein each one of the plurality of silicon carbide layer stacks (30; 230; 330; 430; 530; 630; 730; 830) has a shape of a pillar protruding from the first main side (21), such that each point of each channel layer (37; 237; 337; 437; 537; 637; 737) is laterally sandwiched between two opposing portions of the gate electrode layer (45), wherein the two opposing portions of the gate electrode layer (45) have a distance (d) of less than 2 pm along a straight line extending through that point of that channel layer (37; 237; 337; 437; 537; 637; 737). 2. The silicon carbide power device (100; 200; 300; 400; 500; 600; 700; 800) according to claim 1, wherein the channel layer (37; 237; 337; 437; 537; 637; 737) comprises a 3C-SiC and the drain layer (35; 235; 335; 435; 735) comprises a 4H-
SiC or a 6H-SiC.
3. The silicon carbide power device (700) according to claim 1 or 2, wherein the substrate (20; 25) has a doping concentration above 1017 cm'3 or above 5 1017 cm’ 3, and wherein the drain layer (735) of each silicon carbide layer stack (730) is in direct contact with the substrate (20; 25).
4. The silicon carbide power device (100; 200; 300; 400; 700; 800) according to any one of claims 1 to 3, wherein the first insulating layer portions (42; 242; 342; 442) are tube-shaped, respectively surrounding laterally a corresponding one of the plurality of silicon carbide layer stacks (30; 230; 330; 430; 730; 830) to form a plurality o f vertical gate-all-around field effect transistor cells (50). 5. The silicon carbide power device (100; 200; 300; 400; 700; 800) according to claim 4, wherein the channel layer (37; 237; 337; 437; 737) of each silicon carbide layer stack (30; 230; 330; 430; 730; 830) has a largest horizontal width (w) in any horizontal direction parallel to the first main side (21), which largest horizontal width (w) is below 2 pm, or below 1 pm.
6. The silicon carbide power device (100; 200; 300; 400; 500; 600; 700; 800) according to any one of claims 1 to 5, wherein the first insulating layer (40; 240; 340; 440; 540; 640) is a silicon oxide layer or a silicon nitride layer.
A method for manufacturing a silicon carbide power device (100; 200; 300; 400; 500; 600; 700; 800), the method comprising the following steps: providing a first conductivity substrate (20; 25); forming a sacrificial layer (60) on a first main side (21) of the substrate (20; 25); structuring the sacrificial layer (60) to form a plurality o f sacrificial structures (65) protruding from the first main side (21) and having a shape of a pillar or a fin, wherein each sacrificial structure (65) comprises a first end (65A) adjacent to the substrate (20; 25) and a second end (65B) opposite to the first end (65A); forming a continuous insulating material layer (70) on the plurality of sacrificial structures (65) and on the first main side (21); thereafter removing a portion of an insulating material layer (70) on the second end (65B) of each sacrificial structure (65) to expose the second end (65B) of each sacrificial structure (65), while the remaining insulating material layer (70’) covers a lateral surface of each sacrificial structure (65), wherein at least a part of the remaining insulating material layer (70’) forms a first insulating layer (40; 240; 340; 440; 540; 640) in the silicon carbide power device (100; 200; 300; 400; 500; 600; 700; 800);
thereafter removing each sacrificial structure (65) by selective etching to form a plurality of cavities (75) in the remaining insulating material layer (70’), wherein an exposed portion (24) of the first main side (21) is exposed at a bottom of each
cavity (75);
forming a first silicon carbide layer of the first conductivity-type selectively on the exposed portion (24) of the first main side (21) in each cavity (75) to form the drain layers (35; 235; 335; 435; 735);
forming a second silicon carbide layer of the second conductivity-type selectively on the first silicon carbide layer in each cavity (75) to form channel layers (37; 237; 337; 437; 537; 637; 737); forming a third silicon carbide layer of the first conductivity-type selectively on the second silicon carbide layer in each cavity (75) to form source layers (36; 236;
336; 436; 836); and
forming a gate electrode layer (45) on that part of the remaining insulating material layer (70’) which forms the first insulating layer (40; 240; 340, 440, 540; 640) in the silicon carbide power device (100; 200; 300, 400; 500; 600; 700; 800), wherein the finished silicon carbide power device (100; 200; 300; 400; 500; 600; 700; 800) comprises:
the first conductivity-type substrate (20; 25) having the first main side (21) and a second main side (22) opposite to the first main side (21); a plurality of silicon carbide layer stacks (30; 230; 330; 430; 530; 630; 730; 830) arranged on the first main side (21) of the substrate (20; 25), wherein each silicon carbide layer stack (30; 230; 330; 430; 530; 630; 730; 830) comprises the following layers stacked on the first main side (21) in a direction away from the first main side (21): the first conductivity-type drain layer (35; 235; 335; 435; 735) on the substrate (20; 25), the second conductivity-type channel layer (37; 237; 337; 437; 537; 637) on the drain layer (35; 235; 335; 435; 735) and the first conductivity-type source layer (36; 236; 336; 436, 836) on the second conductivity-type channel layer (37; 237; 337; 437; 537; 637), the second conductivity-type being different from the first conductivity-type; the continuous first insulating layer (40; 240; 340; 440; 540; 640), which comprises a plurality of first insulating layer portions (42; 242; 342; 442; 542; 642) respectively extending directly on a lateral surface of a corresponding one of the plurality of silicon carbide layer stacks (30; 230; 330; 430; 530; 630; 730; 830) so that the plurality of first insulating layer portions (42; 242; 342; 442; 542; 642) laterally covers and laterally surrounds at least the drain layer (35; 235; 335; 435; 735) and the channel layer (37; 237; 337; 437; 537; 637; 737) of each silicon carbide layer stack (30; 230; 330; 430; 530; 630; 730; 830), and a second insulating layer portion (43; 243; 343; 443) extending on the first main side (21) between the plurality of first insulating layer portions (42, 242; 342; 442; 542,
642); and the gate electrode layer (45) extending directly on the first insulating layer (40; 240; 340; 440; 540; 640) such that the gate electrode layer (45) is electrically separated from each one of the plurality of silicon carbide layer stacks (30; 230; 330; 430; 530; 630; 730; 830) by the first insulating layer portions (42; 242; 342;
442; 542; 642),
wherein each one of the plurality of silicon carbide layer stacks (30; 230; 330; 430; 530; 630; 730; 830) has a shape of the pillar or the fin protruding from the first main side (21), such that each point of each channel layer (37; 237; 337; 437; 537; 637; 737) is laterally sandwiched between two opposing portions of the gate electrode layer (45), wherein the two opposing portions of the gate electrode layer (45) have a distance (d) of less than 2 pm along a straight line extending through that point of that channel layer (37; 237; 337; 437; 537; 637; 737). 8. The method according to claim 7, wherein the sacrificial layer (60) comprises an
amorphous silicon.
9. The method according to claim 7 or 8, wherein the insulating material layer (70) is formed by thermal oxidation.
10. The method according to any one of claims 7 to 9, comprising a step of forming a second insulating layer (44; 744) on the remaining insulating material layer (70’) before forming the gate electrode layer (45), such that after forming the gate electrode layer (45), the second insulating layer (44; 744) is sandwiched in a vertical direction perpendicular to the first main side (21) between the remaining insulating material layer (70’) and the gate electrode layer (45). 11. The method according to claim 10, wherein the second insulating layer (44, 744) is a spin-on-glass layer
12. The method according to any one of claims 7 to 11, wherein each sacrificial structure (65) has a length (L) in a vertical direction perpendicular to the first main side (21) in a range between 50 nm and 10 pm, exemplarily in a range between
5 pm and 10 pm.
13. The method according to any one of claims 7 to 12, wherein forming the first silicon carbide layer, forming the second silicon carbide layer and forming the the gate electrode layer (45) extending directly on the first insulating layer (40; 240; 340; 440; 540; 640) such that the gate electrode layer (45) is electrically separated from each one of the plurality of silicon carbide layer stacks (30; 230; 330; 430; 530; 630; 730; 830) by the first insulating layer portions (42; 242; 342;
442; 542; 642),
wherein each one of the plurality of silicon carbide layer stacks (30; 230; 330; 430; 530; 630; 730; 830) has a shape of the pillar or the fin protruding from the first main side (21), such that each point of each channel layer (37; 237; 337; 437; 537; 637; 737) is laterally sandwiched between two opposing portions of the gate electrode layer (45), wherein the two opposing portions of the gate electrode layer (45) have a distance (d) of less than 2 pm along a straight line extending through that point of that channel layer (37; 237; 337; 437; 537; 637; 737). 8. The method according to claim 7, wherein the sacrificial layer (60) comprises an
amorphous silicon.
9. The method according to claim 7 or 8, wherein the insulating material layer (70) is formed by thermal oxidation.
10. The method according to any one of claims 7 to 9, comprising a step of forming a second insulating layer (44; 744) on the remaining insulating material layer (70’) before forming the gate electrode layer (45), such that after forming the gate electrode layer (45), the second insulating layer (44; 744) is sandwiched in a vertical direction perpendicular to the first main side (21) between the remaining insulating material layer (70’) and the gate electrode layer (45). 11. The method according to claim 10, wherein the second insulating layer (44, 744) is a spin-on-glass layer
12. The method according to any one of claims 7 to 11, wherein each sacrificial structure (65) has a length (L) in a vertical direction perpendicular to the first main side (21) in a range between 50 nm and 10 pm, exemplarily in a range between
5 pm and 10 pm.
13. The method according to any one of claims 7 to 12, wherein forming the first silicon carbide layer, forming the second silicon carbide layer and forming the third silicon carbide layer is respectively performed at a temperature below 1400°C.
The method according to any one of claims 7 to 13, wherein the step of removing the portion of the insulating material layer (70) on the second end (65B) of each sacrificial structure (65) comprises a first step of forming a continuous first masking material layer (90) on the insulating material layer (70), a second step of etching back the first masking material layer (90) to form a first masking layer (90’) exposing the portion of the insulating material layer (70) on the second end (65B) of each sacrificial structure (65), and a third step of etching the portion of the insulating material layer (70) on the second end (65B) using the first masking layer (90’) as an etching mask.
The method according to any one of claims 7 to 14, comprising a step of removing a portion of the third silicon carbide layer to expose a portion of the second silicon carbide layer; and
thereafter a step of forming a first main electrode (852) electrically contacting the third silicon carbide layer and the second silicon carbide layer, wherein the first main electrode (852) is electrically insulated from the gate electrode layer (45).