DESC:EARLIEST PRIORITY DATE:
This Application claims priority from a Provisional patent application filed in India having Patent Application No. 202241044938, filed on August 05, 2022, and titled “SYSTEM AND METHOD FOR INCREASING SPEED OF SERIALIZER AND DESERIAIZER”.
FIELD OF INVENTION
[0001] Embodiments of the present disclosure relate to the field of data communications and more particularly, a system and a method for increasing the speed of a serializer and deserializer.
BACKGROUND
[0002] Typically, a network system converts low-speed parallel data into high-speed serial data for transmitting the data at high speeds. Serializer and Deserializer (SERDES) is a pair of functional blocks commonly used in high-speed communication to convert parallel data and serial data. The basic SERDES function typically includes a parallel-to-serial converter for transmitting and a serial-to-parallel converter for receiving. Specifically, the serializer functions to convert and transmit the parallel data into serial data whereas the deserializer functions to receive and convert the serial data into the parallel data.
[0003] Parallel clock input and a set of parallel data inputs are typically found in a parallel-to-serial converter. To multiply the incoming parallel clock up to the higher serial clock rate, a Phase-Locked Loop (PLL) may be used. A parallel clock output and a set of parallel data outputs are typically found in the serial-to-parallel converter. The serial clock recovery technique may be used to recover a high-speed clock. The recovered clock is then divided down to the parallel clock rate by the Serial-to-Parallel converter. Alternatively, the serial and parallel clocks may be supplied externally.
[0004] Further, slicers are an integral part of the serializer-deserializer. The existing slicers have three phases namely, resetting the previous-phase output, sampling the current input, and regeneration of current inputs. In the existing slicers, phase-1 is assigned dedicated time whereas phase-2 and phase-3 are combined in time. In phase 1, the slicer outputs are either pulled up to supply voltage or pulled down to the ground for resetting. At the start of phase-2 and 3, the slicers’ output starts from a common mode where the slicer gain is near zero. The slicers spend some time to bring the common mode to the optimal point where the gain of the slicer is high and then starts to resolve. Due to this common mode settling time, slicers require more time to resolve.
[0005] Hence, there is a need for an improved system and method for increasing the speed of serializer and Deserializer which addresses the aforementioned issue(s).
BRIEF DESCRIPTION
[0006] In accordance with an embodiment of the present disclosure, a system for increasing the speed of a serializer and deserializer is provided. The system includes a slicer unit including a plurality of phases to scale up the speed of the serializer and de-serializer, wherein the plurality of phases includes a reset phase, a sampling phase and a regeneration phase. The reset phase resets an output by providing connection between the output and a common mode voltage through a reset switch, wherein the reset phase resets a previous output when a clock generation unit generates a high clock signal. The sampling phase is configured to amplify an input using a preamplifier and apply an amplified output at a latch input. The regeneration phase is configured to regenerate the output from the common mode voltage, wherein the regeneration phase lowers time required in the regeneration of rail-rail voltage when gain of slicer unit is high. The system further includes a superposition unit operatively coupled to the slicer unit, wherein the superposition unit combines the reset phase and the sampling phase simultaneously in time synchronization and assign a dedicated time to the regeneration phase, thereby increasing the speed of the serializer and de-serializer. Further, the system also includes a data storage unit operatively coupled to the superposition unit, wherein the data storage unit is configured to store a valid output of the superposition module at an end of the regeneration phase, wherein the data storage unit comprises at least one of a latch and a flipflop.
[0007] In accordance with another embodiment of the present disclosure, a method for increasing the speed of a serializer and deserializer is provided. The method includes resetting, by a reset phase of a slicer unit, an output by providing connection between the output and a common mode voltage through a reset switch, wherein the reset phase resets a previous output when a clock generation unit generates a high clock signal. The method also includes amplifying, by a sampling phase of the slicer unit, an input using a preamplifier and applying an amplified output at a latch input. Further, the method includes regenerating, by a regeneration phase of the slicer unit, the output from the common mode voltage, wherein the regeneration phase lowers time required in the regeneration of rail-rail voltage when gain of slicer unit is high. Further, the method also includes combining, by a superposition unit, the reset phase and the sampling phase simultaneously in time synchronization. Furthermore, the system includes assigning, by the superposition unit, a dedicated time to the regeneration phase, thereby increasing the speed of the serializer and de-serializer. Moreover, the system includes storing, by a data storage unit, a valid output of the superposition module at an end of the regeneration phase, wherein the data storage module comprises at least one of a latch and a flipflop.
[0008] To further clarify the advantages and features of the present disclosure, a more particular description of the disclosure will follow by reference to specific embodiments thereof, which are illustrated in the appended figures. It is to be appreciated that these figures depict only typical embodiments of the disclosure and are therefore not to be considered limiting in scope. The disclosure will be described and explained with additional specificity and detail with the appended figures.
BRIEF DESCRIPTION OF THE DRAWINGS
[0009] The disclosure will be described and explained with additional specificity and detail with the accompanying figures in which:
[0010] FIG. 1 is a block diagram representation of a system for increasing the speed of a serializer and deserializer is provided in accordance with an embodiment of the present disclosure;
[0011] FIG. 2 is a circuit diagram representation of a slicer unit of FIG. 1 in accordance with an embodiment of the present disclosure;
[0012] FIG. 3a and FIG. 3b are timing diagrams of multiple phases of the slicer unit of FIG. 1 in accordance with an embodiment of the present disclosure; and
[0013] FIG. 4 illustrates a flow chart representing the steps involved in a method for increasing the speed of a serializer and deserializer in accordance with an embodiment of the present disclosure.
[0014] Further, those skilled in the art will appreciate that elements in the figures are illustrated for simplicity and may not have necessarily been drawn to scale. Furthermore, in terms of the construction of the device, one or more components of the device may have been represented in the figures by conventional symbols, and the figures may show only those specific details that are pertinent to understanding the embodiments of the present disclosure so as not to obscure the figures with details that will be readily apparent to those skilled in the art having the benefit of the description herein.
DETAILED DESCRIPTION
[0015] For the purpose of promoting an understanding of the principles of the disclosure, reference will now be made to the embodiment illustrated in the figures and specific language will be used to describe them. It will nevertheless be understood that no limitation of the scope of the disclosure is thereby intended. Such alterations and further modifications in the illustrated system, and such further applications of the principles of the disclosure as would normally occur to those skilled in the art are to be construed as being within the scope of the present disclosure.
[0016] The terms “comprises”, “comprising”, or any other variations thereof, are intended to cover a non-exclusive inclusion, such that a process or method that comprises a list of steps does not include only those steps but may include other steps not expressly listed or inherent to such a process or method. Similarly, one or more devices or subsystems or elements or structures or components preceded by "comprises... a" does not, without more constraints, preclude the existence of other devices, sub-systems, elements, structures, components, additional devices, additional sub-systems, additional elements, additional structures or additional components. Appearances of the phrase "in an embodiment", "in another embodiment" and similar language throughout this specification may, but not necessarily do, all refer to the same embodiment.
[0017] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those skilled in the art to which this disclosure belongs. The system, methods, and examples provided herein are only illustrative and not intended to be limiting.
[0018] In the following specification and the claims, reference will be made to a number of terms, which shall be defined to have the following meanings. The singular forms “a”, “an”, and “the” include plural references unless the context clearly dictates otherwise.
[0019] Embodiments of the present disclosure relates to a system for increasing the speed of a serializer and deserializer. The system includes a slicer unit comprising a plurality of phases to scale up the speed of the serializer and de-serializer, wherein the plurality of phases comprises a reset phase, a sampling phase and a regeneration phase. The reset phase resets an output by providing connection between the output and a common mode voltage through a reset switch, wherein the reset phase resets a previous output when a clock generation unit generates a high clock signal. The sampling phase is to amplify an input using a preamplifier and apply an amplified output at a latch input. The regeneration phase regenerates the output from the common mode voltage, wherein the regeneration phase lowers time required in the regeneration of rail-rail voltage when gain of slicer unit is high. The system further includes a superposition unit operatively coupled to the slicer unit, wherein the superposition unit combines the reset phase and the sampling phase simultaneously in time synchronization and assign a dedicated time to the regeneration phase, thereby increasing the speed of the serializer and de-serializer. Further, the system also includes a data storage unit operatively coupled to the superposition unit, wherein the data storage unit is configured to store a valid output of the superposition module at an end of the regeneration phase, wherein the data storage unit comprises at least one of a latch and a flipflop.
[0020] FIG. 1 is a block diagram representation of a system (100) for increasing the speed of a serializer and deserializer is provided in accordance with an embodiment of the present disclosure. The system (100) includes a slicer unit (105) including a plurality of phases to scale up the speed of the serializer and de-serializer. The plurality of phases includes a reset phase (110), a sampling phase (115), and a regeneration phase (120).
[0021] The reset phase (110) resets an output of the slicer unit providing connection between the output and a common mode voltage through a reset switch. Typically, the common mode voltage is a voltage common to both input terminals of the slicer unit. As used herein, the reset switch is a button that resets the slicer unit. Typically, the outputs of the slicer unit are connected to a common mode voltage Vdd/2 through the reset switch. The reset phase (110) resets a previous output when a clock generation unit generates a high clock signal. Typically, the clock is a specific type of signal that oscillates between a high state and a low state. As used herein, the clock generator is an electronic oscillator that produces a clock signal.
[0022] The sampling phase (115) amplifies an input using a preamplifier (not shown in FIG. 1) and applies an amplified output at a latch input. The input may be a square wave. The square waves are used in digital switching circuits and are generated by binary logic devices. Generally, the square wave and two states are represented. The two states are frequently denoted as “1” and “0”, which corresponds to binary digits, also referred to as logic high and logic low which indicates the voltage. The logic “1” state corresponds to the high state and the logic “0” corresponds to the low state. Typically, the sampling phase (115) samples a current input when the clock generation unit generates a high clock signal. Typically, the pre-amplifier samples and amplifies the input signal. Sampling is a technique used to convert a continuous-time signal to a discrete-time signal. An analog signal must be converted into a discrete-time signal in digital communications. The primary goal of sampling is to reconstruct the original signal. Similarly, the primary function of the preamplifier is to extract the original signal without degrading the intrinsic signal-to-noise ratio.
[0023] The regeneration phase (120) regenerates the output from the common mode voltage. The regeneration phase (120) lowers time required in the regeneration of rail-rail voltage when gain of the slicer unit is high. As used herein, the gain is the ratio of an output voltage to an input voltage. In general, the gain describes the amplification of a signal. For example, the ratio of output current to the input current of an amplifier is referred to as current gain and the ratio of output voltage to the input voltage of the amplifier is referred to as voltage gain. The regeneration phase regenerates the current input when the clock generation unit generates a low clock signal.
[0024] The system (100) also includes a superposition unit (125) operatively coupled to the slicer unit (105). The superposition unit combines the reset phase (110) and the sampling phase (115) simultaneously in time synchronization, and assign a dedicated time to the regeneration phase, thereby increasing the speed of the serializer and de-serializer. Typically, the reset phase and the sampling phase utilizes a single clock signal for sampling and reset. The output of superposition unit is valid for a unit interval time.
[0025] Further, the system (100) includes a data storage unit (130) operatively coupled to the superposition unit (125). The data storage unit is configured to store a valid output of the superposition unit at an end of the regeneration phase. The data storage unit includes at least one of a latch and a flipflop. As used herein, the latch is a memory device that instantly changes the output in response to the input. The latch stores 1 or 0 at a time. The latch has two inputs Set and Reset. Similarly, the flip-flop is an electronic circuit that may store digital data and has two stable states. Flip-flops are a key component of digital electronic systems and are used to store data in a variety of systems, including computers, and communications. The flip-flop comprises an input terminal at which data to be stored is received and an output terminal at which data which are stored in the flip-flop are output. Typically, the latch or the flipflop includes a plurality of circuits. The plurality of circuits includes one of the P-channel metal oxide semiconductor (PMOS) inverters, N-channel metal oxide semiconductors (NMOS), inverters, and switches.
[0026] FIG. 2 is a circuit diagram representation of a system for increasing the speed of a serializer and deserializer is provided in accordance with an embodiment of the present disclosure. The slicer unit includes a pre-amplifier (205) and a regeneration phase working on different phases of the clock (clk). The outputs of the slicer unit may be stored using a latch or a flip-flop. Vdd is referred to as drain supply voltage and VSS is referred to as ground voltage. Typically, the pre-amplifier (pre-amp) accepts the input, by accepting the input the preamplifier samples and amplifies the input and the pre-amplifier output may be stored in the latch or the flipflop and through the reset switch, the slicer unit resets to supply voltage or ground.
[0027] The slicer unit includes a plurality of phases to scale up the speed of the serializer and de-serializer, wherein the plurality of phases includes a reset phase, a sampling phase, and a regeneration phase. The reset phase resets an output by providing connection between the output and a common mode voltage through a reset switch, wherein the reset phase resets a previous output when a clock generation unit generates a high clock signal. The sampling phase is to amplify an input using a preamplifier and apply an amplified output at a latch input. The regeneration phase regenerates the output from the common mode voltage, wherein the regeneration phase lowers time required in the regeneration of rail-rail voltage when gain of slicer unit is high. The system further includes a superposition unit operatively coupled to the slicer unit, wherein the superposition unit combines the reset phase and the sampling phase simultaneously in time synchronization and assign a dedicated time to the regeneration phase, thereby increasing the speed of the serializer and de-serializer. Further, the system also includes a data storage unit operatively coupled to the superposition unit, wherein the data storage unit is configured to store a valid output of the superposition module at an end of the regeneration phase, wherein the data storage unit comprises at least one of a latch and a flipflop.
[0028] FIG. 3a and FIG. 3b are timing diagrams of multiple phases of the slicer unit of FIG. 1 in accordance with an embodiment of the present disclosure. FIG. 3a illustrates a reset phase (305) wherein the outputs of stage 1 are shorted to ensure that there is no memory pertaining to the previous data. Further, in a sampling phase (310), the inputs of the reset phase (first stage) are charged to respective values from the input of the slicer unit. Furthermore, in a regenerating phase (315), the sampled inputs are regenerated using a cross coupled stage to rail-rail voltage levels.
[0029] FIG.3b illustrates the transparent phase (320) that propagates the outputs of the first stage in the second stage. Further, the outputs are valid in hold phase of the latch (325).
[0030] FIG. 4 illustrates a flow chart representing the steps involved in a method (400) for increasing the speed of a serializer and Deserializer in accordance with an embodiment of the present disclosure. The method (400) includes resetting an output by providing connection between the output and a common mode voltage through a reset switch, wherein the reset phase resets a previous output when a clock generation unit generates a high clock signal in step 410. Typically, a clock generator is an electronic oscillator that generates a clock signal for use in synchronizing the operation of a circuit. The signal may be as simple as a symmetrical square wave or as complex as possible.
[0031] The method (400) also includes amplifying an input using a preamplifier and applying an amplified output at a latch input in step 420. Typically, the preamplifier is an electronic amplifier that converts a weak electrical signal into an output signal. The output signal is strong enough to be noise-tolerant and strong enough for further processing.
[0032] Further, the method (400) includes regenerating the output from the common mode voltage, wherein the regeneration phase lowers time required in the regeneration of rail-rail voltage when gain of slicer unit is high in step 430. Typically, the rail-rail voltage is the range from a maximum voltage (Vdd) to a minimum voltage (Vss). The rail-rail voltage includes a differential of the common mode voltage and the output voltage.
[0033] Furthermore, the method (400) includes combining the reset phase and the sampling phase simultaneously in time synchronization in step 440.
[0034] Moreover, the method (400) includes assigning a dedicated time to the regeneration phase, thereby increasing the speed of the serializer and de-serializer in step 450.
[0035] In one embodiment, the regeneration phase is coupled to the input circuit. The regeneration circuit includes a plurality of regeneration field effect transistors for the desired performance.
[0036] Additionally, the method (400) includes storing a valid output of the superposition module at an end of the regeneration phase, wherein the data storage module includes at least one of a latch and a flipflop in step 460.
[0037] In one embodiment, the slicer unit samples the input signal, regenerates the sampled data, stores the data in an RS-latch or flipflop, and presets the regeneration nodes to high or low values in preparation for sampling the next input data.
[0038] Various embodiments of the system and method for increasing the speed of serializer and deserializer as described above provides better speed as the slicer unit combines the reset phase and the sampling phase and a dedicated time to the regeneration phase instead of combining the sampling phase and the regeneration phase, thus as the settling time is less and the speed of the slicer unit increases.
[0039] It will be understood by those skilled in the art that the foregoing general description and the following detailed description are exemplary and explanatory of the disclosure and are not intended to be restrictive thereof.
[0040] While specific language has been used to describe the disclosure, any limitations arising on account of the same are not intended. As would be apparent to a person skilled in the art, various working modifications may be made to the method in order to implement the inventive concept as taught herein.
[0041] The figures and the foregoing description give examples of embodiments. Those skilled in the art will appreciate that one or more of the described elements may well be combined into a single functional element. Alternatively, certain elements may be split into multiple functional elements. Elements from one embodiment may be added to another embodiment. For example, the order of processes described herein may be changed and are not limited to the manner described herein. Moreover, the actions of any flow diagram need not be implemented in the order shown; nor do all of the acts need to be necessarily performed. Also, those acts that are not dependent on other acts may be performed in parallel with the other acts. The scope of embodiments is by no means limited by these specific examples.
,CLAIMS:1. A system (100) for increasing speed of a serializer and de-serializer, comprising:
a slicer unit (105) comprising a plurality of phases to scale up the speed of the serializer and de-serializer, wherein the plurality of phases comprises:
a reset phase (110) to reset an output by providing connection between the output and a common mode voltage through a reset switch, wherein the reset phase resets a previous output when a clock generation unit generates a high clock signal;
a sampling phase (115) to amplify an input using a preamplifier and apply an amplified output at a latch input;
a regeneration phase (120) to regenerate the output from the common mode voltage, wherein the regeneration phase lowers time required in the regeneration of rail-rail voltage when gain of slicer unit is high;
a superposition unit (125) operatively coupled to the slicer unit, wherein the superposition unit:
combines the reset phase (110) and the sampling phase (115) simultaneously in time synchronization; and
assign a dedicated time to the regeneration phase (120), thereby increasing the speed of the serializer and de-serializer; and
a data storage unit (130) operatively coupled to the superposition unit (125), wherein the data storage unit is configured to store a valid output of the superposition unit at an end of the regeneration phase, wherein the data storage unit comprises at least one of a latch and a flipflop.
2. The system (100) as claimed in claim 1, wherein the common mode voltage is half of a voltage common to both sides of a differential input.
3. The system (100) as claimed in claim 1, wherein the sampling phase samples a current input when the clock generation unit generates a high clock signal.
4. The system (100) as claimed in claim 1, wherein the regeneration phase regenerates the current input when the clock generation unit generates a low clock signal.
5. The system (100) as claimed in claim 1, wherein the sampling phase and the regeneration phase are enabled to perform amplification of the input using a pre-amplifier circuit.
6. The system (100) as claimed in claim 1, wherein the rail-rail voltage comprises a differential of the common mode voltage and the output voltage.
7. The system (100) as claimed in claim 1, wherein the reset phase and the sampling phase utilizes a single clock signal for sampling and reset, wherein the output of superposition unit is valid for a unit interval time.
8. A method (400) for increasing speed of a serializer and de-serializer, comprising:
resetting, by a reset phase of a slicer unit, an output by providing connection between the output and a common mode voltage through a reset switch, wherein the reset phase resets a previous output when a clock generation unit generates a high clock signal; (410)
amplifying, by a sampling phase of the slicer unit, an input using a preamplifier and applying an amplified output at a latch input; (420)
regenerating, by a regeneration phase of the slicer unit, the output from the common mode voltage, wherein the regeneration phase lowers time required in the regeneration of rail-rail voltage when gain of slicer unit is high; (430)
combining, by a superposition unit, the reset phase and the sampling phase simultaneously in time synchronization; (440)
assigning, by the superposition unit, a dedicated time to the regeneration phase, thereby increasing the speed of the serializer and de-serializer; (450) and
storing, by a data storage unit, a valid output of the superposition module at an end of the regeneration phase, wherein the data storage module comprises at least one of a latch and a flipflop. (460)

Dated this 25th day of July 2023

Signature

Jinsu Abraham
Patent Agent (IN/PA-3267)
Agent for the Applicant