A system and a method for increasing the speed of serializer and deserializer is disclosed. The system includes a slicer unit (105) comprising a plurality of phases. The reset phase (110) resets an output when a clock generation unit generates a high clock signal. The sampling phase (115) amplifies an input when a c...

A system (10) to enable joint adaptation of a feed forward equalizer (20) and a decision feedback equalizer (30) is provided. The system includes the feed forward equalizer to provide first equalized signals. The system includes the decision feedback equalizer to provide second equalized signals. The system includes...

A dynamic clock divider for fractional N phase locked loop with spread spectrum control and a method is disclosed. The dynamic clock divider features a chain of 2/3 divider cells capable of providing an output of a variable clock frequency based on a dynamically changing division factor. The dynamic clock divider i...

A radio frequency (RF) limiter with integrated power detection control is disclosed. The RF limiter (100) includes a limiter circuit (110) shunt-connected to a primary RF transmission path coupled to a receiver unit (115) input terminal. The circuit comprises a power detection unit (120), coupled via a first capacit...