We Claim:
1. A transistor (10), in particular a wide bandgap semiconductor power transistor (40), comprising:
5 - an epitaxial layer (11) of a first conductivity type;
- at least one well region (13) of a second conductivity type formed in a selected area of the epitaxial layer
(11);
- at least one terminal region (14), in particular a 10 source region (29), of the first conductivity type
formed in or adjacent to the at least one well region (13);
- at least one terminal electrode (15), in particular a source electrode (21), formed at least partly on a
15 surface (12) of a first part of the at least one terminal region (14); and
- at least one resistive region (16) formed within the at least one terminal region (14), the at least one resistive region (16) comprising amphoteric impurities.
20
2. The transistor (10) of claim 1, wherein the at least one resistive region (16) comprises at least one of Manganese, Mn, and Vanadium, V, as amphoteric dopants.
25 3. The transistor (10) of claim 1 or 2, wherein a
concentration of amphoteric dopants in the at least one resistive region (16) lies in the range of 1011 to 1018 cm-3.
4. The transistor (10) of any one of claims 1 to 3, wherein 30 - a resistivity p of the terminal region (14) exceeds 10
Qcm, and preferably lies in the range of 20Qcm to 20 kQcm.
5. The transistor (10) of any one of claims 1 to 4, wherein a short-circuit withstand time, SCWT, of the transistor exceeds 3 us, and preferably is or exceeds 10 us-
5 6. The transistor (10) of any one of claims 1 to 5, wherein an implantation depth d of the at least one resistive region (16) lies in the range of 0 to 100%, preferably in the range of 10% to 100%, of the maximal thickness of the at least one terminal region (14).
: c
7. The transistor (10) of any one of claims 1 to 6, wherein the at least one terminal region (14) comprises at least three sub-regions, comprising at least one first sub-region (45) comprising amphoteric impurities and at least one second 15 sub-region (18, 19, 46) essentially free of amphoteric impurities, in particular one of:
one first sub-region (45) arranged horizontally between
and/or separating two adjacent second sub-regions (18, 19,
4 6); 20 - one first sub-region (45) arranged vertically between
and/or separating two adjacent second sub-regions (46);
a plurality of first sub-regions (45) partially or
completely embedded as resistive islands in a common
second sub-region (46); and 25 - a first plurality of first sub-regions (45) and a second
plurality of second sub-regions (46) forming at least one
of a horizontal grid, a vertical grid, a comb structure,
and a chess-board pattern.
30 8. The transistor (10) of any one of claims 1 to 7, wherein the transistor (10) is one of a metal-oxide-semiconductor field-effect transistor, MOSFET, a metal-insulator-semiconductor field-effect transistor, MISFET, a junction
field-effect transistor, JFET, and an insulated-gate bipolar transistor, IGBT, in one of a planar or a trench configuration.
5 9. The transistor (10) of any one of claims 1 to 8, further comprising at least one of the following:
a substrate (41) of the first conductivity region carrying
the epitaxial layer (11);
at least one highly doped well contact region (28) of the 10 second conductivity type, electrically connecting the at
least one well region (13) with the at least one terminal
electrode (15);
a second terminal region and a second electrode formed at
least partly on a surface of the second terminal region; 15 - at least one channel region (42) formed within the at
least one well region (13) in proximity to a gate
structure (23); and
a first insulation layer (25a) formed on a surface (12) of
the epitaxial layer (11) and a gate electrode (24) formed 20 on a surface of the first insulation layer (25a).
10. A power electronic switching device, comprising a plurality of transistor cells arranged on a common substrate and/or electrically connected in parallel, each transistor
25 cell comprising a transistor (10) according to one of claims
1 to 9.
11. A method for manufacturing a transistor (10), in particular a wide bandgap semiconductor power transistor
30 (40), comprising:
epitaxially growing (S2) a semiconductor layer of a first conductivity type;
forming (S3) at least one well region (13) of a second conductivity type formed in a selected area of the epitaxial layer (11);
forming (S5) at least one terminal region (14), in 5 particular a source region (29), of the first conductivity type in or adjacent to the at least one well region (13); and
implanting (S7) an amphoteric dopant in at least a part of the at least one terminal region (14).
: c
12. The method of claim 11, wherein the amphoteric dopant is implanted using an implantation energy in the range of 50 to 1000 keV.
15 13. The method of claim 11 or 12, wherein the amphoteric
dopant is implanted using an implantation dose in the range of 1010 cm"; to lO1^ cm-2.
14. The method of any one of claims 11 to 13, further 20 comprising:
annealing (S8) at least one resistive region (16) comprising the implanted amphoteric dopants at a first temperature Ti, wherein the first temperature Ti is selected based on a target resistivity p of the terminal 25 region (14) .
15. The method of claim 14, further comprising:
prior to annealing (S8) the at least one resistive region (16), activating (S6) the at least one terminal region 30 (14) at a second temperature T2 exceeding the first temperature Ti; and/or
after implanting (S7) the amphoteric dopant, forming (S9) at least one terminal electrode (15), in particular a source electrode (21), at least partly on a surface (12; of at least part of the at least one terminal region 16]