A startup circuit for use with a SCVR circuit includes a comparator operative to generate a first control signal as a function of a comparison between an output voltage generated by the SCVR circuit and a reference voltage, the first control signal being used to disable the startup circuit. The startup circuit furth...

Single-ended read circuits for SRAM devices are disclosed for high performance sub-micron designs. One embodiment is an SRAM device that includes a memory cell array and a bit line traversing the memory cell array for reading data from memory cells of the memory cell array. A read circuit coupled to the bit line ...

A data storage system with a cache organizes cache windows into lists based on the number of cache lines accessed during input/output operations. The lists are maintained in temporal queues with cache windows transferred from prior temporal queues to a current temporal queue. Cache windows are removed from the o...

ABSTRACT OF THE DISCLOSURE Disclosed is a system and method for providing redundancy to RAID 0 virtual disks by utilizing any right sized physical disk in the SAS domain. The system and method restore redundancy in a degraded redundant virtual disk. This may be done even in the absence of a configured hot spare. ...

An integrated circuit having a programmable clock spreader configured to generate a plurality of controllably skewed clock signals, each applied to a corresponding region within the integrated circuit with circuitry configured to be triggered off the applied clock signal. The programmable clock spreader is designed ...

A cache controller implemented in O/S kernel, driver and application levels within a guest virtual machine dynamically allocates a cache store to virtual machines for improved responsiveness to changing demands of virtual machines. A single cache device or a group of cache devices are provisioned as multiple logi...

A cache controller having a cache store and associated with a storage system maintains information stored in the cache store across a reboot of the cache controller The cache controller communicates with a host computer system and a data storage system. The cache controller partitions the cache memory to include ...

Methods and structure for preemptively terminating Serial Attached Small Computer System Interface connections are provided. One exemplary embodiment includes an expander comprising multiple physical links, switching circuitry able to establish connections between end devices coupled with the expander through the ph...

Abstract Methods and structure are provided for tracking changes to a logical volume over time. One exemplary embodiment is a backup system for a Redundant Array of Independent Disks (RAID) storage system. The backup system includes a backup storage device that includes Copy-On-Write snapshots of a logical volume o...

Systems and methods to safely and efficiently handle dirty data flush are disclosed. More specifically, when a cache controller determines that one(or more) storage device of a cache device is running out of space, that storage device is given priority to be flushed prior to the other storage devices that are not in...

ABSTRACT In one embodiment, an integrated circuit comprising a current-sensing circuit having a power transistor and an amplifier.  The current-sensing circuit is coupled to (i) sense a current supplied to a load by a voltage source through an inductor and (ii) generate an inductor-current signal based on the sense...

Methods and structure are provided for rebuilding cache data from a failed cache device based on tracking data for the failed cache device. The system includes a memory and a cache manager. The memory stores tracking data that correlates entries at a cache with logical block addresses of a logical volume. The cache ...

The disclosure is directed to a system and method for managing a plurality of storage devices. In an embodiment, at least one enclosure is configured to contain or support a plurality of storage devices accessible by a plurality of initiators. The enclosure further includes or is coupled to a power management contro...

The disclosure is directed to a system and method for managing READ cache memory of at least one node of a multiple-node storage cluster. According to various embodiments, a cache data and a cache metadata are stored for data transfers between a respective node (hereinafter "first node") and regions of a storage...

The disclosure is directed to a system and method for managing cache memory of at least one node of a multiple-node storage cluster. According to various embodiments, a first cache data and a first cache metadata are stored for data transfers between a respective node and regions of a storage cluster receiving at l...

Aspects of the disclosure pertain to a system and method for providing improved system performance by moving pinned data to ONFI module(s) while the system is in a running state. Further, when a virtual array of the system is offline, the system allows for scheduling and performance of background operations on vi...

The disclosure is directed to a system and method of cache management for a data storage system. According to various embodiments, the cache management system includes a hinting driver and a priority controller. The hinting driver generates pointers based upon data packets intercepted from data transfer requests...

The disclosure is directed to a system and method of cache management for a data storage system. According to various embodiments, the cache management system includes a hinting driver, a priority controller, and a data scrubber. The hinting driver generates pointers based upon data packets intercepted from data...

A memory cell includes a storage element including a pair of cross-coupled inverters, and first switching circuitry for selectively connecting at least one internal storage node of the storage element with a corresponding bit line as a function of a first control signal. Write assist circuitry is connected between a...

A sense amplifier includes a latch, first and second switching circuitry, and control circuitry. The first switching circuitry selectively couples a voltage supply node and/or a voltage return node of the latch to a voltage supply and/or a voltage return of the sense amplifier, respectively, as a function of a first...

Methods and structure for utilizing a Solid State Drive (SSD) to enhance boot time for a computer. The computer includes an SSD that stores a boot cache for an Operating System of a computer, a Hard Disk Drive that stores the Operating System, and a processor. The processor is able to load an interrupt handler that ...

Systems and methods presented herein provide a storage system that adaptively powers-down one or more disk drives based on the predicted idle time of each disk drive. One embodiment includes a storage controller that includes a processor operable to track idle durations of the disk drive. When an idle duration en...

Abstract A memory device includes a memory array having a plurality of memory cells each having first and second power supply nodes, first and second virtual power supply nodes, a latch circuit, and a write assist circuit. The latch circuit includes a first and second inverters in a cross-coupled inverter configura...

A storage system includes a plurality hard disk drives and a plurality of solid-state drives and a storage controller operable to manage the hard disk drives and solid-state drives as a plurality of logical volumes, and categorize input/output requests to the logical volumes into types based on sizes of the input/ou...

A modified or host driver operable on a host computer communicates with a host interface of a PCIe adapter. A controller memory space is managed by the kernel space of the host operating system. The modified driver entirely avoids the overhead associated with making a copy from the application or user space to a sep...

In certain embodiments, a method and apparatus for adjusting the timing of a sense-amplifier read operation in an SRAM integrated memory circuit to overcome process-and-temperature variations are disclosed. A charge-injection pull-up transistor is provided to adjust the rate at which a signal line (e.g., a tracking ...

Systems and methods maintain cache coherency between storage controllers utilizing bitmap data. In one embodiment, a storage controller processes an I/O request for a logical volume from a host, and generates one or more cache entries in a cache memory that is based on the request. The storage controller identifies ...

Methods and structure for intelligent cache window management are provided. The system comprises a memory and a cache manager. The memory stores entries of cache data for a logical volume. The cache manager is able to track usage of the logical volume by a host, and to identify logical block addresses of the logical...

Aspects of the disclosure pertain to a system and method for providing prediction based, fast routing of IP flows. A hash table-based mechanism is implemented by the system such that classification information obtained and/or utilized for a.first packet of an IP flow is applied to subsequent packets of the IP flow, ...

A data storage system controller designates critical drives for staggered spin up and other, non-critical drives for spin up only when the controller notifies the appropriate expander. Each expander in the data storage system maintains configuration information for each PHY of the expander and reports completion ...

Systems and methods herein provide for managing devices through a Serial Attached Small Computer System Interface (SAS) expander. The SAS expander includes a processor adapted to detect deadlock conditions in a SAS environment. In one embodiment, the SAS expander is operable to detect an Open Address Frame associate...

A method of controlling a switched capacitor voltage regulator includes modifying a topology factor associated with the switched capacitor voltage regulator in response to a change in output voltage associated with the switched capacitor voltage regulator, thereby maintaining an average output voltage associated wit...

Systems and methods herein provide for managing connection requests through a Serial Attached Small Computer System Interface (SAS) expander. In one embodiment, the expander receives a low priority open address frame (OAF) that includes a source address and a destination address. The expander also receives a high pr...

A method of controlling a ping-pong buffer includes selectively providing one of a ping gated write clock signal and a ping gated read clock signal to a single-port ping buffer, and selectively providing a pong gated write clock signal or a pong gated read clock signal to a single-port pong buffer. A controller of a...

[0037] The present disclosure is directed to a method for managing a cache based on a charge of a power source. The method includes the step of determining a charge of the power source at a first time instance. The method also includes the step of designating for write back cache an amount of data in the cache w...

The disclosure is directed to preserving data consistency in a multiple- node data storage system. According to various embodiments, a write log is maintained including log entries for data transfer requests being served by a respective node of the multiple-node data storage system. Rather than maintaining a ful...

Methods and structure are provided for creating and managing unused storage capacity in Redundant Array of Independent Disks (RAID) systems. One embodiment is a RAID controller that includes a controller operable to create and manage a logical volume out of storage space that would otherwise not be used by a RAID sy...

Nodes in a data storage system having redundant write caches identify when one node fails. A remaining active node stops caching new write operations, and begins flushing cached dirty data. Metadata pertaining to each piece of data flushed from the cache is recorded. Metadata pertaining to new write operations a...