Technical field
[0001]The present invention is an integrated circuit system, activation control method for an integrated circuit system and a startup control program.
BACKGROUND
[0002]FPGA increase in capacity of (Field Programmable Gate Array), etc. The programmable device of, also increasing the data size of the configuration data. Therefore, there recently, becoming impossible to ignore the bit error rate of the configuration data is a bit stream data. Furthermore, progress in the miniaturization of device process, power consumption, performance, while has come to benefit of cost, it is becoming susceptible to soft errors due to cosmic rays.
[0003]
　Therefore, in spite of not a hardware failure, a phenomenon in which the programmer device does not start properly began to occur. As a result, the phenomenon must be carried out the hardware repair every time occurs, is growing that extra man-hours and costs may occur. Also, if you do not start up normally, programmable devices resulting in a stack. As a result, the system will be down, would be a nuisance to the user during operation. Therefore, from the viewpoint of fail-safe, solution of these problems has been desired.
[0004]
　In volatile programmable device such as FPGA, technology that focuses on the challenges of rewriting the circuit information has been proposed (e.g., refer to Patent Document 1, Patent Document 2). In particular, in the technique described in Patent Document 1 is aimed to solve the above problems. In the technique described in Patent Document 1, processing of the logic circuit reads the circuit information on the FPGA (hereinafter, also referred to as configuration processing) when performing, if it fails the configuration process from various factors, the FPGA It provides a redundant function to prevent the stack.
[0005]
　The technique described in Patent Document 1, for example, a configuration including a FPGA as shown in FIG. 10, a system which performs processing as shown in FIGS. 11 and 12. 10, interface 201 is a Config I / F. Interface 202 is originali / F. Further, reference numeral 203 is a signal line. In the system, FPGA102 is, when it is determined that the soft error on the read circuit information from the flash memory 100 is generated via the PLD101 (FIG. 11: step S3, True), and notifies the configuration NG in PLD101 ( Figure 11: step S7). The cause of soft error, as described above, abnormality or such a bit stream included in the circuit information (0 and 1 of the information binary) bits are inverted, abnormality affected by cosmic rays is there.
[0006]
　PLD101 receives a notification of configuration NG from FPGA 102 (FIG. 12: step S22, True), refers to the activation surface information of the flash memory 100, a flash other circuit information indicated by the inverted value of the value of the activation surface information read from the memory 100 (FIG. 12: step S23). PLD101 transmits the other circuit information read in FPGA 102 (FIG. 12: step S25). Thus, for example, as circuit information, in a case where two circuits information circuit information A and the circuit information B exists, if it fails to configuration processing in the circuit information A, the configuration processing in the circuit information B it is possible to perform. If successful in the circuit information B fails to configuration processing by the circuit information A, it is detected as a soft error. On the other hand, if it fails to configure treatment with both circuit information A and the circuit information B, it is detected as a hardware failure.
CITATION
Patent Document
[0007]
Patent Document 1: Patent No. 6032360 Patent Publication
Patent Document 2: JP 2009-182438 JP
Summary of the Invention
Problems that the Invention is to Solve
[0008]
　In the technique described in Patent Document 1, FPGA 102 is, information that one at or subjected to configuration processing circuit information A and the circuit information B, and information on whether FPGA 102 has succeeded or failed in the configuration process, the determination in PLD101 doing. Therefore, in the technique described in Patent Document 1, in order to perform the configuration process of the FPGA 102, the control device that PLD101 has become a separate desired configuration.
[0009]
　However, the need for such separate control devices, in actual equipment development, component cost of the control device occurs. For this reason, there is a problem that the apparatus cost ratio is poor.
[0010]
　Further, it is necessary to secure a mounting area for the control device on the mounting board. Therefore, in the board design, new work, such as to consider the arrangement of the control device ends up occurring, and there is a problem that inhibits miniaturization.
[0011]
　The present invention is an integrated circuit system that solves the above problems, the start control method of the integrated circuit system, and to provide a start control program.
Means for Solving the Problems
[0012]
　In order to solve the above problems, one aspect of the present invention includes a plurality of circuit information, activation control logic start control circuit used in the construction of selecting said circuit information not fail to configure the logic circuit a storage element for storing in advance information, upon activation, or when the configuration of the logic circuit according to any one of the circuit information of said plurality of circuit information has failed, the startup control circuit information from said memory element read by a logic circuit for the startup control, to select the circuit information not fail the activation control logic circuit formed in the configuration of the logic circuit, said circuit being selected in the start-up control logic circuit an integrated circuit that performs the configuration of the logic circuit in accordance with the circuit information by reading information from the storage element is an integrated circuit system comprising: a.
[0013]
　Another embodiment of the present invention, an integrated circuit system comprising a storage device for storing a plurality of circuit information, and an integrated circuit which reads the circuit information from the storage device to configure the logic circuit in accordance with the circuit information a start control method in the stores the start control circuit information used in configuration of the activation control logic circuit for selecting the circuit information not fail to configure logic circuits in the memory device, upon actuation or, when the structure of the logic circuit according to any one of the circuit information of said plurality of circuit information fails, on the basis of the start control circuit information of the memory element, the activation control logic circuit to the integrated circuit configure, the circuit information constituting the said activation control logic circuit selects the circuit information not fail configuration of the logic circuit, the activation control logic circuit selects Based on a start-up control method for an integrated circuit system and performs a configuration of the logic circuit to the integrated circuit.
[0014]
　Another embodiment of the present invention is connected to a storage device for storing a plurality of circuit information, the integrated circuit constituting the logic circuit in accordance with the circuit information, upon activation, or any of the plurality of circuit information when the configuration of the logic circuit by Kano circuit information has failed, by constituting a start control logic circuit, to select the circuit information not fail to configure the logic circuit to the activation control logic circuit, said start control It said circuit information use logic circuit selected to read from the storage element, the circuit wherein the activation control program is a start control circuit information for executing that causes the configuration of a logic circuit according to the information it is.
The invention's effect
[0015]
　According to the present invention, the programmable integrated circuit, if it fails to start, without using another control device, it is possible to start with other circuit information not fail.
BRIEF DESCRIPTION OF THE DRAWINGS
[0016]
And [FIG. 1] integrated circuit system 1 according to one embodiment, is a block diagram showing a connection relationship between apparatus connected to the integrated circuit system 1.
Is a diagram showing an example of arrangement of data in a flash memory according to [2] the same embodiment.
[3] the flash memory according to the embodiment is a diagram showing an arrangement example of data when it is 512Mbit.
4 is a flowchart illustrating a configuration process by FPGA according to the embodiment.
5 is a flowchart showing a start control process according to configured activation control logic circuit in the FPGA of the same embodiment.
A [6] a flowchart showing the overall flow of processing will start first configuration data and the second configuration data in the same embodiment (Part 1).
Is [7] a flowchart showing the overall flow of processing will start first configuration data and the second configuration data in the same embodiment (Part 2).
8 is a flowchart illustrating a configuration process of the start control for the configuration data in the embodiment.
9 is a diagram showing a pattern of activation of the first configuration data and the second configuration data in the embodiment.
Is a block diagram showing the configuration of a system for switching the configuration data of the FPGA by using FIG. 10] PLD.
11 is a flowchart showing a flow of processing by the system of switching the configuration data of the FPGA by using a PLD (Part 1).
Is [12] a flowchart showing the flow of processing by the system of switching the configuration data of the FPGA by using a PLD (Part 2).
13 is a diagram showing a minimum configuration of an integrated circuit system.
DESCRIPTION OF THE INVENTION
[0017]
　It will be described below with reference to the accompanying drawings, embodiments of the present invention. 1, CPU to connect to the integrated circuit system 1, and the integrated circuit system 1 according to an embodiment (Central Processing Unit) 3 and JTAG (Joint Test Action Group) Connector5, and PC connected to CPU3 and JTAG Connector5 (Personal Computer ) is a block diagram showing a fourth configuration. Integrated circuit system 1 includes a flash memory 10 and FPGA 20.
[0018]
　Flash memory 10 is connected by a connecting line 2 with FPGA 20. The connection line 2, for example, QSPI (Quad Serial Peripheral Interface), such as are applied those specifications of the general-purpose serial interface for connecting the FPGA20 and flash memory 10.
[0019]
　Flash memory 10, data erasure, can be written, a nonvolatile semiconductor memory capable of maintaining the information supply of power is stored even lost. Figure 2 is a diagram showing an example of arrangement of data in the flash memory. Flash memory 10, are arranged data as shown in FIG. Flash memory 10, the second configuration data 12, the first configuration data 11, start surface information 13, boot history information 14, and stores a start control for the configuration data 15.
[0020]
　The first configuration data 11, the second configuration data 12, start control configuration data 15 is loaded from the FPGA 20, a circuit information included in the logic circuit by which is activated through the configuration process. For example, the first configuration data 11 and the second configuration data 12 is a circuit information included in the logic circuit to be actually operated in accordance with some applications the user of the FPGA 20. Activation control configuration data 15 is a circuit information included in the logic circuit for starting control.
[0021]
　Start surface information 13 is information indicating whether or not to start the first configuration data 11, or activates the second configuration data 12. The information is written into the start surface information 13 in the flash memory 10 by the CPU 3. Start the history information 14, information indicating the circuit information configuration processing is performed by the FPGA 20 immediately before is written by FPGA 20. That is, the boot history information 14, or the first configuration data 11, information that indicates whether the circuit information of the second configuration data 12 are written. The size of the data areas 11-15 of the flash memory 10, when the flash memory 10 has N blocks, starting surface information 13 and the boot history information 14 are each one block. Further, activation control configuration data 15 is k blocks, the first configuration data 11 and the second configuration data 12 are each (N-2-k) / 2 blocks.
[0022]
　Returning to Figure 1, the CPU 3, when updating the logic circuit FPGA20 with the version upgrade, and software control unit for switching the circuit information to load the FPGA20 implemented. CPU3 receives an instruction signal from the PC 4, and writes the information indicating the circuit information to start the activation surface information 13 in the flash memory 10 through the connection line 2 via the FPGA 20. Thus, the switching of the circuit information are performed.
[0023]
　JTAG Connector5 is connected to the JTAG circuit 29 of FPGA 20, upon receiving an instruction signal from the PC 4, to test the FPGA 20 and debugging and the like. PC4 has a CPU3, connected to the JTAG Connector5, in response to the operation of the user, and outputs an instruction signal to CPU3 and JTAG Connector5.
[0024]
　FPGA20 by reading the circuit information, a programmable integrated circuit constituting the logic circuit in response to the read circuit information. FPGA20 the first status register 21, the second status register 22, the configuration address register 23, an error counter register 24, the control unit 25, the configuration memory 26, the programmable elements 27, I / O circuit 28, and a JTAG circuit 29 provided. In FPGA 20, the first status register 21, when succeeding in the configuration process, a value indicating "NORMAL", "0x0" is written by the control unit 25. On the other hand, if the configuration process fails, the first status register 21, a value indicating "ERROR", "0x1" is written by the control unit 25. Further, in the first status register 21, when cleared by the control unit 25, a value indicating "NORMAL", "0x0" is written.
[0025]
　The second status register 22, the activation control logic circuit 35, when starting the process of the FPGA reconfiguration instruction on itself, is asserted by the start control logic circuit 35. Activation control logic circuit 35 is configured by the startup control for the configuration data 15 is started in the FPGA 20. Assertion is, for example, is that the value of "0x1" is written.
[0026]
　The configuration address register 23, the start address circuit information in the flash memory 10 is stored, is written by the control unit 25 or the activation control logic circuit 35. Configuration processing of FPGA20 is initiated by reading the circuit information from the address value of the flash memory 10 stored in the configuration address register 23. The error counter register 24, the number of times the configuration processing of the start control for the configuration data 15 has failed is written by the control unit 25.
[0027]
　Control unit 25, the above each register included in the FPGA 20, namely the first status register 21, the second status register 22, the configuration address register 23, an error counter register 24 FPGA 20 is initialized when it is activated. The control unit 25, or writes information or values ​​for each register, or performing the read. The control unit 25 reads the information or values ​​stored in each register, the determination process is performed on the basis of the read information and values. The control unit 25 reads the circuit information from the flash memory 10 the address value stored in the configuration address register 23 as start address. Then, the control unit 25 writes the read circuit information in the configuration memory 26. The control unit 25 starts the configuration process for the circuit information written in the configuration memory 26. The control unit 25 includes, for example, in the FPGA 20, a logic circuit which is previously constructed as hardware to perform these processes.
[0028]
　The configuration memory 26, the circuit information control unit 25 is read from the flash memory 10 is written by the control unit 25. Programmable element 27 is an element serving as a logic circuit in accordance with the circuit information stored in the configuration memory 26. For example, the programmable elements 27, in the first configuration data 11, the first logic circuit 31, and when the second configuration data 12, the second logic circuit 32. Also, programmable elements 27 in the case of activation control configuration data 15, the activation control logic circuit 35.
[0029]
　I / O circuit 28 transmits and receives signals to and from an external circuit connected to the FPGA 20. JTAG circuit 29 is connected to the JTAG Connector5. JTAG circuit 29 performs upon receiving the instruction signal from the PC4 via JTAG Connector5, testing and debugging of FPGA 20, for example, a test or the like of a logic circuit built programmable element 27 according to the circuit information.
[0030]
　3, the flash memory 10, for example, illustrates an example of the arrangement of data when a flash memory of 512Mbit. Activation control configuration data 15 is written into the region of the address value "0x0000000 ~ 0x0EDFFFF". Boot history information 14 is written into the region of the address value "0x0EE0000". For example, if the configuration processing is performed in the first configuration data 11, the value "0x0" as the boot history information 14 is written. On the other hand, if the configuration processing is performed in the second configuration data 12, the value "0x1" as the boot history information 14 is written.
[0031]
　Start surface information 13 is written into the region of the address value "0x0EF0000". For example, if the first configuration data 11 is designated as the activation surface information 13 value "0x0" is written. On the other hand, when the second configuration data 12 is designated as the activation surface information 13 value "0x1" is written. The first configuration data 11 is written into the region of the address value "0x0F00000 ~ 0x277FFFF". The second configuration data 12 is written into the region of the address value "0x2780000 ~ 0x3FFFFFF". For example, to start the first configuration data 11 in FPGA 20, the start address value "0x0F00000", written in the configuration address register 23. Configuration address register 23, when cleared, the value "0x0000000" is stored. Therefore, when FPGA20 is activated in a state in which the configuration address register 23 is cleared, the start control for the configuration data 15 is selected.
[0032]
(Configuration processing)
　with reference to FIGS. 4 and 5, it describes the processing of the integrated circuit system 1. Figure 4 is a diagram showing the configuration process performed by the control unit 25. Through the configuration process of Figure 4, the programmable element 27 of FPGA20 is when the activating control logic circuit 35, by the activation control logic circuit 35, start control process shown in FIG. 5 is executed.
[0033]
　Figure 4 is a flowchart illustrating a configuration process in FPGA 20. The first time FPGA20 is activated, becomes a process of the power-on reset, initialization of FPGA20 is performed. At this time, each of the registers, that is, the first status register 21, the second status register 22, the configuration address register 23 and the error counter register 24, it is also initialized.
[0034]
　Control unit 25, based on the address value stored in the configuration address register 23, reads circuit information from the flash memory 10. Control unit 25 reads the write circuit information in the configuration memory 26, and starts the configuration process (FPGA configuration processing) (step Sa1). Control unit 25 determines whether the configuration processing is performed normally (step Sa2).
[0035]
　The control unit 25 determines, for example, when detecting the occurrence of soft errors in the configuration process, the configuration processing was not successful. If configuration processing is judged not normally performed (step Sa2, No), the control unit 25 writes the value "0x1" indicating "ERROR" in the first status register 21, clears the configuration address register 23 (step Sa3).
[0036]
　Control unit 25 determines the second status register 22, whether or not asserted, i.e. whether the second status register 22 value "0x1" is stored (step Sa4). Control unit 25, the second status register 22, when it is determined that the asserted (step Sa4, Yes), clears the second status register 22, i.e., writes "0x0" to the second status register. Control unit 25 returns to step Sa1 (step Sa5).
[0037]
　On the other hand, the control unit 25, the second status register 22, when it is determined not to be asserted (step Sa4, No), it refers to the value of n which is stored in advance in the internal storage area. Control unit 25, a value indicating the number of times the configuration process fails stored in the error counter register 24 is equal to or smaller than n (step Sa6). Control unit 25, if the value stored in the error counter register 24 is determined to be less than n (step Sa6, Yes), 1 is added to the value stored in the error counter register 24, an error counter register 24 writes. Control unit 25 returns to step Sa1 (step Sa7).
[0038]
　On the other hand, the control unit 25, if the value stored in the error counter register 24 is determined not to be less than n (step Sa6, No), hardware failure, and ends by stopping the configuration processing ( step Sa8).
[0039]
　Returning to step Sa2, the control unit 25, if the configuration processing is determined to have been normally performed (step Sa2, Yes), clears the error counter register 24 (step Sa11). That is, the control unit 25 causes the writing and storing the value "0" in the error counter register 24. Control unit 25 clears the configuration address register 23 (step Sa12). That is, the control unit 25 causes the writing and storing the value "0x0000000" on the configuration address register 23. Control unit 25 determines the second status register 22, whether or not asserted, i.e. whether the "0x1" is stored in the second status register 22 (step Sa13).
[0040]
　Control unit 25, the second status register 22, when it is determined that the asserted (step Sa13, Yes), clears the first status register 21 and the second status register 22 (step Sa14). That is, the control unit 25 causes the writing and storing value "0x0" indicating "NORMAL" in the first status register 21. The control unit 25 writes the value "0x0" in the second status register. Control unit 25, the first configuration data 11 programmable elements 27 to start or second configuration data 12, the configuration process is successful, configured as a first logic circuit 31 or the second logic circuit 32 and it ends the process (step Sa15). Or be configured as a first logic circuit 31, is either constructed as a second logic circuit 32, it is selected by the processing of the start control for the configuration data starts in step Sa16 (FPGA boot).
[0041]
　On the other hand, the control unit 25, if the second status register 22 is determined not to be asserted (step Sa13, No), the configuration process starts the start control configuration data 15 was successful (step Sa16 ). By activating a starting control for the configuration data 15, the startup control process by the configured start control logic circuit 35 (FIG. 5) is started (step Sa17).
[0042]
(Startup control processing)
　Next, referring to FIG. 5, the logic circuit 35 for start control constituted by activating a starting control for the configuration data 15 for startup control process is described for performing. Figure 5 is a flowchart showing a start control processing by the logic circuit 35 for startup control constructed in FPGA 20.
　Activation control logic circuit 35 reads the values stored from the flash memory 10 to the start surface information 13 (step Sb1). Activation control logic circuit 35 reads the values stored from the flash memory 10 to the boot history information 14 (step Sb2). Activation control logic circuit 35 reads the values stored in the first status register 21 (step Sb3). Activation control logic circuit 35 determines whether the value stored in the first status register 21 is a either a "NORMAL", "ERROR" (step Sb4).
[0043]
　Activation control logic circuit 35, the value stored in the first status register 21, "NORMAL" when it is determined that (step Sb4, NORMAL), the circuit information indicated by the value read from the activated surface information 13 It writes the start address to the configuration address register 23 (step Sb5). That is, the start control logic circuit 35 writes first configuration data 11, or the start address of the second configuration data 12 in the configuration address register 23.
[0044]
　Activation control logic circuit 35 initializes the boot history information 14 in the flash memory 10 (step Sb6), and writes the value stored in the boot surface information 13 on the boot history information 14 (step Sb7). Thus, the value stored in the boot history information 14, the value stored in the boot surface information 13 is the same value. Activation control logic circuit 35 asserts a second status register 22. That is, the start control logic circuit 35 writes the value "0x1" in the second status register 22. Further, activation control logic circuit 35, the processing of the FPGA reconfiguration instruction, i.e. to re-initialize the FPGA 20 (step Sb8). Thus, in the flowchart of FIG. 4, the control unit 25 starts the processing from step Sa1.
[0045]
　On the other hand, activation control logic circuit 35, the value that the value stored in the first status register 21, when it is determined that the "ERROR" (step Sb4, ERROR), read from the boot surface information 13, starting a value read from the history information 14 is equal to or the same (step Sb10). Activation control logic circuit 35, the value read from the activated surface information 13, if the value read from the execution history information 14 is determined not to be identical (step Sb10, No), the activation control process as hardware failure completed (step Sb11). That is, the start control logic circuit 35 stops the configuration process.
[0046]
　On the other hand, activation control logic circuit 35, the value read from the activated surface information 13, when determining the value read from the execution history information 14 are the same (step Sb10, Yes), activated surface of the flash memory 10 reading the value stored in the information 13. Activation control logic circuit 35 writes the start address of the circuit information inverted value indicates a value read from the activated surface information 13 in the configuration address register 23 (step Sb12). For example, if the starting surface information 13 value "0x0" is written, the start control logic circuit 35, the start address of the second configuration data 12 indicated by the value "0x1" is the inverted value, configuration write to the configuration address register 23. In contrast, for example, if the starting surface information 13 value "0x1" is written, the start control logic circuit 35, the first configuration data 11 indicated by the value "0x0" is the inverted value the start address, write to the configuration address register 23.
[0047]
　Activation control logic circuit 35 initializes the boot history information 14 in the flash memory 10 (step Sb13), and writes the inverted value of the value stored in the boot surface information 13 on the boot history information 14 (step Sb14). Thus, the value stored in the boot history information 14, the value stored in the boot surface information 13 with different values. Activation control logic circuit 35, the process proceeds to step Sb8, asserting a second status register 22. That is, the start control logic circuit 35 writes "0x1" to the second status register 22. Further, activation control logic circuit 35, the processing of the FPGA reconfiguration instruction, i.e. to re-initialize the FPGA 20 (step Sb8). Thus, in the flowchart of FIG. 4, the control unit 25 starts the processing from step Sa1.
[0048]
(Specific example of the process)
　by the start control processing performed by the configuration process and the start control logic circuit 35 shown by FIGS. 4 and 5, a first configuration data 11 second configuration data 12 is started Referring to FIGS. 6-8, the following explains that stream. 6 and 7 are flowcharts showing the overall flow of processing will start with the first configuration data and a second configuration data. Figure 8 is a flowchart illustrating a configuration process of the start control for the configuration data.
　As a prerequisite, the activation surface information 13 in the flash memory 10, a value indicating the first configuration data 11 "0x0" is assumed to have been written in advance by the CPU 3.
[0049]
　When FPGA20 is started, as shown in step Sc1 of Figure 6, the configuration process of the start control for the configuration data of FIG. 8 is performed. The configuration processing of the start control for the configuration data shown in FIG. 8 will be described with reference to the processing of the flowchart of FIG.
　When FPGA20 is started, initialization of FPGA20 is performed. At this time, each of the registers, that is, the first status register 21, the second status register 22, the configuration address register 23 and the error counter register 24, it is also initialized. By being initialized, the first status register 21 is stored the value "0x0" indicating "NORMAL", the second status register 22 has a value "0x0" are stored. By being initialized, the configuration address register 23, the stored address value "0x0000000", an error counter register 24 the value "0" is stored.
[0050]
　Control unit 25, by referring to the configuration address register 23, reads circuit information from a region of the flash memory 10 to the start address and the value "0x0000000". As shown in FIG. 3, in the area, the activation control configuration data 15 are stored. Control unit 25 writes the configuration memory 26 reads out the start control configuration data 15 from the flash memory 10. Control unit 25 starts the configuration process of activation control configuration data 15 (FIG. 4: step Sa1, Figure 6: step Sc1, Figure 8: step Sd1).
[0051]
　Control unit 25 determines the configuration processing of the start control for the configuration data 15, for example, whether soft error has occurred. Thus, the control unit 25 determines whether the configuration processing is performed normally (Figure 4: step Sa2, Figure 8: step Sd2).
[0052]
　Control unit 25, if the configuration processing of the start control for the configuration data 15 is determined to have been normally performed (Figure 4: step Sa2, Yes, Figure 8: step Sd2, Mu error), clears the error counter register 24 and (4: step Sa11), clears the configuration address register 23 (FIG. 4: step Sa12). Control unit 25, the second status register 22, determines whether or not asserted (Figure 4: Step Sa13). Here, the second status register 22, because they remain in the initialized state, not asserting. Therefore, the control unit 25 determines that the second status register 22 is not asserted (Figure 4: Step Sa13, No). Control unit 25 starts the start control configuration data 15 (FIG. 4: step Sa16, Figure 8: Step Sd3).
[0053]
　On the other hand, the control unit 25, if the configuration processing of the start control for the configuration data 15 is determined to have not been performed normally (Figure 4: step Sa2, No, 8: step Sd2, the error Yes), the first status write the value "0x1" indicating "ERROR" in the register 21. The control unit 25 clears the configuration address register 23. Here, the configuration address register 23 stores the value "0x0000000". Therefore, even if cleared, it will store the identical value "0x0000000" (Figure 4: Step Sa3).
[0054]
　Control unit 25, the second status register 22, determines whether or not asserted (Figure 4: Step Sa4). Here, the second status register 22, because they remain in the initialized state, not asserting. Therefore, the control unit 25 determines that the second status register 22 is not asserted (Figure 4: Step Sa4, No). Control unit 25, the value stored in the error counter register 24 is equal to or less than n be predetermined (FIG. 4: step Sa6). That is, the determination in step Sa6 is determined whether the failed configuration process start control for the configuration data 15 n consecutive times (FIG. 8: step Sd4).
[0055]
　Control unit 25, the value stored in the error counter register 24, when it is judged less than n be predetermined (FIG. 4: step Sa6, Yes, Figure 8: Step Sd4, No), the following process do. That is, the control unit 25 adds 1 to the value stored in the error counter register 24, thereby writing and storing added value in the error counter register 24 (step Sa7). Thereafter, the control unit 25 processes the in Figure 4 returns to step Sa1, 8 returns to step Sd1. Then, the control unit 25 again performs the configuration process of activation control configuration data 15.
[0056]
　On the other hand, the control unit 25, the value stored in the error counter register 24, when it is determined that it is not less than n which is predetermined, i.e., n times in succession failed configuration processing of the start control for the configuration data 15 If you (Figure 4: step Sa6, No, 8: step Sd4, Yes), the control unit 25 determines that a hardware failure has occurred. Control unit 25 stops the configuration process (FIG. 4: step Sa8, Figure 8: step Sd5).
[0057]
　Step Sa16 of Fig. 4, in step Sd3 in FIG. 8, the control unit 25, when you start the activation control configuration data 15, the logic circuit 35 is configured for activation control. Then, the activation control logic circuit 35, start control process shown in FIG. 5 is started (Fig. 4: Step Sa17, Figure 6: step Sc2). With reference to the flowchart of FIG. 5 illustrating the startup control process.
[0058]
　Activation control logic circuit 35 refers to the address value of the flash memory 10 '0x0EF0000 ", reads the value stored in the boot surface information 13 (FIG. 5: step Sb1). Activation control logic circuit 35 refers to the address value of the flash memory 10 '0x0EE0000 ", reads the value stored in the boot history information 14 (FIG. 5: step Sb2). Activation control logic circuit 35 reads the values ​​stored in the first status register 21 (FIG. 5: step Sb3). Activation control logic circuit 35 determines the value stored in the first status register 21, the whether it is "NORMAL", "ERROR" (FIG. 5: step Sb4). Here, "NORMAL" is stored in the first status register 21. Thus, activation control logic circuit 35, the value stored in the first status register 21, determines that "NORMAL" (FIG. 5: step Sb4, NORMAL).
[0059]
　In step Sb1, the startup control logic circuit 35 is the starting surface information 13 reads the value "0x0", the value "0x0" indicates a first configuration data 11. Thus, activation control logic circuit 35 writes the start address "0x0F00000" of the first configuration data 11 in the configuration address register 23 (FIG. 5: step Sb5).
[0060]
　Activation control logic circuit 35 initializes the boot history information 14 in the flash memory 10 (FIG. 5: step Sb6), boot history information 14 in the boot surface information 13 to stored values, i.e., writing the value "0x0" (FIG. 5: step Sb7). Thus, the value stored in the boot history information 14, the value stored in the boot surface information 13 has a value "0x0" of a first configuration data 11. Activation control logic circuit 35 asserts a second status register 22. That is, the start control logic circuit 35 writes the value "0x1" in the second status register 22. Activation control logic circuit 35, the processing of the FPGA reconfiguration instruction, i.e. to re-initialize the FPGA 20 (FIG. 5: step Sb8).
[0061]
　Returning to FIG. 6, FPGA 20 is reinitialized (FPGA reinitialization) is performed by FPGA reconfiguration instruction (FIG. 6: step Sc3). Here, FPGA reconfiguration instruction, the CPU3 or external, the software control unit implemented in CPU3, not a directive commands output from such firmware control unit. FPGA reconfiguration instruction, as described above, activation control configuration data 15 is an instruction command output from activation control logic circuit 35 constructed started. At this time, each of the registers, that is, the first status register 21, the second status register 22, are stored in the configuration address register 23 and the error counter register 24, the value is held.
[0062]
　The control unit 25, the configuration process of the first configuration data 11 is started. Control unit 25, by referring to the configuration address register 23, reads circuit information start address from the area of ​​the flash memory 10, the address value "0x0F00000". As shown in FIG. 3, in the area, the first configuration data 11 is stored. Control unit 25 writes the configuration memory 26 reads out the first configuration data 11 from the flash memory 10. Control unit 25 starts the configuration process of the first configuration data 11 (FIG. 4: step Sa1, Figure 6: step Sc4).
[0063]
　Control unit 25 determines the configuration processing of the first configuration data 11, for example, whether soft error has occurred. Thus, the control unit 25 determines whether the configuration processing is performed normally (Figure 4: step Sa2, Figure 6: step Sc5).
[0064]
　Control unit 25, if the configuration processing of the first configuration data 11 is determined to have been normally performed (Figure 4: step Sa2, Yes, Figure 6: step Sc5, Mu error), clears the error counter register 24 (Figure 4: step Sa11), clears the configuration address register 23 (FIG. 4: step Sa12). Control unit 25, the second status register 22, determines whether or not asserted (Figure 4: Step Sa13). Here, since after the processing in step Sb8 in the startup control process of step Sc2, the second status register 22 is asserted. Therefore, the control unit 25 determines that the second status register 22 is asserted (Figure 4: Step Sa13, Yes).
[0065]
　Control unit 25 writes the value "0x0" indicating "NORMAL" in the first status register 21 is cleared, cleared by writing the value "0x0" in the second status register 22 (FIG. 4: step Sa14, 6 : step Sc6). Control unit 25, after the configuration process of all data of the first configuration data 11, to switch the user mode, activates the first configuration data 11, constituting the first logic circuit 31 (FIG. 4: step Sa16, Figure 6: step Sc7). Then, the control unit 25 ends the process. In this case, the first logic circuit 31 which is activated by the first configuration data 11 specified in the start-up surface information 13 the user has planned originally is operated. For this reason, corresponding to the normal operation state.
[0066]
　On the other hand, for example, if by a soft error has occurred, it is determined that the configuration processing of the first configuration data 11 is not performed normally (Figure 4: step Sa2, No, 6: step Sc5, the error Yu) will be described. In this case, the control unit 25 writes the value "0x1" indicating "ERROR" in the first status register 21. The control unit 25 is cleared by the configuration address register 23 writes the value "0x0000000" (Figure 4: Step Sa3, Figure 6: step Sc8).
[0067]
　Control unit 25 determines the second status register 22, whether or not asserted, i.e. whether the second status register 22 value "0x1" is stored (FIG. 4: step Sa4). Here, since after the processing in step Sb8 in the startup control process of step Sc2, the second status register 22 is asserted. Therefore, the control unit 25, the second status register 22, and determined to be asserted (Figure 4: Step Sa4, Yes), clears the second status register 22. That is, the control unit 25 writes the value "0x0" in the second status register, the flow returns to step Sa1 (Fig. 4: Step Sa5, Figure 6: step Sc9).
[0068]
　Proceeds to step Sc10 7, again, like configuration processing of the start control for the configuration data shown in FIG. 8 is executed in step Sc1. And activation control logic circuit 35 is configured activation control configuration data 15 is started, the startup control process shown in FIG. 5 is started by the start control logic circuit 35 (FIG. 7: Step Sc11). With reference to the flowchart of FIG. 5 illustrating the startup control process.
[0069]
　At the stage of step Sc11 is started, the first status register 21, a value indicating "ERROR", "0x1" is stored. Further, the activation surface information 13 in the flash memory 10, a value indicating the first configuration data 11 "0x0" is stored. Also, the boot history information, the value indicating the first configuration data 11 "0x0" is stored.
[0070]
　Activation control logic circuit 35 refers to the address value of the flash memory 10 '0x0EF0000 ", reads the value stored in the boot surface information 13 (FIG. 5: step Sb1). Here, as the activation surface information 13, reads the value "0x0" of a first configuration data 11. Activation control logic circuit 35 refers to the address value of the flash memory 10 '0x0EE0000 ", reads the value stored in the boot history information 14 (FIG. 5: step Sb2). Here, activation control logic circuit 35 as an activation history information 14, reads the value "0x0" of a first configuration data 11.
[0071]
　Activation control logic circuit 35 reads the values ​​stored in the first status register 21 (FIG. 5: step Sb3). Activation control logic circuit 35 determines the value stored in the first status register 21, the whether it is "NORMAL", "ERROR" (FIG. 5: step Sb4). In this case, "ERROR" is stored. Thus, activation control logic circuit 35, the value stored in the first status register 21, determines that "ERROR" (FIG. 5: step Sb4, ERROR).
[0072]
　Activation control logic circuit 35 determines the value read from the activated surface information 13, whether or not the value read from the execution history information 14 are the same (Fig. 5: Step Sb10). Here, the value of the activation surface information 13, the value of the execution history information 14 is the same "0x0". Thus, activation control logic circuit 35 determines the value read from the activated surface information 13, the value read from the execution history information 14 are the same (FIG. 5: step Sb10, Yes).
[0073]
　Activation control logic circuit 35, activated surface information inverted value circuit information indicating the value "0x1" is the value read from the 13, i.e. the second configuration start address value of the data 12 "0x2780000" configuration address register 23 written in (FIG. 5: step Sb12). Activation control logic circuit 35 initializes the boot history information 14 in the flash memory 10 (FIG. 5: step Sb13), start the inverted value is a value of the values ​​in the history information 14 stored in the boot surface information 13 "0x1 writing a "(FIG. 5: step Sb14). Thus, the value stored in the boot history information 14, the value "0x1", and the value stored in the boot surface information 13 is a value "0x0".
[0074]
　Activation control logic circuit 35, the process advances to step Sb8. Activation control logic circuit 35 asserts a second status register 22. That is, the start control logic circuit 35 writes the value "0x1" in the second status register 22. Activation control logic circuit 35, the processing of the FPGA reconfiguration instruction, i.e. to re-initialize the FPGA 20 (FIG. 5: step Sb8).
[0075]
　After the startup control process of FIG. 5 (step Sc11), back to FIG. 7, FPGA 20 is re-initialization is performed by FPGA reconfiguration instruction (FIG. 7: Step Sc12). At this time, each of the registers, that is, the first status register 21, the second status register 22, are stored in the configuration address register 23 and the error counter register 24, the value is held. That is, the first status register 21 stores a value "0x1" indicating "ERROR". The second status register 22 stores the value "0x1" indicating asserted. Configuration address register 23 stores the value "0x2780000" is the start address of the second configuration data 12. Error counter register 24 stores a value of "0".
[0076]
　The control unit 25, configuration processing of the second configuration data 12 is started. Control unit 25, by referring to the configuration address register 23, reads circuit information start address from the area of ​​the flash memory 10, the address value "0x2780000". As shown in FIG. 3, in the area, the second configuration data 12 are stored. Control unit 25 writes the configuration memory 26 reads out the second configuration data 12 from the flash memory 10. Control unit 25 starts the configuration process of the second configuration data 12 (FIG. 4: step Sa1, Figure 7: Step Sc13).
[0077]
　Control unit 25 determines the configuration processing of the second configuration data 12, for example, whether soft error has occurred. Thus, the control unit 25 determines whether the configuration processing is performed normally (Figure 4: step Sa2, Figure 7: Step Sc14).
[0078]
　Control unit 25, a second case of configuration processing of the configuration data 12 is determined to have been normally performed (Figure 4: step Sa2, Yes, Figure 7: step Sc14, Mu error), clears the error counter register 24 (Figure 4: step Sa11), clears the configuration address register 23 (FIG. 4: step Sa12). Control unit 25, the second status register 22, determines whether or not asserted (Figure 4: Step Sa13). Here, since after the processing in step Sb8 in the startup control process of step Sc11, the second status register 22 is asserted. Therefore, the control unit 25 determines that the second status register 22 is asserted (Figure 4: Step Sa13, Yes).
[0079]
　Control unit 25 writes the value "0x0" indicating "NORMAL" in the first status register 21 is cleared, cleared by writing the value "0x0" in the second status register 22 (FIG. 4: step Sa14, 7 : step Sc15). Control unit 25, after the configuration process of all data of the second configuration data 12, to switch the user mode, start the second configuration data 12, constituting a second logic circuit 32 (FIG. 4: step Sa16, Figure 7: step Sc16). Then, the control unit 25 ends the process. In this case, failure to start the first configuration data 11 specified in the start-up surface information 13 the user has planned originally, that is, failing to the configuration of the first logic circuit 31. The second logic circuit 32 constituted by the second configuration data 12 are operated. For this reason, corresponding to 擬正 normal operating state.
[0080]
　On the other hand, the control unit 25, for example, by a soft error has occurred, if the configuration processing of the second configuration data 12 is determined to have not been performed normally (Figure 4: step Sa2, No, 7 : step Sc14, explaining the process of error present). In this case, the control unit 25 writes the value "0x1" indicating "ERROR" in the first status register 21. The control unit 25 is cleared by writing to the configuration address register 23 the value "0x0000000" (Figure 4: Step Sa3, Figure 6: step Sc17).
[0081]
　Control unit 25 determines the second status register 22, whether or not asserted, i.e. whether the second status register 22 value "0x1" is stored (FIG. 4: step Sa4). Here, since after the processing in step Sb8 in the startup control process of step Sc2, the second status register 22 is asserted. Therefore, the control unit 25, the second status register 22, and determined to be asserted (Figure 4: Step Sa4, Yes), clears the second status register 22. That is, the control unit 25 writes the value "0x0" in the second status register, the flow returns to step Sa1 (Fig. 4: Step Sa5, Figure 7: Step Sc18).
[0082]
　Again, like the configuration process of activation control configuration data shown in FIG. 8 is executed as step Sc1 and step Sc10 (FIG. 7: Step Sc19). And activation control logic circuit 35 is configured activation control configuration data 15 is started, the startup control process shown in FIG. 5 is started by the start control logic circuit 35 (FIG. 7: Step Sc20). While referring to the startup control process to the flowchart of FIG. 5 (step Sc20) will be described.
[0083]
　At the stage of step Sc20 is started, the first status register 21, a value indicating "ERROR", "0x1" is stored. Further, the activation surface information 13 in the flash memory 10, a value indicating the first configuration data 11 "0x0" is stored. Also, the boot history information, the value indicating the second configuration data 12 "0x1" is stored.
[0084]
　Activation control logic circuit 35 refers to the address value of the flash memory 10 '0x0EF0000 ", reads the value stored in the boot surface information 13 (FIG. 5: step Sb1). Here, as the activation surface information 13, reads the value "0x0" of a first configuration data 11. Activation control logic circuit 35 refers to the address value of the flash memory 10 '0x0EE0000 ", reads the value stored in the boot history information 14 (FIG. 5: step Sb2). Here, activation control logic circuit 35 as an activation history information 14, reads the value "0x1" of a first configuration data 11.
[0085]
　Activation control logic circuit 35 reads the values ​​stored in the first status register 21 (FIG. 5: step Sb3). Activation control logic circuit 35 determines the value stored in the first status register 21, the whether it is "NORMAL", "ERROR" (FIG. 5: step Sb4). In this case, "ERROR" is stored. Thus, activation control logic circuit 35, the value stored in the first status register 21, determines that "ERROR" (FIG. 5: step Sb4, ERROR).
[0086]
　Activation control logic circuit 35 determines the value read from the activated surface information 13, whether or not the value read from the execution history information 14 are the same (Fig. 5: Step Sb10). Here, different from the value of the activation surface information 13, the value of the execution history information 14. Thus, activation control logic circuit 35, the value read from the activated surface information 13, the value read from the execution history information 14 is determined not to be identical (FIG. 5: step Sb10, No), as hardware failure It ends the start control process (step Sb11). In this case, the user has failed to the configuration of the first logic circuit 31 according to the first configuration data 11 specified in the start-up surface information 13 which has been planned originally. Then, it has failed to configure the second configuration data 12 that started in place of the second logic circuit 32. For this reason, corresponding to the abnormal termination state.
[0087]
　In the above embodiment, in FIG. 6 and FIG. 7 has been described process of specifying the value "0x0" of a first configuration data 11 to start surface information 13. However, not limited to these embodiments. If the activation surface information 13 specifying the value "0x1" of a second configuration data 12, start of the second configuration data 12 is performed first. When the failure of the second configuration data 12 to the configuration of the second logic circuit 32, start of the first configuration data. Furthermore, if the first configuration data 11 also fails to the configuration of the first logic circuit 31, to fail.
　To summarize the processing described in the above embodiment, it indicated by relationship shown in the table of FIG. In the table of FIG. 9, the pattern 1, 3, 5, corresponds to the pattern described with reference to FIGS. 6-8. Pattern 2, 4, 6 and 8, corresponds to the pattern of specifying a value of a second configuration data 12 to start surface information 13.
[0088]
　As it has been described in the above embodiment, the flash memory 10, the first configuration data 11, a second configuration data 12, and stores the activation control configuration data 15. As a boot control configuration data 15, when the configuration of the logic circuit according to any one of the first configuration data 11 or the second configuration data 12 fails, the other configuration data has not failed is selected . FPGA20 the time of startup, or when the configuration of the logic circuit according to any one of the circuit information has failed, reads the startup control configuration data 15 from the flash memory 10. FPGA20 constitutes a start control logic circuit 35 in response to the read start control configuration data 15. FPGA20 reads either the first configuration data 11 or the second configuration data 12 that is not failed configuration of a logic circuit selected by the activation control logic circuit 35 which is composed of a flash memory 10, the read configuration to configure the logic circuit in accordance with the configuration data. Thus, in the FPGA 20, if it fails to the configuration of the logic circuit in any of the configuration data of the first configuration data 11 or the second configuration data 12, without using the control device, such as another PLD, failure it is possible to start with other configuration data that is not.
[0089]
　Further, the configuration of the above embodiment, even if it fails the various factors in the configuration process, it is possible to start the other configuration data. Therefore, it is possible to provide redundant features such as the system does not stack comprising a FPGA 20. Thus, the integrated circuit system 1 according to this embodiment, it is possible to improve the mounting area and the apparatus cost ratio. Further, the configuration of the present embodiment, while having an effect with a technique shown in Patent Document 1, it is possible to reduce the mounting area and BOM (Bill of Materials) cost. Thus, it is made possible to contribute to achievement of cost and mounting area in the device development.
[0090]
　As described above, the processing shown in FIG. 4, is provided to activate the circuit information included in the logic circuit that is actually utilized, such as, the first configuration data 11 second configuration data 12 It has been realized by using the function of FPGA20. The first storage area of ​​the flash memory 10, i.e., allowed to store a start control for the configuration data 15 in the region of the address value "0x0000000". Thus, when the FPGA20 is activated, by configuring the address register 23 is initialized, the configuration address register 23 stores the value "0x0000000" is the start address of the start control configuration data 15. Thus, at the time of startup of the FPGA 20, it will be always started from the configuration process start control for the configuration data 15. Also, if it fails to the configuration of the logic circuit in any of the configuration data, in step Sa3 of Fig. 4, the configuration address register 23 is cleared, the value "0x0000000". This will be initiated from the configuration process start control for the configuration data 15 again. Thus, the activation control configuration data 15, when the configuration of the logic circuit according to any one of the first configuration data 11 or the second configuration data 12 fails, the other configuration data not failed by defining the processing for starting, without using the control device, such as another PLD, it is possible to start with other configuration data that is not to fail.
[0091]
　The arrangement in the flash memory 10 of FIG. 3 is an example, not limited to the subject embodiment. For example, a start control for the configuration data 15, it is not kept and stored address value in the flash memory 10 to "0x0000000" as the start address. Activation control configuration data 15 may be stored in another storage area of ​​the flash memory 10. However, in that case, for example, if the FPGA20 is first started, the process of writing the configuration address register 23 to start control for the configuration data 15 the start address (other addresses of the storage area) before the process in step Sa1 is It takes place. Further, in step Sa3, instead of clearing the configuration address register 23, processing is performed to write the start address of the start control configuration data 15.
[0092]
　In the above embodiment, the flash memory 10 may be composed of a plurality of flash memories. In this case, the first configuration data 11 and the second configuration data 12 and the like may be stored in different flash memory.
[0093]
　In the above embodiment, the first configuration data 11 has been described processing by two configuration data referred to as second configuration data 12. However, non-startup control configuration data 15, the configuration data of the first configuration data 11 and the second configuration data 12 a user uses the operation may be a plurality. In that case, the activation surface information 13 is configured to be able to specify multiple configuration data. Furthermore, activation in the history information 14, just prior to not only the history of the configuration data that failed to start, leaving also history of configuration data that failed to start in the past. Further, in the processing shown in FIG. 5, with reference to the execution history information 14 for storing a history of configuration data that failed to start in the past, configuration data not fail to start, the process used by switching in the order It is carried out.
[0094]
　Further, in the above embodiment has been described as a target FPGA 20, it may be applied to volatile programmable devices other than FPGA 20.
[0095]
　FPGA20 reads the startup control program that corresponds to the start control circuit information described above from the flash memory 10, by starting and stored in the configuration memory 26, and functions as a device comprising a start control circuit. Activation control program may be recorded on a computer-readable recording medium. The computer readable recording medium, for example, a flexible disk, a magneto-optical disk, ROM, portable media such as a CD-ROM, a storage device such as a hard disk built in the computer system. Activation control program may be transmitted via an electric communication line.
[0096]
　Figure 13 is a diagram showing a minimum configuration of an integrated circuit system.
　Integrated circuit system may be Sonaere at least a memory element, and an integrated circuit.
　Storage device (flash memory 10) includes a plurality of circuit information, pre-stores a startup control circuit information used in configuration of the activation control logic circuit for selecting the circuit information not fail to configure logic circuits.
　Integrated circuits (FPGA 20) is the time of startup, or any of the circuit when the configuration of the logic circuit fails due to information, activation control logic circuit from the storage device activation control circuit information read out of said plurality of circuit information constitute a. The integrated circuit, to select the circuit information not fail to configure the logic circuit arrangement the activation control logic circuit. Integrated circuit performs a configuration of a logic circuit according to the circuit information is read circuit information is selected activation control logic circuit from the storage element.
[0097]
　Have been described above in detail with reference to the accompanying drawings, embodiments of the present invention, the specific configuration is not limited to this embodiment also includes designs and the like without departing from the scope of the invention.
[0098]
　This application claims priority based on Japanese Patent Application has been Japanese Patent Application No. 2017-055025 on March 21, 2017, the entire disclosure of which is incorporated herein.
Industrial Applicability
[0099]
　According to the present invention, the programmable integrated circuit, if it fails to start, without using another control device, it is possible to start with other circuit information not fail.
DESCRIPTION OF SYMBOLS
[0100]
1 integrated circuit system
2 connecting lines
3 CPU
4 PC
5 JTAG Connector
10 flash memory
20 FPGA
21 first status register
22 second status register
23 configuration address register
24 error counter register
25 the control unit
26 configuration memory
27 programmable elements
28 I / O circuit
29 JTAG circuit
31 first logic circuit
32 and the second logic circuit
35 starts the control logic circuit

The scope of the claims

[Requested item 1]A plurality of circuit information, a memory element for storing in advance a configuration startup control circuit information used for the activation control logic circuit for selecting the circuit information not fail to configure the logic circuitry,
　upon activation, or , wherein according to any of the circuit information of the plurality of circuit information when the configuration of the logic circuit fails, a logic circuit for the activation control from the memory device reads out the start control circuit information, constituted the start the to the control logic circuit to select the circuit information not fail to configure logic circuits corresponding to the circuit information by reading the circuit information selected in the start-up control logic circuit from the storage device the , an integrated circuit for performing a configuration of a logic circuit
　integrated circuit system comprising: a.
[Requested item 2]
　The storage element,
　the store failed boot history information the is information about the circuit information on the configuration of the logic circuit,
　the activation control logic,
　by referring to the execution history information, the configuration of the logic circuit selecting said circuit information not failed
　integrated circuit system according to claim 1, characterized in that.
[Requested item 3]
　Wherein the plurality of circuit information, and a first circuit information and the second circuit information,
　the activation history information is information indicating the circuit information which the integrated circuit immediately before is read from the storage element,
　the memory element includes
　a first circuit information, said one of the second circuit information storing boot surface information initially indicating to start,
　the integrated circuit,
　the circuit information which the boot history information indicates but wherein it comprises a storage unit for storing information indicating whether the successful construction of the logic circuit,
　the activation control logic circuit,
　and the activation surface information, said activation history information, the storage unit based on the storage information, the activation surface information into configuration of the logic circuit by the circuit information indicated by, if the start face information while the circuit information indicated fails to configuration of the logic circuit, the other before select the circuit information And configure the logic circuit when said other circuit information fails to the configuration of the logic circuit, and terminates the processing
　integrated circuit system according to claim 2, characterized in that.
[Requested item 4]
　The start control circuit information
　is stored at the head of the storage area of the storage element,
　said integrated circuit
　during the activation, or the configuration of the logic circuit according to the any of the circuit information has failed when, by reading from the information stored at the head of the memory element, the logic circuit for the activation control from the memory device reads out the start control circuit information
　from claim 1, wherein the 3 integrated circuit system according to any one of.
[Requested item 5]
　A storage element for storing a plurality of circuit information, a start control method in an integrated circuit system comprising an integrated circuit which reads the circuit information from the storage device to configure the logic circuit in accordance with the circuit information,
　the stores the start control circuit information used in configuration of the activation control logic circuit for selecting the circuit information not fail to configure logic circuits in the memory device,
　upon activation, or, of the plurality of circuit information when the configuration of the logic circuit according to any one of the circuit information has failed, on the basis of the start control circuit information of the storage device, constitute the activation control logic circuit to the integrated circuit,
　configured to said start control use logic circuit selects the circuit information not fail configuration of the logic circuit, based on the circuit information which the activation control logic has selected, the integrated circuit To configure the logic circuit
　activation control method for an integrated circuit system, characterized in that.
[Requested item 6]
　It is connected to a storage device for storing a plurality of circuit information, the integrated circuit constituting the logic circuit in accordance with the circuit information,
　upon activation, or configuration of the logic circuit according to any one of the circuit information of the plurality of circuit information There upon failure to configure a start control logic circuit, said by selecting the circuit information not fail configuration of the logic circuit to start the control logic circuit,
　the circuit information in which the activation control logic circuit selects the so read out from the memory element, the circuit the cause the configuration of a logic circuit according to the information
　the activation control program is a start control circuit information for executing that.