[Document Name] Specification [Title of the Invention] JITTER SUPPRESSION CIRCUIT AND JITTER SUPPRESSION METHOD [Technical Field] [0001] The present invention relates to a jitter suppression circuit and a jitter suppression method. [Background Art] [0002] In a digital transmission network, a pulse stuffing method is used for multiplexing asynchronous signals. In a pulse stuffing method, destuffing processing is needed in a receiving end. Because a signal for which destuffing processing has been performed has a large jitter, this jitter needs to be suppressed. [0003] Conventionally, as a suppression means of a destuffing jitter, as disclosed in patent document 1, a method using a memory and a digital phase locked loop (DPLL) has been formulated. In this method, a jitter included in input clock and input data can be suppressed by writing the input data in a memory once, reading the data from the memory using an output clock with less jitter, and then outputting it. Frequency synchronization is maintained between the input clock and the output clock by a DPLL so that the data discontinuity by the overflow or underflow of the memory does not occur. [0004] Generally in a PLL (Phase Locked Loop) ,m order to make a pull-in time short, the loop bandwidth needs to be expanded. On the one hand, in order to suppress a jitter component of an input signal, the loop bandwidth needs to be narrowed so that the output clock does not follow the jitter of then input clock. The loop bandwidth is determined by the bandwidth of a loop filter mainly. [0005] Accordingly, in a conventional jitter suppression circuit, in order to achieve a high jitter suppression effect, the bandwidth of the loop filter needs to be narrowed, and as a result, there is a problem that a pull-in time becomes long. [0006] Also in a PLL, as disclosed in patent document 2, for the purpose of shortening a pull-in time and of improving stability when synchronized, a means to detect whether a phase difference between an input signal and an output signal is no smaller than a predetermined value or not, and change a parameter of a loop filter according to the detection result is being proposed. [0007] Because a PLL is generally used to make an output signal phase-locked to an input signal, a phase error between the input signal and the output signal is small when they are in a synchronous state. Accordingly, the means to perform parameter change according to whether a phase error is no smaller than a predetermined value is effective in shortening a pull-in time and improving stability at the time of synchronization. Additionally, as a related art, patent documents 3-7 are cited, for example. [Patent document 1] Japanese Patent Application Laid-OpenNo. 1992-246939 [Patent document 2] Japanese Patent Application Laid-Open No. 1997-200049 [Patent document 3] Japanese Patent Application Laid-Open No. 2000-031953 [Patent document 4] Japanese Patent Application Laid-Open No. 2003-023353 [Patent document 5] Japanese Patent Application Laid-OpenNo. 2007-036366 [Patent document 6] Japanese Patent Application Laid-Open No. 1993-327782 [Patent document 7] Japanese Patent Application Laid-Open No. 1994-053821 [Disclosure of Invention] [Problem(s) to be Solved by the Invention] [0008] However, in a PLL in a jitter suppression circuit, an input clock has a large jitter component, and thus it is necessary that an output clock does not follow a jitter component. Accordingly, even in a synchronous state, there may be a case when a phase difference between an input clock and an output clock becomes a large value momentarily. So, when the above-mentioned method is plied just as it is, as a result of mis-determination that it is m the asynchronous state when it is, in reality, in a synchronous state, an unnecessary change of a parameter occurs, and the jitter suppression characteristics degrades. Therefore, there is a problem that it is difficult to satisfy both of shortening of a pull-in time and high jitter suppression characteristics. [0009] Accordingly, the object of the present invention is to provide a jitter suppression circuit and a jitter suppression method which satisfy both of shortening of a pull-in time and high jitta-suppression characteristics. [Means for Settling the Problem] [0010] A' first circuit of the present invention is, in a jitter suppression circuit using a digital phase locked loop, characterized in that shortening of a pull-in time and suppression of a jitter is achieved by determining whether the loop is in a synchronous state fi-om a phase difference between an input clock and an output clock, and then changing characteristics of a loop filter accordmg to the determination result. [0011] A second circuit of the present invention is characterized in that, in addition to the aforementioned constitution, it comprises: a clock transferring part which performs retiming of an input data; and a digital phase locked loop which suppresses a jitter of an output data of the clock transferring part and an output clock by changing characteristics of a loop filter according to a determination result of whether the loop is in a synchronous state or not [0012] A third circuit of the present invention is characterized in that, in addition to aforementioned constitution, the clock transferring part comprises: a serial/parallel converting circuit which performs serial-to-parallel conversion of input data; a flip-flop circuit viiich changes timing of parallel data from the serial/parallel converting circuit; and a parallel/serial converting cu-cuit which performs parallel-to-serial conversion of data fix)m the flip-flop circuit, wherein the digital phase locked loop comprises: a phase comparator which compares a phase difference between an input clock of the clock transferring part and an output clock; a numerical control oscillator which supplies a clock signal to the flip-flop circuit and the parallel/serial convertmg circuit; a loop filter inserted between the phase comparator and the numerical control oscillator; and a parameter selection circuit which selects and changes a parameter of the loop filter according to output of the phase comparator. [0013] A fourth circuit of the present invention is characterized in that, in addition to aforementioned constitution, the above-mentioned phase comparator comprises: an input-side rising edge detection circuit which detects a rising edge of an iiq)ut-side phase comparison signal which is generated by dividing the input clock; an output-side rising edge detection circuit which detects a rising edge of an output-side phase comparison signal which is generated by dividing the output signal; a counter which detects a phase difference by counting a period fixim a rising edge of the input-side phase comparison signal to a rising edge of the ouut-side phase comparison signal by a sampling clock. [0014] A first method of the present invention is, in a jitter suppression method using a digital phase locked loop, characterized in that shortening of a pull-in time and suppression of a jitter is achieved by detennining whether the loop is in a synchronous state or not from a phase difference between an input clock and an output clock, and changing characteristics of a loop filter according to the determination result. [0015] The second method of the present invention is chmacterized in that, in addition to aforementioned constitution, a jitter of output data of said clock transferring part and an output clock is suppressed by performmg retiming for an input data by a clock transferring part, and by changing characteristics of a loop filter according to a determination result of whether, in a digital phase locked loop, the loop is in a synchronous state or not. [The Effect of the Invention] [0016] According to the present invention, in a jitter siq)inession circuit using a digital phase locked loop, both of shortening of a pull-in time and a high jitter suppression effect can be satisfied by determining whether the loop is in a synchronous state or not using a phase difference between the input clock and the ouut clock, and tlum changing chanu;teristics of a loop filter according to the determination result. [Best Mode for Carrying Out the Invention] [0017] An embodiment of a jitter suppression circuit according to the present invention is m a jitter suppression circuit using a digital phase locked loop, characterized in that shortening of a pull-in time and suppression of a jitter is achieved by determining viiether tiie loop is in a synchronom state from a phase difference between an input clock and an output clock, and changing characteristics of a loop filter according to the detomination result. [0018] According to aforementioned constitution, both shortening of a pull-in time and suppression of a jitter is satisfied by determining whether the loop is in a synchronous state using a phase difference between the input clock and the output clock, and changmg characteristics of a loop filter according to the determination result. Because an expaisive voltage controlled oscillator and other analog parts are not needed, and integration can be achieved easily, cost can be reduced. In addition, by using a DPLL, it is possible to realize constant jitter suppression characteristics without being influenced by aging changes and temperature changes. [0019] Another embodiment of a jitter suppression circuit according to the present invention is • characterized in that it comprises: a clock transferring part by which retiming of an input data is performed; and a digital phase locked loop which suppresses a jitter of an output data of the clock transferring part and an output clock by changing characteristics of a loop filter according to a determination result of whether the loop is in the synchronous state or not. [0020] According to aforementioned constitution, both shortening of a pull-in time and suppression of a jitter is satisfied by determining whether the loop is in a synchronous state using a phase difference between the input clock and the ouut clock, and changing characteristics of a loop filter according to ibs determination result. Because an expensive voltage controlled oscillator and other analog parts are not needed, and thus integration can be achieved easily, cost can be reduced. In addition, by using a DPLL, it is possible to realize constant jitter suppression characteristics without being influenced by aging changes and temperature changes. [0021] Yet another embodiment of a jitter suppression circuit according to the present invention is characterized in that, in addition to aforementioned constitution, the clock transferring part comprises: a serial/parallel converting circuit wiiich performs serial-to-parallel conversion of input data; a fiip-flop circuit which changes timing of parallel data from the serial/parallel convertmg circuit; and a parallel/serial converting circuit which performs parallel-to-serial conversion of data fim the flip-flop circuit, and the digital phase locked loop comprises: a phase comparator which compares a phase difference between an input clock of the clock transferring part and an output clock; a numerical control oscillator which supplies a clock signal to the flip-flop cutjuit and the parallel/serial convating circuit; a loop filter mserted between the phase comparator and the numerical control oscillator, and a parameter selection circuit which selects and changes a parameter of the loop filter according to output of the phase comparator. [0022] According to aforementioned constitution, both shortening of a pull-in time and suppression of a jitter is realized by determining whether the loop is in a synchronous state using a phase difference between then input clock and the output clock, and changing characteristics of a loop filter according to the determination result. Because an expensive voltage controlled oscillator and other analog parts are not needed, and thus integration can be achieved easily, cost can be reduced. In addition, by using a DPLL, it is possible to realize constant jitter suppression characteristics without being influenced by aging changes and temperature changes. [0023] The other embodiment of a jitter suppression circuit according to the present invention is characterized in that, in addition to aforementioned constitution, the phase comparator comprises: an input-side rising edge detection circuit which detects a rising edge of an input-side phase comparison signal vch is generated by dividing the input clock; an output-side rising edge detection circuit which detects a rising edge of an output-side phase comparison signal which is generated by dividmg an ouut signal; a counter yMch detects a phase difference by counting a period from a rising edge of the input-side phase comirarison signal to a rising edge of the ouut-side phase comparison signal by a samplmg clock. [0024] According to aforementioned constitution, both shortening of a pull-in time and suppression of a jitter is satisfied by determining whether the loop is m a synchronous state usmg a phase difference between the input clock and the output clodc, and changing charactoistics of a loop filter according to the determination result Because an expensive voltage controlled oscillator and other analog parts are not needed, and thus integration can be achieved easily, cost can be reduced. In addition, by using a DPLL, it is possible to realize constant jitter suppression characteristics without being influenced by aging changes and temperature changes. [0025] An embodiment of a jitter suppression method according to the present invention is, in jitter suppression method using a digital phase locked loop, characterized in ihst shortening of a pull-in time and suppression of a jittra: is achieved by dermining >iiether the loop is m a synchronous state fix)m a phase difference between an input clock and an output clock, and changing characteristics of a loop filter according to the determination result. [0026] According to aforementioned constitution, both rtoiing of a pull-in time and suppression of a jitter is satisfied by determining whethra: the loop is in a synchronous state using a phase difference between flie input clock and the output clock, and changing characteristics of a loop filter according to the determination result. Because an expensive voltage controlled oscillator and oiher analog parts are not needed, and thus integration can be achieved easily, cost can be reduced. In addition, by using a DPLL, it is possible to realize constant jitter suppression characteristics without being influenced by agii changes and temperature changes. [0027] Another embodiment of a jitter suppression method according to the present mvention is characterized in that, m addition to aforementioned constitution, retiming is performed for an input data by the clock transferring part and a jitter of output data of the clock transfraring part 1 and the output clock is suppressed by changing, in a digital phase locked loop, characteristics of a loop filter according to the determination result of whether the loop is in a synchronous state. [0028] Further, the embodiments mentioned above indicate an example of the preferred embodiments of the present invention, and various kinds of modified implementation are possible within the range that does not depart fi-om the point of the present invention without being limited to this. The present invention will be described in detail using an example. [Example 1] [0029] (Structure of the Example) Fig. 1 is a block diagram which shows an example of a jitter suppression circuit according to the present invention. A jitter suppression circuit shown in Fig. 1 includes a clock transferring part 1 and a digital phase locked loop (DPLL) 2 when separated generally. The clock transferring part 1 includes a serial/parallel convting circuit 4, an input-side timing signal generating circuit 5, an output-side timing signal generating circuit 11, a D fiip-fiop 10 and a parallel/serial converting circuit 14. The DPLL 2 includes an input-side fi%quency divider 6, an output-side fiuency divider 12, a phase comparator 7, a parameter selection circuit 8, a loop filter 9 and a numerical control oscillator 13. Each component of the clock transferring part 1 and the DPLL 2 will be described below. [0030] Fu "clock transferring" means "to change the opwation clock of a flip-flop which performs retiming of data." In Fig. 1, although up to the serial/parallel converting circuit 4, the inner D flip-flop 10 is being operated by an input clock, in the D flip-flop 10, it is being operated by an ouut clock. Accordingly, at the D flip-flop 10, it means that the operation clock is transferred fi-om the input clock to the output clock. Although output data of the D flip-flop 10 is outputted from the parallel/serial converting circuit 14 to outside finally, flip-flops in the parallel/serial converting circuit 14 also operate using the output clock. [0031] The serial/parallel converting circuit 4 converts an input data to parallel data based on a timing signal inputted fi-om the input-side timing signal generating circuit 5. The input-side fi«quency divider 6 divides the input clock and ouuts its output to the input-side timing signal generating circuit 5 and the phase comparator 7. In the input-side timing signal generating circuit 5, a timing signal for performing a serial to parallel conversion is generated based on the divided clock inputted from the input-side frequency divider 6 and then siq)plied to the serial/parallel convoting circuit 4. The phase comparator 7 detects a phase error betweoi a phase comparison signal in the input side and a phase comparison signal in the output side, aiad outputs phase error information to the parameter selection circuit 8 and the loop filter 9. The parameter selection circuit 8 obtains the absolute value of the inputted phase error information and compares it with a phase error threshold value set in advance. If the comparison result continues to be no smaller than the lase error tiueshold value for predetermined forward proton stage count times, it is determined that the loop is in an asynchronous state, and parameter a 1 and p 1 correspondii to a broad-bandwidth are ouutted to the loop filter 9. [0032] Here, "continuation for predetermined forward protection stage count times " corresponds to a counter 83 and a comparator 85 of Fig. 4. Although "forward protection" is protection operation when detemiining a transfer fix>m a syacbtonoas state to an asynchronous state, description will be omitted because operation itself is similar to that of backward protection. Similarly, when the comparison result continues to be less than the phase error thresAiold value for backward-protection-step-count times, parameter a 2 and P 2 corre>ondii to a narrow-bandwidth are outputted. The loop filter 9 averages phase error information using coefficients a and P supplied from the parameter selection circuit 8 and outputs a phase control value. The numerical control oscillator 13 controls the phase of the output clock according to the phase control value supplied fix)m the loop filter 9. The ouut-side frequency divider 12 divides the output clock and outputs the divided clock to the output-side timing signal gei-ating circuit 11 and the phase comparator 7. In the output-side timing signal genoting circuit 11, a timing signal for taking m output of the serial/parallel converting circuit 4 by the D flip-flop 10 is generated. In the parallel/serial converting circuit 14, parallel data of the D flip-flop 10 output is converted back to serial data, and then ouutted to outside. [0033] Fig. 2 is a block diagram showing an example of the serial/parallel converting circuit 4 that is used for a jitter suppression circuit shown in Fig. 1. As shown in Fig. 2, the serial/parallel converting circuit 4 is realized by combination of a shift register in which D flip-flops 40-42 are connected in series, and D flip-flops 43-46 with an enable terminal which latch the output of the shift register based on a timing signal. The ratio of the serial/parallel conversion is determined by the jitter amount of the input clock and the required suppression quantity. When a jitter of the input clock is large, in order to reserve an enough tuning margin, the conversion ratio needs to be niade large. Fig. 2 shows an example in which every 4 bits of input data are converted into 4-bits parallel data. [0034] Fig. 3 is a block diagram showing an example of tiie phase comparator 7 that is used for a jitter suppression circuit shown m Fig. 1. In Fig. 3, a rising edge detection circuit 70 and a rising edge detection circuit 71 detect a rising edge of an input-side phase comparison signal and an output-side phase comparison signal, respectively, to generate a pulse, and then output it to a counter 72. In the counter 72, the pulses ouutted from the rising edge detection circuit 70 and &e rising edge detection circuit 71 are used as a count start signal and a count stop signal, req)ectively. The count stop signal is outputted to the parameter selection circuit 8 as a synchronization determination timing signal after retiming is performed by a D flip-flop 73. The counter 72 performs counting using a sampling clock after a count start signal is inputted until a count stop signal is inputted, and outputs the count value at the time when the count stop signal is inputted. [0035] The sampling clock is a clock which is outputted from an oscillator 3 and has a sufficiently higher frequency than the input/output clock. An adder 74 subtracts a phase ofTset value set in advance from output of the counter 72 and ouuts the result to the parameter selection circuit 8 and the loop filter 9 as phase error information. The phase offset value is a value for specifying a phase difference between the input side and the output side when a loop is in a synchronous state. Usually, a phase offset value is set so that just the center of the data may be taken in when data converted into parallel data is transferred to the output clock. As a result, the margin for the jitter of an input clock is maximized. [0036] Fig. 4 is a block diagram showing an example of the parameter selection circuit 8 that is used for a jitter suppression circuit shown in Fig. 1. In Fig. 4, an absolute value converter 80 converts phase error information inputted from the phase comparator 7 into an absolute value. A comparator 81 compares the phase error absolute value and a phase error threshold value (2 in Fig. 4 ) set in advance and outputs the comparison result to the counter 83 through an inversion gate 82 and to a counter 84. In the counter 83, countii up is performed by a sampling clock based on a synchronization determination timing signal inputted fix>m the phase comparator 7. When output of the inversion gate 82 is '1', the count value is cleared. A comparator 85 compares the count value of the counter 83 and a predetermined forward protection stage count (3 in Fig. 4) and inputs the result to the set terminal of a set/reset flip-flop (S/R flip-flop) 87. Similarly, the counter 84 pm the loop filter 9, a fi%quency offset value set in advance and ouut of the D flip-flop 132, and outputs the result to the modulo 8 arithmetic unit 131. The D flip-flop 132 holds the output of the modulo 8 arithmetic unit of one clock before. In the case of a synchronous state, because a phase control value is approximately 0, output of tiie adder 130 increases by 1 (fi«quency offset value) m every one clock. In the modulo 8 arithmetic unit 131, when adder ouut increases to 8 (the set value of the modulo arithmetic unit), the remainder of subtracting just 8 fix)m the adder output is outputted to the D flip-flop 132 and the comparator 133. By repeating the above mentioned operation, output of the modulo 8 arithmetic unit repeats numerical values of 0-7. [0056] In the comparator 133, the ouut of a modulo 8 arithmetic unit and the threshold value set in advance (4 in Fig. 6) is compared, and when it is no smaller than the threshold value, 'I'is ouutted, and when it is less than the threshold value, '0' is outputted. This threshold value sets a numerical value of 1/2 of modulo calculation. As a result, m output of the comparator 133, the proportions of '1' and '0' become even. After poforming retiming of outputs of the comparator 133, the D flip-flop 134 outputs it to the D flip*flop 10, the output-side timing signal generating circuit 11, the output-side firequency divider 12, the parallel/serial converting circuit ID 14 and outside as the ovttput clock. [0057] As shown in Fig. 10, wiien a phase difiference between an input-side phase comparison signal and an output-side phase comparison signal is smaller than 180 degrees, a phase control value will be a negative value. As shown in Fig. 12, m the numerical control oscillator 13, when a negative phase control value is inputted, it is controlled so that the phase of the output clock may be delayed. Conversely, when the phase diflTerence is larger than 180 degrees, a phase control value will be a positive value, and it is controlled so that phase lead of the output clock may be achieved. Thus, the DPLL 2 performs control so that a phase difference between an input-side phase comparison signal and an output-side phase comparison signal may be always kept to 180 degrees. [Example 2] [0058] A block diagram of another example of a jitter si:q>pression circuit according to the present invention is shown in Fig. 13. In Fig. 13, in the parameter selection circuit 8, ouut of the loop filter 9 is used as phase error information for synchronization determination. In c(»nparison with the case where output of the phase comparator 7 is used for synchronization determination as is in a jitter suppression circuit shown in Fig. 1, because avenged phase error information is beii used, more correct synchronization determination can be performed, although a quick parameter change cannot be performed. [0059] A modified example of tiie loop filter 9 that is used in a jitter suppression cuxniit shown in Fig. 1 is shown in Fig. 14. It is a digital filter with low pass characteristics like the case shown in Fig. 5, and its fi«quency characteristic is expressed in the formula (2). From the formula (2), it can be found out that, also by using the structure of Fig. 14, a bandwidth is able to be set by changing values ofaandp. H (jm) = p/(l-a-exp-jco)... (2) [0060] That is, accordmg to the present invention, in a jitter suppression circuit using a digital phase locked loop (DPLL), both shortening of a pull-in time and high jitter suppression effect is satisfied by determinmg whether the loop is in a synchnmous state fix)m a phase difference between an input clock and an output clock, and tiien changing characteristics of a loop filter tccordiiig to the determination result. [0061] In Fig. 1, the phase comparator 7 detects a phase error between an mput-side phase comparison signal and an output-side phase comparison signal, and outputs phase error information to the parameter selection circuit 8 and the loop filter 9. The parameter selection circuit 8 compares the absolute value of the inputted phse error information and a phase error threshold value set in advance. When the phase error information is no smaller than the phase error threshold value for predetermined forward protection stage count times continuously, it is determined that the loop is in an asynchronous state, and parameters a 1 and P 1 which make the bandwidth of the loop filter 9 wide are outputted. Also, when it is less than the phase error threshold value for predetermined backward protection stage count times continuously, it is determined that a loop is in a synchronous state and values of coefficients a 2 and the P 2 which make the bandwidth narrow are outputted. [0062] Here, the portions correspondmg to "continuation for predetermined backward protection stage count times" are the counter 84 and the comparator 86 of Fig. 4. "Backward protection" is for improving reliability of determination when performing synchronization determination (determination of transition fi-om a asynchronous state to a synchronous state). When described referring to Fig. 4, in the comparator 81, although temporary synchronization determination is performed by whether inputted phase error information is smaller than a phase error threshold value or not, this phase difference error mfoimation is not information which can be trusted absolutely (that is, in spite of being in an asynchronous state, there may be a case where phase error information is smaller than a phase error threshold value, and also a case where phase error information is larger than a phase error threshold value.) Accordingly, in the counter 84, counting of the number of times that phase error information is continuously smaller than the phase error threshold value is performed. Then, in the comparator 86, the count value and a predetermined protection stage count value (such as 3 times, for example) are compared, and when it is no smaller than the protection ste count, it is determined for the first time that it is in a synchronous state. Thus, the jitter suppression effect is improved by shortening a pull-in time by expanding the bandwidth of the loop filter 9 when judgment has been made that the loop is in an asynchronous state, as well as by narrowing the bandwidth of the loop filter 9 when it is determined the loop is in a synchronous state. [0063] Further, the embodiment mentioned above mdicates an example of the preferred embodiments of the present invention, and various kinds of modified implementation are possible within the range that does not depart fi-om the point of the present invention without lunited to this. For example, in the example mentioned above, although the description has been made using the phase comparator shown in Fig. 3, the present invention is not limited to this, and a phase comparator of an EOR (exclusive logical sum) type may be used. (Description of the Effect) As it has been described above, the present inventicm has the effects indicated bellow. The first effect is that, in a jitter suppression circuit using a DPLL, both shortening of a pull-in time and high jitter suppression effect can be satisfied by determining whether the loop is in a synchronous state or not fix>m a phase difference between an input clock and an output clock, and then changing characteristics of a loop filter according to the determination result [0064] The second effect is that, by using a DPLL, an expensive voltage controlled oscillator and other analog parts are not needed, and thus integration can be achieved easily, resulting in cost reduction. [0065] The third effect is that, by using a DPLL, it is possible to realize constant jitter suppression characteristics without being influenced by aging changes and temperature changes. [0066] This application is based upon and claims the benefit of priority firom Japanese Patent Application No. 2007-236563, filed on September 12, 2007, the disclosure of which is incorporated herein in its entirety by reference. [Industrial Applicability] [0067] The present invention can be used for a digital communication apparatus and digital equipment using a DPLL, and thus it has industrial applicability. [Brief Description of the Drawings] [0068] [Fig. 1] A block diagram showing an example of a jitter suppression circuit according to the present invention [Fig. 2] A block diagram showing an example of the saial/parallel convrating circuit 4 that is used for a jitter suppression circuit shown in Fig. 1 [Fig. 3] A block diagram showing an example of the phase comparator 7 tiiat is used for jitter suppression circuit shown in Fig. 1 [Fig, 4] A block diagram showing an example of the parameter selection circuit 8 that is used for a jitter suppression circuit shown in Fig. 1 [Fig. 5] A block diagram showing an example of the loop filter 9 that is used for a jitter suppression circuit shown in Fig. 1 [Fig. 6] A block diagram showing an example of the numerical control oscillator 13 that is used for a jitter suppression circuit shown in Fig. 1 [Fig. 7] A block diagram showing an example of tfie parallel/serial converting circuit 14 that is used for a jitter suppression circuit shown in Fig. 1 [Fig. 8] An example of a timing chart of a jitter si:q>pression circuit shown in Fig. 1 [Fig. 9] An example of a timing chart of the input-side timing signal generating cuvuit 5 and the output-side timing signal generating circuit 11 \ch are used for a jitter suppression circuit shown in Fig. 1 [Fig. 10] An example of a timing chart of the phase comparator 7 that is used for a jitter suppression circuit shown in Fig. 1 [Fig. 11] An example of a timing chart of the i»rameter selection circuit 8 that is used for a jitter suppression circuit shown in Fig. 1 [Fig. 12] An example of a timing chart of the numerical control oscillator 13 shown in Fig. 6 [Fig. 13] A block diagram of another example of a jitter suppression circuit according to the present invention [Fig. 14] A modification of the loop filter 9 that is used for a jitter suppression circuit shown in Fig. 1 [Explanations of Letters] [0069] 1 Clock transferring part 2 Digital phase locked loop (DPLL) 3 Oscillator 4 Serial/parallel converting circuit 5 Input-side timing signal generating circuit 6 Input-side divider 7 Phase comparator 8 Parameter selection circuit 9 Loop filter 10 D flip-flop 11 Output-side timing signal generating circuit 12 Output-side divider 13 Numerical control oscillator 14 Parallel/serial conversion circuit [Document Name] Claims 1. A jitter suppression circuit using a digital phase locked loop characterized in that shortening of a pull-in time and suppression of a jitter is achieved by determining whether the loop is in a synchronous state from a phase difference between an input clock and an out clock, and changing characteristics of a loop filter according to a determination result. 2. A jitter suppression circuit according to claim 1, comprising: a clock transferring part by which retiming of an input data is performed; and a digital phase locked loop which suppresses a jitter of an out data of said clock transferring part and an output clock by changing characteristics of the loop filter according to a determination result of whether the loop is in the synchronous state or not. 3. A jitter suppression circuit according to claim 2, wherein said clock transferring part comprises: a serial/parallel converting circuit which performs serial-to-parallel conversion of input data; a flip-flop circuit which changes timing of parallel data from said serial/parallel converting circuit; and a parallel/serial converting circuit which performs parallel-to-serial conversion of data from said flip-flop circuit, and wherein said digital phase locked loop comprises: a phase comparator which compares a phase difference between an input clock of said clock transferring part and an output clock; a numerical control oscillator which supplies a clock signal to said flip-flop circuit and said parallel/serial converting circuit; a loop filter inserted between said phase comparator and said numerical control oscillator; and a parameter selection circuit which selects and changes a parameter of said loop filter according to output of said phase comparator. 4. A jitter suppression circuit according to claim 3, wherein said phase comparator comprises: an input-side rising edge detection circuit which detects a rising edge of an input-side phase comparison signal which is generated by dividing said input clock; an output-side rising edge detection circuit which detects a rising edge of an output-side phase comparison signal which is generated by dividing said output signal; a counter which detects a phase difference by counting a period from a rising edge of said input-side phase comparison signal to a rising edge of said output-side phase comparison signal by using a sampling clock. 5. A jitter suppression method using a digital phase locked loop, wherein shortening of a pull-in time and suppression of a jitter is achieved by determining whether the loop is in a synchronous state from a phase difference between an input clock and an output clock, and changing characteristics of a loop filter according to a determination result. 6. A jitter suppression method according to claim 5, wherein a jitter of output data of said clock transferring part and an output clock is suppressed by performing retiming for an input data by said clock transferring part, and by changing characteristics of a loop filter according to a determination result of whether, in a digital phase locked loop, the loop is in a synchronous state or not.