FILED OF INVENTION
The present invention relates to electrostatic precipitators used for air pollution
control. More particularly the present invention relates to a PCI (Peripheral
Component Interconnect) based device for control and monitoring of the
electrostatic precipitator.
BACKGROUND OF THE INVENTION
Electrostatic precipitation is one of the most effective ways to control air
pollution generated by industrial emissions. This technique, which has proven
highly effective in controlling air pollution, has been used for removal of
undesirable matter from a gas stream by electrostatic precipitation. Electrostatic
precipitator (hereafter referred to as ESP) is an air pollution control device
designed to electrically charge and collect particulates generated from industrial
processes such as those occurring in power plants, cement plants, pulp and
paper mills and utilities etc. The electrically charged particles are attracted
towards electrode plates, viz., discharge electrode and collection plate. ESP is
divided into a plurality of fields depending on the dust load. During continuous
operation of an ESP, the dust from collector plates & discharge electrodes must
be periodically removed for further conveying of the collected dust.

In the ESP, the electrostatic precipitation is achieved by controlling the
transformer rectffier set by a dedicated ESP controller. An ESP installation
consists of a plurality of fields, each field being controlled by a dedicated ESP
controller. The present invention seeks to provide enhanced control and
monitoring of the ESP performance. The present invention enables monitoring
and control of the ESP through a PCI based device. The PCI based module
referred to in the present invention has a plurality of techniques to perform
communication, data acquisition and computation acceleration.
PCI based devices for performing monitoring and control of ESP operation are
not generally existing.
Further, PCI based devices of prior art are not equipped with multiple features to
perform controller area network (CAN) communication, analog interface, digital
interface and computation acceleration for enhanced ESP operation control.
Again, the PCI based device of prior art are not equipped to interface the
electrostatic precipitator controllers with the PC based control and monitoring
system
In some of the prior art, PCI based devices are however, equipped with in-built
microprocessor. The existing PCI based devices for ESP monitoring and control
are not based on core-module based CPU design.
In the prior art, the PCI based devices for ESP monitoring and control are not
equipped to communicate both over Ethernet network as well as controller area
network (CAN) communication protocol.

In the prior art, the PCI based devices for ESP monitoring and control are not
equipped to enable remote monitoring of ESP performance through a web-
interface.
OBJECTS OF THE INVENTION
It is therefore an object of invention to propose an enhanced PCI based device
for performing monitoring and control of ESP operation.
Another object of invention is to propose an enhanced PCI based device for
performing monitoring and control of ESP operation which has a plurality of
features to perform controller area network (CAN) communication, analog
interface, digital interface and accelerated computation.
A still another object of the invention is to propose an enhanced PCI based
device for performing monitoring and control of ESP operation which is based on
core-module based CPU design.
Yet another object of the invention is to propose an enhanced PCI based device
for performing monitoring and control of ESP operation that provides the
capability to communicate over Ethernet network as well as controller area
network (CAN) communication protocol.

A further object of the invention is to propose an enhanced PCI based device for
performing monitoring and control of ESP operation which has the capability of
presenting the ESP operating parameters through a web-interface.
A still further object of the invention is to propose an enhanced PCI based device
for performing monitoring and control of ESP operation which has acceleration
computation module to analyze and optimize the ESP operating parameters.
Yet further object of the to propose an enhanced PCI based device for
performing monitoring and control of ESP operation which is enabled to acquire
and analyze field signals, both analog and digital, for optimized ESP operation.
Another object of the invention is to propose an enhanced PCI based device for
performing monitoring and control of ESP operation which is enabled to interface
the ESP-controllers with the personal computer (PC) based control and
monitoring system.
SUMMARY OF THE INVENTION
The present invention provides a PCI based device for performing monitoring
and control of ESP operation. PCI (peripheral component interconnect) is a PC
bus standard founded by PCI Special Interest Group. The present invention
utilizes the core module and peripheral components for implementing the
hardware. The Core module is an intelligent processor based printed circuit
board having communication channel, digital input-output and memory.

The PCI based device referred to here above has the capability to perform
communication, data acquisition and computation acceleration. The PCI based
module consists of a PCI based card and a termination board.
The invented device has hardware circuit and the associated software to perform
controller area network (CAN) communication. The invented device can interface
with the ESP controllers that communicate over controller area network (CAN).
The invented device has hardware circuit and the associated software to perform
Ethernet network communication. The invented device has the capabilities to
present the ESP operating parameters through a web-interface.
The invented device has hardware circuit and the associated software to acquire
and analyze the field signals, both analog and digital. The field signals are
analyzed to control the ESP operating parameters to achieve optimum ESP
operation.
The invented device has the hardware circuit and the associated software to
interface the ESP controllers with the PC based control and monitoring system.
The invented device acquires the field signals and the ESP operating parameters
and furnish the same to the PC based control and monitoring system through
PCI bus.

BRIEF DESCRIPTION OF THE ACCOMPANYING DRAWINGS
Figure 1 is hardware block diagram of PCI based device.
Figure 2 is software architecture diagram of PCI based device.
Figure 3 illustrates Interfacing of the ESP controllers with a PC based control and
monitoring system using the PCI based device.
DETAILED DESCRIPTION OF A PREFERRED EMBODIMENT OF THE
INVENTION
The hardware block diagram of a PCI based device (10) for performing control
and monitoring of ESP is shown in Figure 1.
The PCI based device has a core module based processor (01).
Blocks (02), (03) and (04) represents the hardware for PCI interface circuitry.
The Block (04) is the PCI bus of the PC based control and monitoring system.
The Block (03) has the hardware for PCI interface chipsets and facilitate PC
based control and monitoring system to identify the device (10). The block (02)
has the hardware to facilitate memory access from the CPU of the PCI based
device including from the PC based control and monitoring system. The Block
(02) also has the hardware to read the analog data and digital data.

Blocks (05) and (08) consists of the hardware, which enables reading and writing
of data for both Ethernet and CAN communication. The block (05) has the circuit
for CAN communication. This circuit interfaces the CAN protocol based field level
controllers through a first port (09). The block (08) has the circuit for Ethernet
communication. The processor receives/transmit data frames through the blocks
(09), (05) and (08) and. The data is processed by the processor and transferred
to the control and monitoring system through the PCI bus (04).
7
The block (06) is the hardware for reading analog inputs. The block (07) is the
hardware for reading digital inputs.
Figure 2 shows the software architecture diagram of the present invention.
The Software architecture (19) consists of a plurality of task blocks (11), (12),
(13), (14), a driver block (15), an Operating system block (16), a hardware layer
block (17) and a PCI driver block (18).
The task blocks '(11), (12), (13) and (14) represents the CAN communication
task, Ethernet task, analog task and digital tasks respectively. The tasks are
created and initialized at the beginning of the software execution.
The block (15) consists of a driver software for the various tasks. The driver
software contains instructions to drive the hardware components.

The block (16) is the real-time multitasking operating means. The tasks are
executed based on their priority. The switching over to a lower priority task
happens once the higher priority task is executed.
The Block (17) represents a hardware layer.
The block (18) represents a PCI driver software. The PCI driver software is the
lower most layer in the PC based control and monitoring system architecture.
The layer drives the PCI components from the PC side.
Figure 3 illustrates Interfacing of the ESP controllers with the PC based control
and monitoring system using the PCI based device. The interface diagram is
shown in a block (28).
The PC based control and monitoring system containing the PCI based device is
shown in block (20).
The field level ESP controllers with CAN communication protocol (23), (24), (25)
and (26) are connected over a CAN bus (27) to the invented device (10). The
ESP controllers are interfaced with the plant level controllers through Ethernet
communication using the control and monitoring system (20). Communication
bus is terminated by using terminating resistors (21) and (22).

WE CLAIM
1. An enhanced Peripherial Component Interconnect (PCI) based device (10) for
monitoring and control of Electrostatic precipitators (ESPS), comprising:
- a core module based processor (10) for receiving and transmitting data
frames through hardware circuits (05, 08), the hardware circuits (05,08)
being enabled for Ethernet and CAN communication, the former (05)
being connected to the CAN-based filed level controllers (23,24, 25, 26)
via a first port (09), the processor (Ol)transmitting processed data via a
PCI-bus (04) to the device (10);
- one each hardware circuit (06, 07) for reading analog and digital inputs;
- a hardware circuit (02) to allow memory access from the processor (01),
and further from a PC-based control and monitoring system (20) which
incorporates the device (10);
- a hardware circuit (03) for the PCI - interface chipsets; and
- a software architecture (19) comprising a plurality of task blocks (11, 12,
13, 14), a driver block (15), an operating system block (16), a hardware
layer block (17), and a PCI driver block (18).
2. The device as claimed in claim 1, wherein the plurality of task blocks
(11,12,13/14) are enabled to create respectively the CAN communication
task, Ethernet task, analog task and digital task, and wherein the task blocks
(11,12,13,14) are capable of being initialized at the start of the software
execution.

3. The PCI based device as claimed in claim 1, comprising hardware enabling
communication over Ethernet network (08) including controller area network
(CAN) communication protocol (05).
4. The PCI based device as claimed in claim 1, comprising means for enabling
the Electrostatic precipitator (ESP) displaying the operating parameters
through a web-interface, including remote monitoring and control of the ESP
through a web-interface.

ABSTRACT

PCI BASED CONTROLLER FOR ESP
This invention relates to an enhanced Peripherial Component Interconnect (PCI)
based device (10) for monitoring and control of Electrostatic precipitators (ESPS),
comprising: a core module based processor (10) for receiving and transmitting
data frames through hardware circuits (05, 08), the hardware circuits (05,08)
being enabled for Ethernet and CAN communication, the former (05) being
connected to the CAN-based filed level controllers (23,24, 25, 26) via a first port
(09), the processor (01) transmitting processed data via a PCI-bus (04) to the
device (10); one each hardware circuit (06, 07) for reading analog and digital
inputs; a hardware circuit (02) to allow memory access from the processor (01),
and further from a PC_based control and monitoring system (20) which
incorporates the device (10); a hardware circuit (03) for the PCI - interface
chipsets; and a software architecture (19) comprising a plurality of task blocks
(11, 12, 13, 14), a driver block (15), an operating system block (16), a hardware
layer block (17), and a PCI driver block (18).