Specification Processor and Instruction Control Method
Technical Field
This application claims the priority based on Japanese patent application Wo. 2006-166077 filed on June 15,. 2006, the disclosure of which is incorporated herein in its entirety by reference.
The present invention relates to a processor and an instruction control method and, more particularly, to a processor and instruction control method which can reduce -he amount of memory consumption without degrading instruction execution performance. Background Art
In a programmable processor which fetches and executes one or more instruction words from a program memory in each cycle, ir order to improve the usage of a precious program memory resource, it is generally necessary to use a fixed instruction word length. In general, each instruction differs in a required bit count X depending on the contents of operation designation for the processor.
In general, processor operation can be designated most efficiently with instruction word length X=A+BxC+D+E [bits], where A [bits] is the bit count of an opcode, B [bits] is the bit count required to express the number of registers which can be

designated in an operand, C is a register count needs to be designated, D [bits] is the bit count of a flag modifying the operation of an instruction, and E [bits] is the bit count of an immediate field. Consider, for example, dyadic operation and monadic operation. The former is larger in C than the latter by one, and hence generally differs in the optimal word length X for each instruction or each instruction type.
Assume that only one type of fixed instruction word length Y is available. In this case, therefore, if X < Y concerning a given instruction, a space which is unnecessary under normal conditions is generated in the instruction word, resulting in the degraded usage o£ the program memory. In addition, if X > Y concerning a given instruction, the number of bits of the instruction must be decreased to match X with Y. This degrades the operation designation efficiency of the instruction for the processor. Under the circumstances, for example, Japanese Patent Laid-open No. 8-95783 (reference 1) discloses a variable-word-length programmable processor which is provided with a predetermined basic word length and simultaneously uses a plurality of instruction word lengths of integer multiples of the basic word length.
In this case, instruction set design can be performed such that the double word length is assigned to an instruction consuming a larger bit count, and the basic word length is assigned to an instruction oth^r

than such instruction. This technique therefore improves the usage of the program memory to a certain extent and facilitates implementing a high-performance processor by increasing the degree of freedom in each instruction design without impairing the merit of a fixed instruction word length, i.e., that no gap is produced in the program memory space.
In addition, for example, Japanese Patent Laid-open No. 5-150979 (reference 2) discloses a technique for a VLIW processor which has a dedicated instruction to designate the extension of an immediate field, instead of increasing the nuiaber of types of word lengths, in consideration of large differences between requests for the respective instructions with respect to the length of the immediate field. Disclosure of invention Problem to be Solved by the Invention
According to the related art disclosed in reference 1, when an instruction word length is to be set to an integer multiple nxY(n^l, 2,...) of a predetermined basic word length Y, an optimal word length X for each instruction or each type of instruction inequitably differs from a given integer multiple of the basic word length, resulting in the following problems.
That is, if a word length i x Y, of word lengths n x Y smaller than X, which is nearest to X is

selected as the word length of a given type of instruction, a bit count of X is reduced by X - (i x Y) bits corresponding to the difference between X and i x Y. This degrades the operation designation efficiency for the processor (i.e., degrades the instruction execution performance).
If a word length j x Y, of word lengths n x Y larger than X, which is nearest to X is selected as the word length of the above instruction, an extra portion of the memory area is uselessly consumed by (j x Y) ~ X bits. This degrades the program memory usage (i.e., increases the amount of memory consuinption) .
According to another related art disclosed in reference 2, even if only Che immediate field can be extended by a dedicated instruction of another word in the same cycle, this technique is one of variable length type techniques in reference 1 which has two types of instruction word lengths, i.e., a single length and a double length. Therefore, the technique also has the above problems.
It is an object of the present invention to provide a processor and instruction control method which reduce the amount of memory consumption without degradation of instruction execution performance, which is a problem in the related art. Means of Solution to the Problem
A processor of the present invention is

characterized by decomposing, at the time of execution, an information word comprising a set of some of bit fields belonging to a plurality of instruction words executed in the same cycle, and restoring each instruction word into an original arrangement.
An instruction control method of the present invention is characterized by comprising the step of causing a processor to decompose, at the time of execution, an information word comprising a set of some of bit fields belonging to a plurality of instruction words executed in the same cycle and restore each instruction word into an original arrangement. Effects of the Invention
The present invention has an effect that it can reduce the amount of memory consumption without degrading the instruction execution performance.
This is because a processor is configured to decompose, at the time of execution, an information word comprising a set of some of bit fields belonging to a plurality of instruction words executed in the same cycle and restore each instruction word into an original arrangeir,enc. Brief Description of Drawings
Fig. 1 is a block diagram showing the arrangement of the first exemplary embodiment of the present invention,-
Fig. 2 is a block diagram showing the

arrangement of the second exemplary embodiment of the present invention;
Fig. 3 is a block diagraiti showing the arrangement of an instruction decoder in Fig. 2;
Fig. 4 is a block diagram showing the arrangement of an instruction word restoration unit in Fig. 3;
Fig. 5 is a view for explaining the format of an original instruction word;
Figs. 6A to 6C are views each for explaining an example of the format of an information word;
Fig, 7 is a view for explaining the operation of the second exemplary embodiment of the present invention;
Fig. 8 is a view for explaining the operation of the third exemplary embodiment of the present invention;
Fig. 9 is a flowchart showing the operation of an instruction word restoration unit; and
Fig, 10 is a block diagram showing the arrangement of part of an instruction word restoration unit as a concrete example of the second exemplary embodiment of the present invention. Best Mode for Carrying Out the invention
The first exemplary embodiment of the present invention will be described in detail next with reference to the accompanying drawings. Fig. 1 is a

block diagram showing the arrangement of the first exemplary embodiment of the present invention. Referring to Fig, 1, a processor 100 of the first exemplary embodiment of the present invention includes an instruction decoder 103 which decomposes an information word comprising a set of some of che bit fields belonging to a plurality of instruction words executed in the same cycle (e.g., at the same pipeline stage), and reproduces the original arrangement of each instruction word.
An original first instruction word ll comprises a bit field Lll and a bit field L12. An original second instruction word 12 comprises a bit field L21 and a bit field L22. An original third instruction word 13 comprises a bit field L31 and a bit field L32.
An information word IW comprises the bit field Ll2 belonging to the original first instruction word ll, the bit field L22 belonging to the original second instruction word I2, and the bit field L32 belonging co the original third instruction word I3.
The instruction decoder 103 receives the bit field Lll as th.^^ first instruction word, the bit field L21 as the second instruction word, the bit field L31 as the third instruction word, and the information word IW in the same cycle. The first word Lll to the third instruction word L31 input to the instruction decoder

103 are obtained by respectively removing the bit fields Ll2 to L32 forming the information word IW from the original first word il to the third instruction word 13, and are also called partial instruction words.
The instruction decoder 103 then decomposes the information word IW into the bit field Ll2, the bit field L22, and the bit field L32.
The instruction decoder 103 restores the arrangement of the original first instruction word II by coiiibining the bit field Lll to the bit field L12. The instruction decoder 103 also restores the arrangement of the original second instruction word 12 by combining the bit field L21 to the bit field L,22 . The instruction decoder 103 further restores the arrangement of the original third instruction word 13 by combining the bit field L31 to the bit field L32.
In the above arrangement, the bit fields Ll^"; to L32 contained in the information word IW do not necessarily exist at the ends of the original first instruction word II to the original third instruction word 13. The bit fields L12 to L32 may exist at the starts or ends or ac predetermined positions determined depending on the types of instructions. In restoration, the bit fields Ll2 to L32 are therefore inserted at the starts or ends or at predetermined positions determined depending on the types of instructions.
Although the case of three instruction words

has been described above, the first exemplary embodiment of the present invention can be applied to n (n is an integer of two or more) instruction words.
The first exemplary embodiment of the present invention is configured to decompose an information word comprising a set of some of the bit fields belonging to a plurality of instruction words executed in the same cycle and reproduce the original arrangement of each instruction word, thereby reducing the amount of memory consumption without degrading the instruction execution performance.
The second exemplary embodiment of the present invention will be described in detail next with reference to the accompanying drawings. A processor of the second exemplary embodiment of the present invention can execute three instructions at most in the same cycle, and can also execute instructions (to be precise, original instructions) having three types of instruction word lengths. Fig. 2 is a block diagram showing the arrangement of the second exemplary embodiment of the present invention.
Referring to Fig. 2, a processor 100 of the second exemplary embodiment of the present invention includes an instruction path 101, an instruction supply unit 102, an instruction decoder 103, an instruction path 104, a control information path 105, a control information path 106, a control information path 107, an

execution unit 108, an execution unit 109, and an execution unit 110.
The instruction supply unit 102 is, for example, an instruction buffer, which stores instruction words and information words, and outputs three instruction words and an information word at most in the same cycle to the instruction decoder 103 via the instruction path 104. For example, the instruction supply unit 102 checks the information word identifier of each word. If there are one or two instruction words to be executed in the same cycle, and an information word follows (in a memory not shown), the instruction supply unit 102 shifts the information word to the end of one or two instruction words, and inserts a NOP instruction {No operation instruction) between the instruction word and the information word. The instruction supply unit 102 then outputs the result.
If the maximum number of instructions executed in the same cycle is n (n is an integer of one or more), and an information word follows the n instruction words, the instruction supply unit 102 places the information word at the end of the n instruction words, and outputs the result. If an information word follows m (ic is an integer of one or more) instruction words which are less in number than n instruction words, the instruction supply unit 102 inserts n - m WOP instructions next to the m instruction words.

The instruction decoder 103 restores the original instruction words, and outputs pieces of control information corresponding to the respective instructions to the execution units 108 to 110 via the control information paths 105 to 107 on the basis of the restoration result. Control information is, for example, information which designates operation between operands. The execution units 108 to 110 execute instructions in the same cycle on the basis of control information.
Fig, 3 is a block diagram showing the arrangement of the instruction decoder 103 in Fig. 2. Referring to Fig. 3, the instruction decoder 103 includes an instruction word restoration unit 200, an individual instruction decoding unit 201 corresponding to the execution unit 108, an individual instruction decoding unit 2 02 corresponding to the execution unit 109, and an individual instruction decoding unit 203 corresponding to the execution unit 110.
Fig. 4 is a block diagram showing the arrangement of the instruction word restoration unit 200 in Fig. 3. Referring to Fig. 4, the instruction word restoration unit 200 includes a decomposition unit 210 and a combining unit 211. The decomposition unit 210 decomposes an information word into a plurality of bit fields. The combining unit 211 restores each instruction word in-o the original arrangement by

combining a plurality of instruction words (obtained by removing the bit fields of portions forming the information word from the original arrangements of the instruction words) to the corresponding bit fields decomposed by the decomposition unit 210.
Fig. 5 is a view for explaining the format of an original instruction word. Referring to Fig. 5, an original instruction word 300 includes a basic field BF of Y [bits] and an extension field EF whose length is determined by the type of instruction. The basic field BF includes an information word identifier 303 of 1 [bit], an opcode 304 (operation code indicating the type of instruction) of Q [bits], and an operand of Y - Q - 1 [bits]. The extension field EF includes an excess operand of A [bits], B [bits], or C [bits] determined by an instruction type M, N, or 0.
The extension field EF can also include an immediate operand of EO [bits]. El [bits], or E2 [bits] determined by the instruction type M, N, or O or the like. If, therefore, an immediate operand is to be used, the word length of the original instruction word is V T A -i- EO [bits] , Y + B + El [bits] , or Y + C + S2 [bits] depending on the instruction type M, N, or 0. If no immediate operand is to be used, the word length of the original instruction word is Y + A [bits], Y + B [bits], or Y + C [bits] depending on the instruction type M, I., or 0.

The portion of the basic field BF of the original instruction word 300 of Y [bits] is isolated as an Instruction word 301. The portion of the extension field EF is contained in an information word 302. The information word 3 02 includes the information word identifier 303 of 1 [bit] and a free bit field (a combination of extension fields EF of a plurality of instruction words executed in the same cycle as the original instruction word 300) FF.
Note that whether each instruction uses an immediate operand can be designated by, for example, the bit pattern of a predetermined operand in an operand designation bit field. That is, an instruction system can be implemented such that when one of the bit patterns of operands is a specific bit pattern, e.g., a pattern of all Is, it indicates that the instruction uses an immediate operand instead of register number designation. An instruction using an immediate operand is executed such that the immediate operand is used in the self-instruction word.
The format of the information word 302 will be described next with reference to the accompanying drawings. Fig. 6A is a view for explaining an example of the format of the informacion word 302 which is one word and comprises only excess operands without including any immediate operand. Figs. 6B and 6C each are a view for explaining an example of the format of

information words 302 and 305, across which excess operands and immediate operands are used.
Referring to Fig. 6A, the information word 3 02 includes right-aligned excess operands of C [bits], B [bitsi, and A [bits] corresponding to the instruction types 0, N, and M. Note that the order of excess operands can be determined in accordance with the order of instruction words to be output from the instruction supply unit 102. Fig. 6A exemplifies a case in which instruction codes are sequentially arranged such that the code corresponding to the type M is placed first (on the left side), the code corresponding to the type N is placed second (in the middle), and the code corresponding to the type 0 is placed last (on the right side]. The same applies to the cases shown in Figs. 6B and 6C to be described later.
Referring to Fig. 6B, the information word 3 02 and the information word 305 include an excess operand of C [bits] corresponding to the instruction type 0, an immediate operand of E2 [bits] corresponding to the instruction type 0, an excess operand of B [bits] corresponding no the inscruction type N, an immediate operand of El [bits] corresponding to the instruction type N, an excess operand of A [bits] corresponding to the instruction type M, and an immediate operand of El [bits] corresponding to the instruction type M, which are right-aligned.

In this case, an excess operand or immediate operand of a given one original instruction can be divided into parts, and the parts can be included in the information word 302 and the information word 305.
Referring to Fig. 6C, the information word 302 includes right-aligned excess operands of C [bits], B [bits], and A [bits] corresponding to the instruction types 0, N, and M. The information word 30S includes i:rmediate operands of E2 [bits], El [bits], and EG [bits] corresponding to the instruction types 0, N, and K. The above are examples, and other formats can be used-
The operation of the second exemplary embodiment of the present invention will be described next with reference to the accompanying drawings. The second exemplary embodiment of the present invention exemplifies an instruction system in which three or more instructions using no immediate data are executed in the same cycle. For the sake of simplicity, the following exemplifies a case in which Y is always larger than the total of three of A, B, and C. The following concerns the information word shown in Fig. 6A.
Fig. 7 is a view for explaining ths operation of the second exemplary embodiment of the present invention. Referring to Fig. 7, the instruction supply unit 102 outputs an instruction word 4O0 of the type M, an instruction word 401 of the type N, an instruction

word 402 of the type 0, and an information word 403, each having the fixed word length Y, in the same cycle via the instruction path 104. For the sake of simplicity, the following exemplifies a case in which the information word 403 is placed at the end, i.e., on the right side of the instruction words 400 to 402.
Upon receiving the instruction words 400 to 402 and the information word 403, the instruction word restoration unit 200 of the instruction decoder 103 determines from the information word identifier 303 of each word whether each word is an information word or an instruction word.
If each word is an information word, the instruction word restoration unit 200 uses the content of the free bit field FF for the restoration of each original instruction word. If each word is an instruction word, the instruction word restoration unit 20C discriminate the type of instruction from the opcode 5 04. The instruction word restoration unit 200 then extracts an excess operand of a bit count corresponding to the type of instruction from the free bit field Fp of the information word 403 existing in the same cycle, as needed, and adds the excess operand to a proper portion ■the end in Fig. 7) of the instruction word, thereby restoring the original instruction word.
That is, the instruction word restoration unit 2JO restores the instruction words 400, 401, and 402 of

the three types M, N, and 0 into original instruction words 405, 406, and 407 of word lengths Y + A [bits], Y + B [bits], and Y + c [bits], respectively. The instruction word restoration unit 200 then outputs the restored original instruction words 405, 406, and 407 to the individual instruction decoding units 201, 202, and 2 03, respectively.
The individual instruction decoding units 201 to 203 respectively decode the original instruction words 405 to 407 and output pieces of control information for the execution of the respective instructions to the execution units 108 to 110 via the control information paths 105 to 107.
The second exemplary embodiment of the present invention is configured to decompose an information word comprising a set of excess operands belonging to a piurality of instruction words executed in the same cycle and reproduce the original arrangement of each instruction word, thereby improving the usage of the memory and reducing the amount of memory consumption without degrading the operation designation efficiency for the processor iOO.
The third exemplary embodiment of the present invention will be described in detail next with reference to the accompanying drawings. A processor 100 of the third exemplary embodiment of the present invention uses two information words and an immediate

operand, unlike the second exemplary embodiment of the present invention. The arrangement of the third exemplary embodiment of the present invention is the same as that of the second exemplary embodiment shown in Figs. 2 and 3. The third exemplary embodiment of the present invention executes three or more instructions using immediate data in the same cycle.
The operation of the third exemplary embodiment of the present invention will be described next with reference to the accompanying drawings. For the sake of simplicity, the following exemplifies a case in which Y is always larger than the total of any three of A, B, C, ED, El, and E2, and is smaller than any four of them. The following concerns the information word shown in Fig. 6B.
Fig. 8 is a view for explaining the operation of the third exemplary embodiment of the present invention. Referring to Fig. 8, an instruction supply unit 102 outputs an instruction word 500 of a type M, an iristruction word 501 of a type N, an instruction word 502 of a type 0, information word 503, and information v.'ord 504, each having a fixed word length Y, via an instruction path 104. For the sake of simplicity, the following exemplifies a case in which the information word 505 and the information word 504 are arranged at the end, i.e., the right side of the instruction words 500 to 502.

upon receiving the instruction words 500 to 502, the information word 503, and the information word 5 04, an instruction word restoration unit 200 of an instruction decoder 103 determines from an information word identifier 303 of each word whether each word is an information word or an instruction word.
If each word is an information word, the instruction word restoration unit 200 uses the content of a free bit field FF for the restoration of each instruction word. If each word is an instruction word, the instruction word restoration unit 200 discriminates the type of instruction from an opcode 304 of it. The i:istruction word restoration unit 200 then extracts an excess operand and immediate operand corresponding to a bit count corresponding to the type of instruction from the free bit fields FF of the information words 503 and 504 existing in the same cycle, as needed, and inserts Che operands at a proper position {the end in Fig. 8) of che instruction word, thereby restoring the original instruction word.
That is, the instruction word restoration unit 2JC restores the inscruccion words 500, 501, and 502 of tns three types M, N, and 0 into original instruction words 505, 506, and 507 of word lengths Y + A + EG [bits], Y + B + El [bits], and Y + C + E2 [bits], respectively. The instruction word restoration unit 200 cnen respectively outputs the restored original

instruction words 505, 506, and 507 to individual instruction decoding units 201, 202, and 203.
The individual instruction decoding units 201 to 203 respectively decode the original instruction words 505 to 507, and output pieces of control information for the execution of the respective instructions to execution units 108 to 110 via control information paths 105 to 107.
The operation of the third exemplary embodiment of the present invention will be described in more detail next. The following exemplifies a case in which instructions of the types M, N, and 0 always require information words, and one or more information words always exist in each cycle.
If, for example, one or more information words are placed at the end (right side) of a word group 800 executed in each cycle, the information words can also be used to delimit instructions to indicate whether they are instructions to be executed in the same cycle. Therefore, when less than three instruction words are to be executed in the same cycle, there is no need to separately provide, in an instruction word, any cedicated bit field expressing the number of instructions executed in the cycle. The following t'aerefore exemplifies a case in which an information \.crd is always placed at the end of an instruction group executed in each cycle.

Fig. 9 is a flowchart showing the operation of the instruction word restoration unit 200. Referring to Fig, 9, the instruction word restoration unit 200 of the instruction decoder 103 receives the word group 800 in the same cycle (step SI in Fig. 9). The word group 800 comprises instruction words executed in the same cycle S-~nd a required number of information words. Assume that the word group 8 00 has Y [bits] x 5 [words]. For the sake of simplicity, assume that Y is a constant.
The instruction word restoration unit 200 sets the fifth word (i.e., the information word) placed at the end of the word group 800 as a current word (step 32). The instruction word restoration unit 200 then performs the processing in steps S3 to S6 for the current word.
The instruction word restoration unit 200 performs the processing in steps S7 and S8 to update the current word, and sequentially performs the processing in steps S3 to S6 for each preceding word.
Upon discriminating from an information word identifier 303 that the current word is an information \:jrd (YES in suep S3), che instruction word restoration unit 200 makes preparations to use the free bit field FF cc the current word for processing for a succeeding instruction word. That is, if the current word is the first information word, the instruction word restoration unit 200 sets the current free bit field position to the

end of the free bit field FF. If the current word is not the first information word, the instruction word restoration unit 200 adds the free bit field FF of the information word at a position before the existing free bit field FF (step SIO).
Upon discriminating that the current word is nor. an information word (NO in step S3), the instruction word restoration unit 200 discriminates the type of the instruction word as the current ^ATord (step S4, S5, or So). The instruction word restoration unit 200 extracts a bit field (excess operand or immediate operand) having a bit length corresponding to the type of instruction from the current free bit field position, and adds the kit field to the end of the instruction word (current word), thereby restoring the instruction word (current v.'crd) into an original instruction word of the original word length. The instruction word restoration unit 200 updates the current free bit field position by shifting ill forward by the' bit length of the extracted bit field f-tep Sll, S12, or S13). With this operation, the instruction word restoration unit 200 restores the i.nscruction word length of each original instruction word.
The third exemplary embodiment of the present invention is configured to decompose an information word comprising a set of excess operands and imiaediate ocerands belonging to a plurality of instruction words

executed in the same cycle and reproduce the original arrangement of each instruction word, thereby improving the usage of the memory and reducing the amount of iriemory consumption without degrading the operation designation efficiency for the processor 100.
A concrete example of the first, second, or third exemplary embodiment of the present invention will be described next. A microprocessor according to this concrete example executes an instruction system including dyadic instructions (type M), monadic instructions {type N), and nullary instructions (type 0) which do not explicitly take operands. The raicroprocessor according to the concrete example always executes three instructions in the same cycle.
A bit count S of an information word idencifier is 1 [bit]. A bit count OP of an opcode is 7 [bits]. The number of registers which can be designated in an operand is 32. A bit count REG for register ciasignation which designates each register is 5 [bits] . The following exemplifies a case in which designation register counts for a dyadic instruction, a monadic i-'.struction, and a nullary instrucuion are chree \Z.'AQ sources and one destination), two (one source and one destination), and one (on destination), respectively, c-i:c a required bit count IMM of an immediate field is 1 ::" 16.
In a case in which no immediace operand is

used, the optimal instruction word lengths of a dyadic instruction (type M), monadic instruction (type N), and nillary instruction (type 0) are respectively S + OP + B-EG x3 = l + 7-f5x3-23 [bits] , S + OP + REG x 2 = 1+7+5x2= 18 [bits], and S + OP + REG x 1 = 1 + 7 - 5 X 1 = 13 [bits].
In a case in which an immediate operand is used, the optimal instruction word lengths of a dyadic instruction (type M}, monadic instruction (type N), and nullary instruction (type 0) are respectively S + OP + RHG X 3 + IMM -1+7+5x3+ 16 =39 [bits], S + OP + REG X 2+ IMM =1+7+5x2+ 16 -34 [bits], and S + 0? + REG X 1 + IMM =1+7 + 5x1 + 16 -29 [bits] .
When an instruction word length is to be determined, with importance being placed on processor performance, by using a general technique (also called related techniqiie 1) using a single instruction word l^ength, the instruction word length is set to the fixed word length 3 9 [bits] in accordance with the optimal v.ord length of a dyadic instruction which is the "congest. When an instruction word length is determined, \--"h importance being placed on processor performance, l-y using a related technique (also called related l:.5chniQue 2; see, for example, "reference 1") based on a variable-word-length scheme using two types of word l^-ji:gths, i.e., a basic word length and the double word Ij-rigth, the instruction word lengths are two types of

v:ord lengths, i.e., the basic word length 29 [bits] and the double word length 58 [bits].
In contrast to this, assume that in the concrete example of the present invention, fixed word length Y = 18 [bits], In this case, if no immediate operand is to be used (which corresponds to Fig. 7), it S'jffices to respectively set a bit count A of the excess operand of a dyadic instruction (type M with 23 [bits] as described above), a bit count B of the excess operand of a monadic instruction {type N with 18 [bits] as c-'^scribed above) , and a bit count C of the excess operand of a nullary instruction (type 0 with 13 [bits] e-2 described above} to A = 23 - 18 = 5 [bits], B ^ 18 -i3 - 0 [bit], and C = 0 [bit] (because 18 > 13). When a:'j immediate operand is to be referred to (which corresponds to Fig. 8), it suffices to set EO, El, and E2 to a maximum of 16 [bits] as well as setting A, B, and C.
In all possible instruction issuance patterns associated with the three types of instructions^ i.e., 1- K, and 0, the maximum value of the total of arbitrary e.iree values of A, E, and ~ is A. -r A + A = 5 + 5 + 5 -13 [bits]. Since this maximurr, value 15 [bits] is sLialier than fixed word length Y-l = 18-l = 17 L'";'i.t3], if instructions using no immediate operand are t-. be issued, it suffices to always issue only an ;:.-ifcrmation word corresponding to one word in each



That is, if such unused free bit field FF falls within the bit count of an immediate operand which is required for an instruction, there is no need to add c.ny new information word for the cycle. As described above, in this concrete example, even if there is an :--i.-isrruction using an immediate operand executed in the ssrr.s cycle, it is not always necessary to increase the nunber of information words.
A detailed comparison between this concrete exa:!iple and related technique 1 described above which uses a single instruction word length and related t-.ichnique 2 described above which uses variable word I'^ngrhs, i.e., two types of word lengths reveals the tollowing effects of the concrete example.
Related technique 1 always requires 39 x 3 = 1_T [bits] in each cycle. Related technique 2 requires S" [bits] (a case of three instruction words with a £hcrter word length: 29 x 3) to 174 [bits] (a case of t"i:r3e instruction words with a longer word length = 58 x ■■,. , According to this concrete example using the fixed v.-'jrd length 18 [bits], in a rare case in which three :.":;strucT:ions each siip.ulcar.eously use an immediate c.x-rand of a significant digit of 16 [bits] in the same c-'-le, 18 X (3 + 4) ^ 126 [bits] are consumed.
In this case, the above value "4" is c-\iz-\i'\ated as follows. The excess operand of one :!-:;. ,i:ruction word has 4 [bits] . The maximum value of an

iirir,ediate operand is 16 [bits] . Therefore, an information word requires (4 + 16) x 3 = 63 [bits] as a '/"aole. Since 3 < (63/17) < 4, a maximum of four -L.iformation words are required in one cycle.
Most cases require a total of four or five words including three instruction words and one or two : .^formation words, i.e., about 18 x 4 = 72 [bits] to 18 ;-- 5 - 90 [bits] .
This concrete example can therefore reduce the p?_-ogram memory consumption amount by about (117 -7:-:}/117 = 38[%] to (117 - 90)/117 = 22[%] in average as cjnpered with related technique 1. In related technique 2 if the average bit count required in each cycle is :;^0 [bits] which is the average of 87 [bits] and 174 ibi"csj , this concrete example can reduce the program n-.Tinory consumption amount by about (130 - 72)/130 = 4.'v.!;%: to (130 - 90)/130 - 30i:%] in average as compared ^■..Lth the related technique.
The arrangement of a concrete example of the is. ;Cond exemplary embodiment will be described next with r^^erence to the accompanying drawings. Fig. 10 is a 1 -zc^ diagraiTi showing Lhe arrangement of part of the :'j£truction word restoration unit 200 according to the c.-:-L";rete example of the second exemplary embodiment of tl'x-:.- present invention. Referring to Fig. 10, the :-3rruction word restoration unit 200 includes a decoder cC, a decoder 611, a decoder 612, a selection signal

(30, a selection signal 631, a selection signal 632, a selection circuit 620, a selection circuit 621, and a selecuion circuit 622.
The decoder 612 decodes the opcode of a third 1 is-ruction word 602, and outputs the selection signal 632 f3r selecting an excess operand of the third i/istruction word 602. The decoder 611 decodes the opcodes of a second instruction word 601 and the third i:isr:ruction word 602, and outputs the selection signal 631 for selecting an excess operand of the second iastruction word 601. The decoder 610 decodes the encodes of a first instruction word 600, the second :..i=:r.ruction word 601, and th'^ third instruction word I "-2, and outputs the selection signal 630 for selecting io - excess operand of the first instruction word 600.
If, for example, the third instruction is of '.'"L~ -.j,pes M, N, and 0, the decoder 612 outputs the £':T2e:tion signal 632 so as to select A [bits], B [bits], a.-ic c [bits] from the end of an information word 603.
for example, the third and second instructions are I t che type 0 and the type N, respectively, the decoder ■_■ -2 cucputs 'he seleczio— signal 651 so as to select B ^o-Lts] from a position shifted forward from the end of \:.:-: information word 603 by C [bits]. If, for example, ^■;i;-: third, second, and first instructions are of the r-"e 0, the type N, and the type M, respectively, the r-.-';:Oder 610 outputs the selection signal 630 so as to

select A fbits] from a position shifted forward from the eid of the information word 603 by B + C [bits].
The selection circuit 620 (18 wa.ys) , selection circuit 621 (9 ways), and selection circuit 622 (3 ways) r>53pectively select and output excess operands of the first instruction word 600, second instruction word 601, a id third instruction word 602 in accordance with the s.=lection signal 630, selection signal 631, and s^slection signal 632.
Although not shown, the processor 100 can have tne arrangement of a microprogram control scheme. That i:. uhe processor 100 operates in accordance with an i ii.truction control program to implement the respective iiincuion units of the instruction supply unit 102, -i-iistruction decoder 103, and execution units 108 to 110 csacL'ibed above. This instruction control program can I" ; p^rovided while being recorded on a machine-readable rh!c.Qrding medium such as an optical disk or magnetic
When n instructions are to be executed in the £ v..Le cycle, the first decoder, . . . , the ith decoder, . . . , ..-?, vi'za decoder, and the first selection circuit,..., -".e ith selection circuit,..., the nth selection circuit a,.2 required. The ith decoder receives the opcodes of v".-..-:- i"h instruction, the (i + 1) th instruction,..., the r "i ^nscruction, and outputs the ith selection signal z -.- nelecting an excess operand or immediate operand

corresponding to the ith instruction word. The ith selection circuit therefore selects an excess operand or ir:jnediate operand corresponding to the ith instruction f-rora a corresponding position in the information word in a.jcordance with the ith selection signal.
The delay time of the 18-way selection circuit t.i or the like is long. If the execution time does not i-jil within one cycle, this concrete example can be i-aplemented by increasing the number of pipeline stages.
As another concrete example, the present invention may be executed in combination with the V i.ri able-word-length instruction scheme which is related -.■"=::hnique 2. In this case, since it is possible to set ■:.ie >;ord length of an information word as a basic word l?.i-gth or another prepared word length of an integer mulciple, the program memory consumption amount can be i:-.:Lrcher reduced.
In the case of the variable-word-length scheme ■,-...-..ig two types of word lengths With the minimum word
.:/jch being Z [bits], referring to Fig. 9, only a word 1-iir-gTih Y of an information word becomes Z [bits] or 2Z '_-j..^\~_ in each cycle. In this case, it is necessary to :' iciease the bit count of the information word i. .i.^r_-:ifier 303 or separately add a bit field for c.-isiqnating a word length in an instruction word or ;.. -formation word.
As described above, the processor 100 of the

£.:jO'/e exemplary embodiment includes the instruction d"jcoder 103 which decomposes an information word comprising a set of some of the bit fields belonging to c. plurality of instruction words executed in the same c;--' le at the time of execution and restores the original a "langement of each instruction word. More i- ecifically, the instruction decoder 103 extracts bit f. elds from an information word, and inserts these bit I -=5lds at predetermined bit positions of the respective i:i3T;ruction words, thereby restoring the respective iji=truction words. In more detail, the instruction ciicocier 103 extracts bit fields from the information V, ;rd, and inserts these bit fields at the starts or ends c: "he respective instruction words or predetermined C'^:-L"ions determined depending on the opcodes of the - ;Spective words, thereby restoring the respective i::sTiLuction words.
In addition, the processor 100 includes an :..:=cruction supply unit 102 which outputs a plurality of
- UT'action words and an information word in the same :,,i-=^, an instruction decoder 103 which decodes the i .--.~p-Jtive restored insurucnion words and outputs : ;'-:-..",coi information for the execution of each .1'..-. :;..-uction word, and one or more execution units IDS to _. _ . -y/iich execute each instruction on the basis of r__'jl information.
1L the maximum number of instructioris executed

i'-: Lhe same cycle is n, and an information word follows c.ie n instruction words, the instruction supply unit 102 paces the information word at the end of the n i istructions and outputs the result. If an information vr.jrd follows m instruction words less than n instruction v:rd3,- the instruction supply unit 102 may insert n - m KO'F instructions next to the n instruction words.
In this case, some of bit fields colleted as c- - ir^^ormation word can be an excess operand or i "jviediate operand whose length is determined by the type C",: i.nstruction word. In this case, the instruction c.-cjoder 103 can include ith decoders 610 to 612 which
.-. 'eive the opcodes of the ith instruction, the (i + : , ,-■; instruction, . . . , and the nth instruction and output ■^■.e ith selection signal for selecting an excess operand c iiTiiaediate operand corresponding to the ith 1->:;;ruction word, and ith selection circuits 620 to 622 ■■ --...^h select an excess operand or immediate operand c :::re3ponding to the ith instruction from the c-^responding position in the information word in i :c'-:'raance with the ith selection signal.
Although the exejiplary embodiments and ■: .;-/.,rere examples of the present invention have been c ;;-C-:ibed in detail with reference to the accompanying c. .:-.■':-ngs, concrete arrangements to be used are not .. .'LJ. :5d to the above exemplary embodiments and concrete ■■ :-._-L-_:le3. The present invention incorporates changes in

c hsign and the like within the spirit and scope of the
i" iver.tion.
;"idu3trial Applicability
The present invention can be applied to the :. Lplernentation of a high-performance processor, e.g., a v-::^^ Very Long instruction Word) type processor, which cir. reduce the number of bits consumed by a program T:.Tinory while maintaining the performance and issue a r"-ur=ility of instructions _n a single cycle.

CLAIMS
1. A processor characterized by decomposing,
a:, the time of execution, an information word comprising
c set of some of bit fields belonging to a^plurality of
i-'istru.ction words executed in the same cycle, and
rescoring each instruction word into an original
a-i'ra:igement.
2. A processor according to claim 1,
c iaractsrized by comprising an instruction decoder which decomposes an information word at the time of execution aid restores each instruction word into an original t ...rar.gement.


5. A processor according to claim 2,
c/iaracterized by further comprising:
an instruction supply unit which outputs a p.irdlity of partial instruction words obtained by r ;:;!oving bit fields of portions forming an information v.)rd from original arrangements of the respective iii£:iruction words and an information word to said instruction decoder in the same cycle; and
at least one execution unit which executes an i. . = :..ruction on the basis of control information, wherein
said instruction decoder comprises individual i:is:ruction decoding units which decode the respective r3£"_cred instruccion words and output pieces of control i v.iormation for execution of the respective instruction '. i:Vi to said respective execution units.
6. (amended) A processor according to claim
c.._c.racterized in that said instruction supply unit c ,:.u.LS, when the maximum number of instructions ■i .-■::'.:Eed in the same cycle is n and an information word .":..D'vs n partial instruction words, outputs an
:.-___ ri-iacicn word upon placing uhe respective bit fields ■-:-. ■ e.'-d. of the n partial instruction words in accordance
",. .■.'■:. i'.ii order of the partial instruction words, and : ■i;_ics, when an information word follows partial i '.:.-. j-ccion words equal in number to m less than n, an :.-i.:o-ryfLation word upon placing n - m NOP instructions at

c. -. e.'iQ of the m partial instruction words and placing -.. e respective bit fields at the end of the NOP :■ i^::ructions in accordance with an order of the partial i.-',jtruction words.
7. A processor according to claim 1,
■: .ar-.rcerized in that a bit field forming an information V, r-.c'. ■;omprises at least one of an excess operand and an i^jiediate operand having a length determined by a type c'■ instruction word.
8. A processor according to claim 6,
;.. "'::..'acterized in that a bit field forming an information V, :.-.,: corp.prises at least one of an excess operand and an :...-.iediar;e operand having a length determined by a type c .: instruction word.
9. A processor according to claim 8,
c. L.;.rd.cterized in that said instruction decoder comprises
an ith decoder which receives, when i is an i-'^'-gsr not less than 1 and not more than n, opcodes of ■■_ .;.- -r-th partial instruction word to the nth partial : ,:;_r.LCtion words, and generates and outputs an ith
■. ^orion signal for selecting one of an excess operand :■ .-.. :._■. rrrimediate operand corresponding to an ith partial
L,i-—uction word on the basis of a type of each partial :.. ■-■ .;.\iction word, and
an ith selection circuit which selects one of -- -i vess operand and an immediate operand corresponding --.:■_ ith partial instruction word from a position

I'rresponding to an information word in accordance with :e ir.h selection signal output from said ith decoder,
10. A processor according to claim 1,
i.:-.raccerized by comprising
a decomposition unit which decomposes an .forr'iation word into a plurality of bit fields, and
a combining unit which restores each ■.ET.ruccion word into an original arrangement by .r.'ub^iiing a partial instruction word obtained by ;ir,L ing a bit field of a portion forming an information .!. o. from an original arrangement of each instruction
■ :-\ 1:0 a corresponding bit field decomposed by said
' .Tf.yosition unit.
11. An instruction control method
.... ....ccerized by comprising the step of causing a
. jcessor to decompose an information word comprising a -■".. L:: some of bit fields belonging to a plurality of .'. L_ucEion words executed in the same cycle at the time
■ -^^v-ecution and restore each instruction word into an
".\.::..^ial arrangement.
12. An instruction control method according to
.■-_..- 11, characterized in that the restoring step
1!-' --ses the step of causing an instruction decoder of -- ;. .rocessor to decompose and restore.
13 - An instruction control method according to ■-■ ■".,2, characterized in that the restoring step ■■ L3^_:S the step of causing the instruction decoder to

F ^r'.ract bit fields from an information word and restore L i~ respective instruction words by inserting the bit i_e^c.3 at predetermined bit positions in the respective j;L3truction words.
14. An instruction control method according to
■: .i-i;:: 12, characterized in that the restoring step
c :T.;:.:'_ses the step of causing the instruction decoder to e.-.cract bit fields from an information word and restore :. -:- respective instruction words by inserting the bit t e„as at any of starts and ends of the respective :. 1,-. I-ruction words and predetermined positions determined ■; .;: ^. ■ j.d ■. ag on opcodes of the respective words.
15. An instruction control method according to
; .,T.j_r,; ^\2, characterized by further comprising the steps
r
causing an instruction supply unit of the X.-.:.:. ossor to output a plurality of partial instruction ■,>■■...o..' obtained by removing bit fields of portions .. ■:.. ..L_ic an information word from original arrangements -\ii respective instruction words and an information .';■ -.G the instruction decoder in the same cycle,
causing uhe msuruction decoder to decode each -1-J:. ji;ed instruction word and output control information :. '.\ '=xeC'ition of each instruction word to at least one r ■ _:::ion unit of the processor, and
causing the execution unit to execute an ._■.■:■_■.C--ion on the basis of the control information.

16. An instruction control method according to
c" ^-;li[; 11, characterized in that the restoring step
c ..li.p-rises the steps of
decoraposiiig an information word into a f. urality of bit fields, and
coinbining a partial instruction word obtained r- .removing a bit field of a portion forming an :, -.'.-.rmation word from an original arrangement of each :. .:;z--_LGtion word to a corresponding bit field obtained h/- Cccomposition.
17. A program for causing a processor to
■,- ;:-"\j]:e the step of decomposing an information word
..iv-ismg a set of some of bit fields belonging to a \ . r.rlity of instruction words executed in the same c- c_-^ at the time of execution and restoring each i..;. iruction word into an original arrangement.
18. A program according to claim 17, which
■ -B nhe processor to execute, as the restoring step, .- ,7ceo of extracting bit fields from an information \ ::■■'- and restoring the respective instruction words by i ■. ::-cing the bit fields at predetermined bit positions :, " e respective irtstruccion words.
19. A program according to claim 17, which
r ■ -s Lihe processor to execute, as the restoring step, .- -ep of extracting bit fields from an information £i"d restoring the respective instruction words by ■.. ■ . --:ing the bit fields at any of starts and ends of