Specification
Voltage keeper based robust flip-flop for low power applications
BACKGROUND
Field of the invention
[001] The present invention relates generally to a flip-flop circuit, and more
particularly, to a voltage keeper based robust flip-flop for low power
applications.
Description of the related art
[002] A flip-flop is a basic storage element in sequential logic and is a
fundamental building block of digital electronic systems used in computers,
communications, and many other types of systems. The flip-flop is a circuit that
has two stable states, and can be used to store state information. The flip-flop
circuit can be made to change state by signals applied to one or more control
inputs and will have one or two outputs. It is desired to have a flip-flop that
consumes low power while having the capability of operating at a high speed.
[003] An existing low power D–flip–flop has the capability of operating at a
high speed. The overall components required in the construction of this flip–
flop are four inverters and four transmission gates. All the four inverters used in
this construction are built using bypass current limiting inverter, an inverter
which comprises of biasing circuitry to control the current through the pull–up
and pull–down network of an inverter during happening of logic switching.
However, said D flip-flip is constructed with an expense of about 16 MOS
transistors.
[004] In another type of CMOS D–type flip flop, the amount of dynamic power
consumed can be reduced by implementing buffered inverters for the purpose
of latching the data to the cross–coupled inverters used in master–slave D–type
flip flop configuration. Though, it has increased a small circuit overhead, but has
achieved approximately 40% reduction in dynamic power when data to the flip
flop ‘D’ is low.
[005] In another type of flip flop, the amount of dynamic power consumed is
reduced by replacing the cross–coupled inverters, tri–state inverters and pass
gates with static CMOS, thereby, eliminating the dynamic power consumption
associated with sequentially switching tri– state inverters and pass gates in
response to state transitions of the clock signal. However, the static power
dissipation (denoted as Pstatic) in the flip–flop circuit corresponds to power
consumed when the MOS transistors are in cut–off (not conducting) state.
Basically, it is a leaking power in MOS transistors. Every MOS transistor in the
flip–flop circuit has the tendency to leak during cut–off. Therefore, more
number of transistors in the flip–flop circuit corresponds to higher Pstatic.
[006] Another existing flip-flop has gated clock inversions within the MASTER
and SLAVE flip flop block itself. Therefore, there is a reduction in circuit
components leading to advantage in terms of area overhead. Moreover, this
also reduces the number of internal logic transitions by prudently selecting
circuit components, which extends in achieving considerable reduction in
overall flip flop power consumption. The flip flop construction in this prior–art
has gated clock (i.e., the clock operating the flip flop will only trigger when
there is some notable change in the input Data). Moreover, as the inverse Clock
is gated instead of the clock, there is a probability that the flip flop may have
logical conflict.
[007] Another existing flip-flop includes a smart keeper circuit. The keeper
circuit here is implanted to avoid the change of logic state at the intermediate
node between the MASTER and SLAVE half of the flip flop during evaluation
phase of the clock. Basically, the keeper circuit facilitates in retaining the logic
state in intermediate node which is captured at the pre–charge phase. As per
the structure of flip flop stated in this patent, contention current will not flow
due to keeper because the keeper will be advantageously off then and there,
when the logic of the intermediate node is uplifted. However, the insertion of
keeper circuit increases the transistor count of this flip flop design.
[008] Most of the existing flip flops are constructed with many logic blocks and
designed with huge number of transistors. This automatically instigates to a
notable amount of Pstatic and the design layout area is also quite high.
OBJECTS OF THE INVENTION
[009] It is an object of the present invention to provide a flip-flop that is
designed using least number of transistors.
[0010] It is another object of the present invention to provide a flip-flop
in which the power dissipation is suppressed during its run–time.
[0011] It is yet another object of the present invention to solve the area
complexity problem and average power dissipation issues of flip-flops within
integrated circuits.
SUMMARY OF THE INVENTION
[0012] In an embodiment of the present invention, there is provided a D-
flip-flop that includes a master latch that receives a data input signal and
generates a delayed inverted data input signal at a negative-level of a CLOCK
signal, and a slave latch that receives the delayed inverted data input signal
from the master latch circuit, and generates a further delayed data input signal
at a positive–level of the CLOCK signal.
[0013] In another embodiment of the present invention, there is provided
a D-flip-flop that includes a master latch that comprises a first pass transistor
that receives an inverted clock signal at a gate terminal, a data input signal at a
source terminal, and generates a delayed data input signal at a master latch
output terminal, when the inverted clock signal turns low; a first CMOS inverter
that receives the delayed data input signal and generates an inverted data input
signal at an output terminal of the first CMOS inverter; and a first voltage
keeper transistor that has a gate terminal for receiving an output of the first
CMOS inverter, and a source terminal connected to the master latch output
terminal, for maintaining the delayed data input signal therein. The D-flip flop
further comprises a slave latch that comprises a second pass transistor that
receives the clock signal at a gate terminal, the first CMOS inverter output signal
at a source terminal, and generates a further delayed inverted data input signal
at a slave latch output terminal, when the clock signal turns high, a second
CMOS inverter that receives the further delayed inverted data input signal and
generates a further delayed data input signal at an output terminal of the
second CMOS inverter, and a second voltage keeper transistor that has a gate
terminal for receiving an output of the second CMOS inverter, and a source
terminal connected to the slave latch output terminal for maintaining the
further delayed inverted data input signal therein. The master latch receives the
data input signal and generates the delayed inverted data input signal at a
negative-level of a CLOCK signal, and the slave latch receives the delayed
inverted data input signal from the master latch, and generates a further
delayed data input signal at a positive–level of the CLOCK signal.
BRIEF DESCRIPTION OF THE DRAWINGS
[0014] FIG.1 illustrates a CMOS inverter, in accordance with an
embodiment of the present invention;
[0015] FIG.2A illustrates a latch, in accordance with an embodiment of
the present invention; and
[0016] FIG.2B illustrates a timing diagram of input, output and clock
signals of the latch, in accordance with an embodiment of the present
invention;
[0017] FIG.3A illustrates a flip-flop structure, in accordance with an
embodiment of the present invention; and
[0018] FIG.3B illustrates a timing diagram of the input and output signals
of the flip-flop structure, in accordance with an embodiment of the present
invention.
[0019] The following detailed description of illustrative embodiments is
better understood when read in conjunction with the appended drawings. For
the purpose of illustrating the present invention, exemplary constructions of the
invention are shown in the drawings. However, the invention is not limited to
specific methods and instrumentalities disclosed herein. Moreover, those in the
art will understand that the drawings are not to scale. Wherever possible, like
elements have been indicated by identical numbers.
DETAILED DESCRIPTION OF THE EMBODIMENTS
[0020] The invention is described in detail below with reference to several
embodiments and numerous examples. Such discussion is for purposes of
illustration only. Modifications to examples within the spirit and scope of the
present invention, set forth in the appended claims, will be readily apparent to
one of skill in the art. Terminology used throughout the specification and claims
herein is given its ordinary meaning as supplemented by the discussion
immediately below. As used in the specification and claims, the singular forms
“a”, “an” and “the” include plural references unless the context clearly dictates
otherwise. Those with ordinary skill in the art will appreciate that the elements
in the Figures are illustrated for simplicity and clarity and are not necessarily
drawn to scale.
[0021] Referring now to Figures, FIG. 1 illustrates a CMOS inverter 100
that includes a PMOS 102, an NMOS 104 and is powered by a voltage supply
Vdd. The input terminal of the CMOS inverter 100 receives a clock signal 106
and the output terminal of the CMOS inverter 100 generates a proper clock
inversion i.e., clock-bar 108 by calibrating the clock signal 100. The PMOS 102
and NMOS 104 are intended to be kept in the lowest aspect ratio so as to
obtain equal rise and fall time in the clock bar 108 with respect to the clock
signal 106.
[0022] FIG.2A illustrates a latch circuit 200 having a pass transistor 202
and a voltage keeper transistor 203 and a CMOS inverter 204, coupled to the
pass transistor 202 and voltage keeper transistor 203. An example of the pass
transistor 202 is an NMOS, and an example of the voltage keeper transistor 203
is a PMOS.
[0023] The pass transistor 202 receives a data input signal (DATA-IN) at
an input terminal 205, and generates a Q–LATCH signal at an output terminal
206, while having the CLOCK signal with 50% duty cycle as a control signal at
the gate terminal.
[0024] The voltage keeper transistor 203 has a source terminal that
receives a power supply Vdd, a gate terminal connected to a CMOS output
terminal 207 of the CMOS inverter 204, and a drain terminal connected to the
output terminal 206 of the pass transistor 202.
[0025] The CMOS inverter 204 receives an input signal from the output
terminal 206, and generates an output signal at the CMOS output terminal 207
which is provided to the gate terminal of the voltage keeper transistor 203.
[0026] In operation, the latch circuit 200 operates on the positive–level of
the CLOCK signal. Likewise, the DATA-IN signal is allowed bit by bit to the latch
output 206 throughout the level high of the CLOCK signal.
[0027] Initially, the logic level at the CMOS output terminal 207 is in a
logic low state, enabling the voltage keeper transistor 203 to strengthen the Q–
LATCH output 206 to logic '1'. The voltage keeper transistor 203 holds strong
logic 1 level at the output terminal 206. The pass transistor 202 fails to transfer
proper logic ‘1’ of the input data signal to the output terminal 206. Therefore,
the voltage keeper transistor 203 helps to readily keep strength of the logic ‘1’
during data transmission.
[0028] When the input terminal 205 inserts a bit '0', it is readily passed by
the pass transistor 202 to the latch output terminal 206, as NMOS has good
susceptibility to logic '0' signal strength. As MOSFET is a symmetrical device, the
source and drain terminals are interchangeable. Thus, in order to pass Vdd
(interpreted as logic ‘1’) through the pass transistor 202 from its input node (let
say source or drain) to its output node (let say drain or source in the same
order), the gate terminal has to be logic ‘1’. The output node eventually gets
charged from 0 to Vdd. But while the output reaches Vdd–Vthn (Vthn interpreted as
the threshold voltage of an NMOS device), the Vgate–Vout (Vgate: voltage at the
gate terminal of NMOS device and Vout: voltage at the output node of the
NMOS device) becomes Vdd–(Vdd–Vthn) = Vthn. Therefore, any voltage levels more
than Vdd–Vthn at the output node will let go the NMOS device to be OFF. Like
way, it is to be noted the maximum voltage level that the NMOS output node
can be charged upto is Vdd–Vthn which logically not logic ‘1’ and thereby, it is
stated that NMOS has a good susceptibility to logic ‘0’ of any signal.
[0029] During this time, the voltage keeper transistor 203 is ON, letting
the data signal at the CMOS output terminal 207 to go in a logic high state,
which in turn disable the voltage keeper transistor 203, confirming a firm logic
'0' at the Q–LATCH output 206.
[0030] When the input terminal 205 inserts a bit '1', it is weakly passed
by the pass transistor 202 to the Q–LATCH output 206 as it is having bad
susceptibility to logic '1' signal strength. Even then, at that time, the voltage
level at the Q–LATCH output 206 is higher than the threshold voltage of the
NMOS of the CMOS inverter 204 to make it ON, letting the terminal node 207
to drain-out the charge acquired at its node capacitance to an extent which
meets the threshold voltage level of the voltage keeper transistor 203. This
turns on the voltage keeper transistor 203 to confirm a firm logic ‘1’ at the Q–
LATCH output 206. Therefore, the Q-Latch output 206 of the latch circuit 200
has the capability of holding both logic '1' and logic '0'.
[0031] The data input signal, the Q-LATCH signal and the CLOCK signals
are illustrated in detail with respect to the timing diagram shown in FIG. 2B.
[0032] FIG.2B illustrates the transient response 210 for the latch circuit
200, in accordance with an embodiment of the present invention. The data
input signal (DATA-IN) at the input terminal 205 is reflected at the latch output
terminal 206 in form of Q-LATCH signal, at every positive level of the CLOCK
signal provided to the gate terminal of the pass transistor. In this process,
switching of DATA-IN signal to Q-LATCH output suffers the propagation delays
(DATA-IN to Q-LATCH) of ΔT1 / ΔT2 / ΔT3 / ΔT4.
[0033] As per the transient response 210, the DATA–IN signal is a
random input signal given to the input terminal 205 and the CLOCK signal is a
periodic signal with 50% duty cycle with certain equal rise and fall time. The
input signal DATA–IN follows the same rise and fall time as the CLOCK signal.
Until the CLOCK positive level is achieved, the DATA–IN signal is not reflected at
the latch output terminal 206 in form of Q–LATCH signal. This incorporates
some delay in the input to output signal propagation during every change in
the DATA–IN signal. Till the time DATA–IN is not changing, Q–LATCH holds the
same voltage level similar to that of DATA–IN.
[0034] FIG.3A illustrates a D-flip–flop 300, in accordance with an
embodiment of the present invention. The D flip-flop 300 includes a MASTER
latch 302 and a SLAVE latch 303. Each of the MASTER latch 302 and the SLAVE
latch 303 is similar to the latch circuit 200 as explained with reference to
FIG.2A.
[0035] The master latch 302 includes a first pass transistor 304 that
receives a data input signal (DATA-IN) at a drain terminal, a clock-bar signal at a
gate terminal, and generates a delayed data input signal at a master latch
output terminal 306 at a negative-level of a CLOCK signal.
[0036] The master latch 302 further includes a first voltage keeper
transistor 308 that has a source terminal for receiving a supply voltage Vdd, a
gate terminal connected to an output of a first CMOS inverter 310, and a drain
terminal connected to the master latch output terminal 306.
[0037] The first CMOS inverter 310 receives a delayed data input signal
from the master latch output terminal 306, and generates an inverted delayed
data input signal at an output terminal 312 of the first CMOS inverter 310.
[0038] The slave latch 303 includes a second pass transistor 314 that
receives the delayed inverted data input signal from the master latch 302 at a
drain terminal, a clock signal at a gate terminal and generates a further delayed
inverted data input signal at a slave latch output terminal 316 at a positive–level
of the CLOCK signal.
[0039] The slave latch 303 further includes a second voltage keeper
transistor 318 that has a source terminal for receiving a supply voltage Vdd, a
gate terminal connected to an output of a second CMOS inverter 320, and a
drain terminal connected to the slave latch output terminal 316.
[0040] The second CMOS inverter 320 receives the further delayed
inverted data input signal from the slave latch output terminal 316, and
generates a further delayed data input signal at a flip-flip output terminal 322
of the second CMOS inverter 320. The input to gate terminal of the second pass
transistor 314 of the SLAVE latch 303 is a CLOCK signal so that the DATA-IN is
latched at the positive–level of CLOCK in the slave latch 303. Therefore, as a
whole, it is noted that the D-flip-flop 300 operates at the positive–edge of
CLOCK signal to transfer the data to the flip-flop output terminal 322.
[0041] In an embodiment, first and second voltage keeper transistors 310
and 320 help in maintaining strong logic levels at latch output terminals 306
and 316 of the master and slave latches 302 and 303 respectively.
[0042] The need of individual MASTER and SLAVE latches 302 and 303 is
quite crucial for the flip-flop design. Any data fed to the input terminal 305 of
the MASTER latch 302 may get captured in synchronous to the negative–level
of the CLOCK signal (i.e. positive level of CLOCK-BAR). While the MASTER latch
302 captures the input data, the SLAVE latch 303 remains inactive and holds the
previous data bit. The SLAVE latch 303 gets activated only with the positive–
level of the CLOCK signal. Therefore, the input data captured at the output
terminal 312 of the Master latch 302 traverse to the output terminal 322 of the
SLAVE latch 303 with some delay in accordance to the positive–level of the
CLOCK. This confirms the operation of positive-edge triggered D–flip–flop. As
latch is a level–triggered and flip flop is an edge–triggered storage element, the
combination of MASTER and SLAVE latches 302 and 303 is important to
generate the desired output of a D–flip–flop.
[0043] FIG.3B illustrates a transient response 302 for the D Flip-Flop 300.
It is observed that change in DATA-IN is transferred to the flip-flop terminal 322
of the SLAVE LATCH 303 is synchronous to every positive–edge of the CLOCK
signal. In that process, switching of DATA-IN signal to Q-FLIP FLOP suffers the
propagation delays (DATA-IN to Q-FLIP FLOP) of ΔT5/ΔT6/ΔT7/ΔT8.
[0044] The transient response 302 for the D Flip-Flop 300 is presented. It
is observed that DATA-IN is relayed to the output Q-FLIP FLOP with respect to
the positive–edges of CLOCK. In that process, switching of DATA-IN experience
the propagation delays (DATA-IN to Q-FLIP FLOP) of ΔT5, ΔT6, ΔT7 and ΔT8.
[0045] The D flip-flop 300 is a robust MASTER–SLAVE D Flip–Flop that is
made of 8 transistors only. Both the MASTER and SLAVE D latches 302 and 303
of the flip–flop is designed using a voltage keeper transistor replacing the use
of typical cross–coupled inverters thereby reducing its transistor count, without
disturbing the proper restoration of logic ‘1’ and logic ‘0’. Thus, this design of
the master-slave D flip–flop 300 brings in reduction of area overhead, delay and
power consumption.
[0046] While the invention has been described in detail, modifications
within the spirit and scope of the invention will be readily apparent to those of
skill in the art. Such modifications are also to be considered as part of the
present invention. In view of the foregoing discussion, relevant knowledge in
the art and references or information discussed above in connection with the
Background of the Invention, the inventions of which are all incorporated herein
by reference, further description is deemed unnecessary. In addition, it should
be understood that aspects of the invention and portions of various
embodiments may be combined or interchanged either in whole or in part.
Furthermore, those of ordinary skill in the art will appreciate that the foregoing
description is by way of example only, and is not intended to limit the invention.
We claim:
1. A D-flip-flop comprising:
a master latch that receives a data input signal and generates a
delayed inverted data input signal at a negative-level of a CLOCK signal;
and
a slave latch that receives the delayed inverted data input signal
from the master latch circuit, and generates a further delayed data input
signal at a positive–level of the CLOCK signal.
2. The D-flip-flop as claimed in claim 1, wherein the master latch comprises:
a first pass transistor that receives an inverted clock signal at a gate
terminal, a data input signal at a source terminal, and generates a delayed
data input signal at a master latch output terminal, when the inverted
clock signal turns low;
a first CMOS inverter that receives the delayed data input signal
and generates an inverted data input signal at an output terminal of the
first CMOS inverter; and
a first voltage keeper transistor that has a gate terminal for
receiving an output of the first CMOS inverter, and a source terminal
connected to the master latch output terminal, for maintaining the
delayed data input signal therein.
3. The D-flip-flop as claimed in claim 2, wherein the slave latch comprises:
a second pass transistor that receives the clock signal at a gate
terminal, the first CMOS inverter output signal at a source terminal, and
generates a further delayed inverted data input signal at a slave latch
output terminal, when the clock signal turns high;
a second CMOS inverter that receives the further delayed inverted
data input signal and generates a further delayed data input signal at an
output terminal of the second CMOS inverter; and
a second voltage keeper transistor that has a gate terminal for
receiving an output of the second CMOS inverter, and a source terminal
connected to the slave latch output terminal for maintaining the further
delayed inverted data input signal therein,
4. The flip-flop as claimed in claim 3, wherein the first and second pass transistors
are NMOS.
5. The flip-flop as claimed in claim 1, wherein the first and second voltage keeper
transistors are PMOS.
6. The flip-flop as claimed in claim 1, wherein the data input signal is a random
input signal.
7. The flip-flop as claimed in claim 1, wherein the first and second voltage keeper
transistors maintains strong logic levels at master and slave latch output
terminals.
8. A D-flip-flop comprising:
a master latch that comprises:
a first pass transistor that receives an inverted clock signal at a gate
terminal, a data input signal at a source terminal, and generates a delayed
data input signal at a master latch output terminal, when the inverted
clock signal turns low;
a first CMOS inverter that receives the delayed data input signal
and generates an inverted data input signal at an output terminal of the
first CMOS inverter; and
a first voltage keeper transistor that has a gate terminal for
receiving an output of the first CMOS inverter, and a source terminal
connected to the master latch output terminal, for maintaining the
delayed data input signal therein; and
a slave latch that comprises:
a second pass transistor that receives the clock signal at a gate terminal,
the first CMOS inverter output signal at a source terminal, and generates a
further delayed inverted data input signal at a slave latch output terminal, when
the clock signal turns high;
a second CMOS inverter that receives the further delayed inverted
data input signal and generates a further delayed data input signal at an
output terminal of the second CMOS inverter; and
a second voltage keeper transistor that has a gate terminal for
receiving an output of the second CMOS inverter, and a source terminal
connected to the slave latch output terminal for maintaining the further
delayed inverted data input signal therein,
wherein the master latch receives the data input signal and
generates the delayed inverted data input signal at a negative-level of a
CLOCK signal, and the slave latch receives the delayed inverted data input
signal from the master latch, and generates a further delayed data input
signal at a positive–level of the CLOCK signal.
9. The D-flip-flop as claimed in claim 8, wherein the first and second pass transistors
are NMOS.
10. The D-flip-flop as claimed in claim 8, wherein the first and second voltage keeper
transistors are PMOS.
