A word-line driver (122-1) included in a memory is described herein. The word-line driver (122-1) is configured to drive a word-line. The word-line driver includes a first transistor(202-l), a second transistor (202-2) and a third transistor (202-3). The first transistor (202-1) includes a gate terminal driven by a ...

The present invention provides a memory with reduced bitline leakage current and method for same. Reducing bitline leakage current thereby provides more split at sense amplifier node and hence results in more speed. A negative voltage is generated and applied to the access transistors of unselected wordlines which r...

This invention relates to a Programmable Logic Device (PLD) and Programmable Gate Array (PGA) providing readback of configuration data. It comprises an input data selector having one input connected to the output of the configuration memory, the output of the input data selector being connected to an input data regi...

The present invention provides a programmable logic device comprising: programmable interconnect structure, a plurality of configurable logic elements including data latches interconnected by said interconnect structure, at least one of said configurable logic elements being configurable as both a shift register an...

The present invention provides an area efficient distributed device for integrated voltage regulators comprising at least one filler cell connected between a pair of PADS on I/O rail of a chip and at least one additional filler cell having small size replica of said device is coupled to said I/O rails for distributi...

The present invention provides a low power content addressable memory circuit comprising a storage means, a comparison enabling means connecdted to the output of said storage means, a searching means for initializing searching data from said storage means. A match or mismatch detection means receiving response from ...

An improved Programmable Logic Device architecture that provides more efficient utilization of resources by enabling access to defined circuit elements in the domain of any Programmable Logic Block (PLB) from any other PLB in the device, by incorporating a connecting means in the routing structure for selectively co...

The instant invention provides digital delay locked loop architecture, which is independent of feedback delay (clock tree delay). The architecture employs a frequency detector circuit, which monitors the frequency of input clock and then sets the division factor for the clock going to the control block to have fast ...

The present invention relates to a system for rapid configuration of reconflgurable devices with a plurality of latches. The number of clock cycles for loading the configuration data are reduced by a substantial amount and the fidelity of data loaded into the configuration latches is high. The invention also incorpo...

The I2C bus is a synchronous serial data two-wire communications bus, which can transfer data at rates up to 100 kbit/s (standard mode), 400 kbits/s (fast mode), or 3.4 Mbit/s (high-speed mode). The load of I2C bus can vary from 10pf to 400pf. The data transfer on the I2C bus take place through the IOs used t...

An offset free sine interpolating filter (114) includes differentiators (202) operating at a first sampling frequency, integrators (206) operating at a second sampling frequency and one or more coefficient multipliers (204). The coefficient multipliers (204) multiply an input value with a constant coefficient value ...

The present invention provides an improved Look up table apparatus to perform two bit arithmetic operation including carry generation. The look up table is modified, so that it can perform two concurrent combinatorial functions or one function for increased number of inputs. This look up table can implement two full...

The present invention provides a Programmable Logic Device (PLD) incorporating a 2-input multiplexer providing the Cascade Logic output and having the Cascade Logic input coupled to its select line with a 2-input multiplexer providing the desired configurable Cascade Logic function, and an initialization circuit tha...

The present invention provides in an electronic circuit containing one or more digital synchronous sequential logic blocks at least one of which is either selected or deselected during operation, an improved clock distribution scheme that reduces power consumption, comprising identifying means for determining the se...

This invention relates to a linear scalable method for computing a Fast Fourier Transform (FFT) or Inverse Fast Fourier transform (IFFT) in a multiprocessing system using a decimation in time approach. Linear scalability means, as the number of processor increases by a factor P (for example), the computational cycle...

This invention relates to an improved fractional divider that comprises an integer value storage means containing the integer part of the division value 'K' connected to the input of a programmable counter means that is configured for a count value of 'K' or 'K+l' depending upon the state of a count control signal a...

The present invention provides a structure for simplifying the programmable memory to logic interface in FPGAs is proposed. The interface is such that it isolates the general purpose routing architecture for intra-PLB (Programmable Logic Blocks) routing from the RAM address, data and control lines. The programmable ...

This invention relates to a system and method for providing improved resolution in the measuring the pulse width of digital signals comprising counting the integral number of measuring clock pulses covered by said digital pulse and triggering a chain of cascaded high resolution delay elements from the trailing edge ...

The present invention relates to a method and system for measurement of timing skew between two digital signals comprising clock generation means for generating time measurement clock and, pulse-to-digital-converter means for converting the timing skew into an equivalent digital coded value after correcting for inte...

This invention relates to an improved Capacitor Discharge Ignition (CDI) system capable of generating intense continuous electrical discharge at spark gap for any desired duration, characterized in that it includes a second controllable power switching means with its input terminal connected to the output terminal o...

This invention relates to a method and an improved apparatus for clock recovery from data streams containing embedded reference clock values characterized in that controlled clock source means consists of a controllable digital Fractional Divider means receiving a control value from digital comparator means and a cl...

A system and method for testing of faults in a shadow logic is described herein. In an embodiment, the system includes a sequential block (112) coupled to a shadow logic block (116). The system includes a delaying block (114) to receive test patterns (120) for testing the shadow logic block (116). The delaying block...

An adaptive temporal motion filter (102) for a video decoder system (100) is described herein. The adaptive temporal motion filter (102) operates in an infinite impluse response (IIR), a max or a bypass mode. The adaptive temporal motion filter (102) includes an adaptive time constant control module (110) and a filt...

An image processing arrangement comprising: an input configured to receive at least one indicator of a power characteristic related to the image processing arrangement; and an image processor configured to process an image based on the at least one indicator of the power characteristic.

The present invention discloses a system and method for reducing the re-lock time of a phase locked loop (PLL) system. The circuit 100 includes a capture control voltage module 104, a force control voltage module 106, a loop filter module 110, and a tinier 112. The capture control voltage module 104 compares the con...

A novel method of handling interrupts generated in a system is introduced by the present invention. A processor known as Interrupt Processor is provided in the embedded system. The function of interrupt processor is to handle interrupts and execute interrupt routines. It performs code execution for,interrupts which ...

A semiconductor memory device comprises of a control circuit, decoder circuit, a normal memory cell array, and a dummy column. The memory array is divided in clusters of N consecutive rows where N can be one or more than one. For each cluster of N rows a common circuitry is used in block. A dummy bit line is connect...

A self-timing write architecture for semiconductor memory and a method for providing the same are provided. The core region of the semiconductor memory comprises of a normal memory cell array and a dummy column. The dummy column comprises of two blocks - block A and block B. Block A is composed of a cluster of N dum...

The present invention provides a read only memory (ROM) for providing a high operational speed with reduced leakage and low power consumption. The read only memory (ROM) includes multiple bit lines, multiple word lines, multiple column select lines and these lines are operatively coupled with multiple transistors. T...

A phase locked loop (PLL) architecture for providing voltage controlled oscillator (VCO) gain compensation across process and temperature variations by providing additional circuitry around the oscillator. A simulator is used to calculate the control voltages for the maximum and minimum output frequency of the VCO f...

The present invention provides an immproved voltage translator circuit for low level to high level voltage translation, having minimum power dissipation, comprising a plurality of transistors coupled to an inverter for receiving a common input signal at input node of said plurality of transistors and passing the tra...

The invention provides a Bit Map Analysis System (BMAS) for high-speed memory testing. The solution provided throught this strategy is a worty using inside the embedded memories irrespective of whether they are asynchronous or synchronous, static or dynamic, volatile or non-volatile as reduces the amount of data tra...

The present invention provides a configurable length First-in First-out memory comprising a memory core for storing the data; a write address counter connected to said memory core for counting the locations for writing the data; and a read address counter connected to said memory core for counting the locations for ...

The present invention discloses a system and method for the channel selection in a digital broadcast reception terminal. In one embodiment, on receiving the user instruction, the system sequentially tunes to different frequencies and generates very short visual clips of just a few frames corresponding to all the cha...

The present invention provides a methodology for efficiently copying of data. An internal controller RAM is multiplexed between an existing RAM data and a copy back operation RAM. The data in the controller RAM is temporarily stored in a free space. The data of the internal RAM, which is to be copied, is read from a...

The present invention provides a system and method for adaptive rrequerteyscaimg lor predicting the load on the processing unit and dynamically changing its clock frequency while keeping the synchronization with other processing units. The amount of data in the input memory waiting to be processed is a good indicato...

The present invention provides an integrated scanable interface for testing memory, comprising a selection means for selecting a signal from at least two input signals responsive to an activation signal, a first means coupled to the output of said selection means for storing said signal responsive to a first enable ...

The instant invention describes a system for maintaining the integrity of data transfers in shared memory configuration by different processes to a data buffer located in the contiguous memory locations. The accesses by the different processes can be at the same time. The proposal has been developed for a system emp...

This invention relates to an area efficient data shifter/rotator using barrel shifter. The invention is a circuit, which uses a single barrel shifter and is controllable to implement either a left or right shift or rotation of bits of a digital data word. The circuit is dynamically controllable to implement left or ...

The present invention provides an improved interconnect structure in programmable devices, which gives a new dimension to the routing architecture, where architecture is divided into various domains. It comprises of atleast one set of input lines, each said set having predetermined number of said input lines; and eq...

According to the present invention an apparatus and method for providing compensation against temperature, process and supply voltage variation in MOS circuits has been proposed. The invention provides a change in process, temperature and voltage detection circuit, which controls the body bias and the drive of the d...

The present invention provides a self test structure for interconnect and logic element testing in programmable devices comprising plurality of said logic elements; an interconnect structure for connecting said logic elements; SRAM based configuration latches for configuring said interconnect structure; characterise...

The present invention provides a system for dynamic power management in a distributed architecture system on chip, comprising a means for dynamically defining the feasibility of entering a low power mode of operation based on the status of components of the system, a means for entering or exiting safely from a low p...

The present invention provides a low noise output buffer capable of operating at high speeds. High-speed I/O buffers require delicate handling of the noise on the supply buffers; this requires the control of current slew rate not only on the rising edge of current but also on the falling edge of the current. A novel...

This invention relates to a Spread Clock Generation system. In particular it relates to a spread spectrum clock generation system that provides both Center-spread and Down-spread operating modes and requires minimal silicon area for on-chip implementation.SYSTEM"

The instant invention provides memory system incorporating shared redundant memories and shared redundant memory architecture. More particularly, the instant invention discloses a modified memory to be used as a shared redundant memory between memory systems. These memory systems may have several smaller memories fo...

The instant invention provides a video decoder receiving an encoded bit stream a header decoder for receiving said encoded bit stream; a variable length decoder connected to said header decoder receiving the header decoded data; a quantizer and compensator connected to said variable length decoder during backward de...

The present invention provides an SRAM cell for reducing gate and sub-threshold leakage currents in the SRAM cell. The SRAM cell is designed to include eight operatively coupled transistors to reduce leakage currents irrespective of data stored in the SRAM cell. The transistors lower the effective supply volt...

The various embodiments of the instant invention disclose a system and method for efficient detection and restoration of data storage array defects where a system according to an embodiment of the invention comprising a data storage subsystem, wherein said data storage subsystem comprises a data storage array (301),...

The present invention discloses an apparatus and method for measuring time interval between two selected edges of a clock signal. The apparatus includes an edge generator, a first multi-tap delay module, a second multi-tap delay module, and a multi-element phase detector. Edge generator produces a first edge at a fi...

The present invention provides a buffer circuit for providing constant impedance to a transmission line in an integrated circuit. The buffer circuit includes an output terminal, an input terminal, a power supply terminal, a virtual voltage terminal, a first switching element, and a second switching element. The inpu...

The present invention provides a brushless motor circuit for driving a brushless direct current (BLDC) motor. The motor includes a rotor and exciting coils for respective phases wounded in a three phase winding in a star configuration. A neutral point in the star configuration is configured to switch to one of a gro...

The present invention provides a methodology and a circuit for measuring maximum operating frequency and its corresponding duty cycle for an input I/O cell under test (IUT), the frequency obeying the specified limits of Upper voltage threshold, lower voltage threshold and duty cycle. The circuit is synchronized with...

The present invention discloses an apparatus and method for measuring the duty cycle of a clock signal. Apparatus includes a first multi-tap delay module, a second multi-tap delay module, and a multi-element detecting module. The input terminal of the first multi-tap delay module and the input terminal of the second...

ABSTRACT The present invention provides a sense amplifier circuit for providing a high speed sensing with a high speed read operation, with a low capacitance and a low resolution time. The sense amplifier circuit includes a latch circuit having a first inverter circuit and a second inverter circuit cross coupled wi...

The present invention provides a flexible on-chip testing circuit and methodology for measuring I/O characterization of multiple I/O structures. The testing circuit includes a register bank, a central processing controller (CPC), a character slew module, a delay characterization module, and a character frequency mod...

The proposed memory chip configuration aims at reducing the bitline leakage in standby as well as dynamic operation mode. The chip design comprises of- a nxm FET matrix, vertically mnning bitlines - each shared by a column in the array, horizontally mnning wordlines - each shared by a row in the array, horizontally ...

A system and method for multiple phase clock generation is disclosed. The disclosed multiple phase clock circuit comprises of a multiple stage voltage controlled oscillator (VCO) and multiple clock dividers. The voltage controlled oscillator (VCO) is made to operate at frequency "N" times higher than the required ou...

.  A melt or solution processable polyaniline which comprises polyaniline doped or protonated with a dopant of the formula (1), (2) or (3) shown below said, melt or solution processable polyaniline having the following characteristics : a. conductivity ranging between 3 to 60 S/Cm b. high solubility in weak polar...

The present invention provides a memory architecture for image processing comprising a memory array having multiple multi-byte memory data paths of equal multi-byte data width, and a multiplexing structure connected to the output of said multiple multi-byte data paths, capable of selectively providing a multi-byte d...

The present disclosure provides an emulator mapping process on a system-on-a-chip (SoC) for debugging. The implementation reduces manual intervention and makes the emulation mapping process very generic and technology independent and hence it reduces overall project cycle time. In the present disclosure, the SoCs co...

The present invention provides a circuit and a method for an automatic coarse tuning in a phase locked loop (I"LL). The methodology observes a variation in a control voltage to disable a fine loop and to enable a coarse loop as the control voltage departs from a specified range. The circuit includes the fine loop, t...

An apparatus for enabling duty cycle locking at the rising / falling edge of the clock comprising a counter receiving a gated input clock; a lock detector receiving an input clock for generating control signals; an address decoder connected to said counter for generating set of selection signals; a first multiplexer...

This invention relates to configurable memory architecture with built-in testing mechanism integrated in said memory to support very efficient buit-in self-test in Random Access Memories (RAMs) with greatly reduced overhead, in terms of area and speed. Memories can fail at high speed due to glitches (unwanted pulse...

The present invention describes a novel technique for reducing the bitline leakage current and at the same time, maintaining a level of performance characteristics of low threshold voltage transistors in deep submicron CMOS technology. The present invention incorporates the reference voltage generator circuit in com...

An efficient Content Addressable Memory array for Classless Inter-Domain Routing with each CAM cell comprising an additional storage means for storing the prefix length associated with the contents of said cell; an enabling logic for connecting said prefix length value to a wired OR plane common to all CAM cells; a...

The present invention discloses an output buffer circuit for improving an output of such buffers during state transitions. The circuit generates variable output impedance proportional to the load transmission line impedance. The buffer includes an output stage, such as pull up / pulls down drivers for receiving an i...

The present invention provides a built-in self-test (BIST) device for testing multiple embedded memories of different characteristics. The BIST includes a BIST controller, a delay generator, multiple interface modules, and a memory wrapper. The BIST controller generates an initialization sequence and a memory test a...

ABSTRACT NOT FILED

ABSTRACT NOT FILED

The present invention provides a differential input receiver, with hysteresis on both sides of the reference voltage using only small transistors. It comprises a 2-input, 1-output differential amplifier consisting of 2 input transistors having a common terminal coupled together with the control terminal of each tran...

A novel method for introducing delays in self timed memories is disclosed. In the proposed method, delays are introduced by introducing a capacitance on the path of signal to be delayed. The capacitances are realized by using idle lying metal layers in the circuit. The signal to be delayed is connected to these idle...

This invention provides a method and an improved FPGA apparatus for enabling the selective deployment of unused flip-flops or other circuit elements in IO cells and unused decoders or other circuit elements in Look Up Tables (LUT), for core logic functions, comprising disconnecting means for selectively disconnectin...

The present invention provides a phase-shift enable and disable signal generator connected to configuration bits at its first input and connected to a reset signal at its reset input for generating a control signal, said configuration bits corresponding to the phase shift required, a logic signal generation device c...

The present invention relates to an efficient method and electronic circuit for initializing latch arrays in an electronic device including an FPGA and a memory device comprising a group of one or more data latches, each consisting of a pair of cross-coupled inverting logic elements, characterized in that it include...

This invention relates to a method for reducing offset voltage in an operational amplifier without the need for switched-capacitors, comprising the steps of introducing a tapped resistor chain between the common connected terminals of the transistors of the input differential pair of the operational amplifier and co...

This invention provides a Content Addressable Memory (CAM) architecture providing improved speed by performing mutually exclusive operations in first state of a clock cycle and by performing at least one operation, dependent on at least one previous operations, in the second state of the same clock cycles. The Conte...

The present invention provides a glitch free controlled ring oscillator comprising a programmable delay chain connected to a gating and inveriting means wherein a latching means is provided between said delay chain and said gating and inverting means for registering the clock state at the time of disabling the oscil...

The current invention is an improved input buffer for CMOS integrated circuits using sub-micron CMOS technology. The devices in sub-micron CMOS technology are affected by the presence of high voltage between various ports of a device. The invention provides input voltage limiting circuit resulting high voltage toler...

The present invention relates to an improved pass gate multiplexer comprising a decoder for selecting one out of a plurality of pass gates characterized in that it includes a weak pull up at the output of said multiplexer for providing a defined logic level when all the pass gates are deselected and means for enabli...

The present invention discloses a high voltage switching module having reduced stress at its driver output stage which in turn controls the gate of a transistor requiring a high current drive. The switching module includes a negative elevating circuit, a delay module, two separate pull-up circuits, and a pull down c...

The present invention provides an area efficient system for providing serial access of multiple data buffers to a data retaining and processing device, comprising a signal synchronization and detection means for synchronizing a clock signal and a data signal, a shifting means for receiving and retaining data receive...

The invention relates to an improved phase locked loop (PLL) circuit for preventing erroneous condition in the charge pump operation. The invention includes modification in the PLL circuitiy by adding delay elements for connection between the phase frequency detector and the charge pump and a digital logic circuit f...

The present invention provides a CMOS output buffer which makes use of feedback from ground node to reduce ground bounce by properly exploiting the tolerable ground bounce limit and making it less sensitive to operating conditions and processing parameters. Input to the NMOS of the output buffer comes from the outpu...

The present invention relates to a system and method for enabling rapid partial configuration of reconfigurable devices, comprising configuration definition means for defining the partial configuration requirements, containing at least one set of starting address of configuration data for said partial reconfiguratio...

This invention relates to a programmable glitch filter comprising a storage means for storing a current state, which is the output of the said filter, the output of said storage means is connected to one input of a state comparator and the other input of the said state comparator is connected to the input signal, a ...

A method for identifying non stuck-at faults in a read-only memory (ROM) (110) includes generating a golden value of a victim cell, providing a fault-specific pattern through an aggressor cell, generating a test reading of the victim cell in response to the provided fault-specific pattern, and determining whether th...

This invention relates to a digital clock generator circuit with in-built frequency and duty cycle control comprising: pulse generator block for generating a start pulse, the said pulse generator is connected to a ring oscillator block to generate multiple signals of a specified frequency and programmable duty cyc...

This invention relates to a synthesizable, synchronous static RAM comprising: custom built memcells and a semi-custom IO / precharge section in form of bit slice, a semi-custom built decoder connected to said bit slice, a semi-custom built control clock generation section, which is connected to said semi-custom b...

The present invention provides a low pin interface module for testing an integrated circuit. The interface module including an input-output module, a controlling module, a processing module and a storage module specific to the integrated circuit to be tested. The interface module reduces required number of hardware ...

The embodiments of the present disclosure teach a file system to manage multiple files in a storage subsystem by optimum utilization of the area of the storage subsystem. A system comprising such a subsystem according to an embodiment of the present disclosure comprises a data area and a header area. The data area s...

Systems and methods for a write circuitry for a memory architecture 200 are described herein. In one embodiment, the memory architecture 200 comprises a plurality of local input and output circuitries 204. Each LIOC is associated with at least one memory bank. The memory architecture 200 further comprises a global i...

Implementations of power management in a device are described. The device includes a power driver 120 configured to manage power supply to one or more components in system-on-chip (SOC) hardware 310. The device further includes power subsystems 308 configured as drivers for controlling the components of the SOC hard...

A device and a method for a sense circuit (200) have been disclosed. In an implementation, the sense circuit (200) includes a sense amplifier (122) and at least one decoupling device (206, 208). The decoupling device (206, 208) is coupled to the sense amplifier (122) through at least one reference line (202, 204). T...

The present invention discloses a system and method for macroblock mode mapping tor transcoding video standards from one format to another. A cascaded pixel domain transcoder (CPDT) for transcoding is disclosed. The CPDT includes a MPEG-2 decoder module, a shared frame buffer, a shared MB information buffer and a VC...

The present invention discloses an amplifier for controlling an offset voltage between its input nodes. The amplifier includes a current generator, a current mirror, and a differential amplifier. The current generator generates a reference current (Iref) by receiving a reference voltage (Vref). The current mirror in...

The present invention discloses a system and a methodology for enhancing pertormance during wireless Communications by reducing system latency and power consumption. The present invention discloses a system and method of wireless data communication in which part of upper layer stack processing is performed on a wire...

An improved multi-wordline memory architecture providing decreased bitline coupling for increased speed and reduced power consumption comprising an interleaving arrangement for connecting adjacent bitcells to different wordlines, coupled to,a multiplexing arrangement for sharing bitlines of adjacent bitcells. ...

This invention relates to a Programmable Logic Device (PLD) incorporating the ability to test the configuration memory either independently or during configuration, comprising a selector for selecting a particular column or row of the configuration memory array, an input data store for storing configuration data req...

The present invention provides a scheme for peripheral routing that provides symmetrical routing across its entire area including the periphery by incorporating peripheral routing lines of equal length that are symmetrically deflected orthogonally. The symmetrical peripheral routing lines are connected to switch box...

A Programmable Logic Device (PLD) incorporating a plurality of Programmable Logic Blocks (PLBs) providing enhanced flexibility for Cascade logic functions, each comprising a multi-input Look Up Table (LUT) providing one input to a Cascade Logic block for implementing desired Cascade Logic functions. The other input ...

An adaptive biasing technique is presented to improve fully differential gain boosted operational amplifiers transients and to reduce power consumption. Presented technique helps in incorporating the advantages of single ended gain boosters together with fully differential gain booster. It also helps in threshold in...

This invention relates to an integrated Low Dropout (LDO) linear voltage regulator providing improved current limiting, comprising a 2-input, 1-output difference voltage amplifier consisting of a differential pair and a reference voltage source connected to a first input of the difference voltage amplifier. The inve...

This invention relates to a high performance interconnect architecture providing reduced delay minimized electro-migration and reduced area in FPGAs comprising a plurality of tiles consisting of interconnected logic blocks, that are separated by intervening logic blocks. Each set of interconnected logic blocks is li...

The present invention relates to a Programmable Logic Device providing efficient scalability for configuration memory programming while requiring reduced area for implementation, comprising: an array of configuration memory cells, a Vertical Shift Register (VSR) connected to the vertical lines of the array of config...

The present invention provides a built-in self-repairable. The invention repairs the faulty IC through hard fuses, as well as through available redundancy in memories on chip. As the faults are not present in all the memories, the invention uses lesser number of fuses to actually make a perfect repair and thus resul...

The invention provides a system and method for generating pulse width modulated signal having variable duty cycle resolution. It provides a hardware solution using minimal hardware to improve the PWM duty cycle resolution up to 0, such that highest possible resolution of a waveform can be obtained including sine wav...

The present invention provides an improved configurable logic device providing enhanced flexibility, scalability and providing area efficient implementation of arithmetic operation on (N-1) bit variables comprising a first configurable logic subsystem capable of generating logic OR output in response to functions of...

The present invention provides an efficient method for mapping a logic design on Field Programmable Gate Arrays comprising the steps of determining the minimum required square grid of FPGA logic blocks for mapping said design, providing a compensation factor on said minimum square grids, and selecting the maximum va...

The present invention provides a low power content addressable memory system comprising an array of content addressable memory cells organized as a plurality of equal sized cam cell groups, each cam cell group having one or more cam cells;a valid entry tag bit associated with each said content addressable memory cel...

The present invention provides an integrated circuit including at lest one configurable logic cell capable of multiplication comprising an addition means for adding a first input and a partial product, a first multiplexing means for receiving a first output of said addition means at its first input and said partial ...

A system for reducing the number of programmable architecture elements in a look-up table required for implementing Boolean functions or operations that are identical or logically equivalent wherein a single set of storage elements connected to the inputs of multiple decoders and said storage elements being concurre...

The present invention provides a structure for simplifying the programmable memory to logic interface in FPGAs is proposed. The interface is such that it isolates the general purpose routing architecture for intra-PLB (Programmable Logic Blocks) routing from the RAM address, data and control lines. The programmable ...

The present invention relates to an improved phase locked loop (PLL) comprising a frequency multiplier including a Voltage Controlled Oscillator (VCO) characterized in that said VCO includes a control circuit for automatically adjusting its initial free-running frequency in response to changes in said integer divide...

This invention relates to a Programmable Logic Device providing reduction in power consumption for sequential logic and data storage functions, comprising at least one circuit arrangement configurable to function as. a dual-edge-triggered flip-flop operating on a selected one or both edges of the circuit clock. ...

The present invention provides a system and method for a fast clock recovery in digital video transmission. The invention utilizes a new clock recovery algorithm to overcome clock recovery problems in the presence of PCR packet jitters in a digital video communication. The proposed clock recovery algorithm has a min...

The present invention provides a resistance multiplication circuit coupled at a first node to provide a high resistance value. The resistance multiplication circuit includes a resistor, a MOSFET, and an operational amplifier (op-amp). The MOSFET can either be a NMOS transistor or a PMOS transistor. The resist...

The present invention provides a memory array for providing leakage reductions with a noise margin control over process corners is provided. The memory array enables to maintain data with reduced voltage across the skewed process corners, which otherwise cause data instability. The memory array includes an array ...

The present invention provides a digital radio frequency (RF) modulator for providing modulation for base-band TV signals. The RF modulator provides direct conversion of digital base-band audio and video signals to a desired RF channel frequency, without any analogue up conversion. The RF modulator in the present in...

The present invention provides a dual port static random access memory (SRAM) having dedicated read and write ports to provide a high speed read operation with reduced leakages. A dual port SRAM includes at least one write word line, at least one read word line, at least one pair of write bit line and read bit line,...

ABSTRACT NOT FILED

The present invention provides a circuit and method for improving matching characteristics with an improved response time. The circuit includes a first pre-charge module, a first multiplexer module, a second pre-charge module, a second multiplexer module, a sense amplifier circuit, a third pre-charge module, an outp...

The present invention provides a compensated output buffer circuit providing an improved slew rate control and a method for minimizing the variations in the current slew rate of the buffer over process, voltage and temperature (PVT) conditions. The output buffer circuit includes a split-gate compensated driver and a...

The present invention provides a system and method for minimizing computations required for compression of motion video frame sequences wherein processing requirements are reduced, the reduction being dependent on the content being processed. The method performs motion estimation of a current video image using a sea...

The present invention provides a level shifter circuit capable of high frequency operations. The level shifter circuit utilizes a dynamic charge injection device, which diminishes a capacitive coupling effect between a gate and a drain of input NMOS devices, when the input signal switches from a high logic le...

The present invention provides an improved Finite Impulse Response (FIR) filter providing linear scalability and implementation without the need for delay lines, comprising, a multiprocessor architecture including a plurality of ALUs (Arithmetic and Logic Unit), Multipliers units, Data cache, and Load/Store units sh...